From nobody Mon Apr 29 12:55:39 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1575897064; cv=none; d=zohomail.com; s=zohoarc; b=bJtMGu2vJjS6OwOAuMaKKoKC/2n+Pf92hrz4TZqsZU4pMmQtvs72KuSnlQyyioBc66klb0woEMP6OYz7xIBcddyNLnkplOMkiWtql/FTcn4Np5PRAWx5+61Rzuwxee31aM34XbOvkSshNHqSKp1s5UZ1EnpjsnaC4XWrqv3Rvjo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1575897064; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To; bh=cioeW4SSr09ObvzRXUyDz1xqJxs21g3MnA23WRs94Qw=; b=XEJ7d3wWeDl/mCySBA6Zh/fD5PJkS3mjaP7eGnE7iQN/Gkmuju6q2AclrZJQNkKAhk0f+KUBSQUUhwxBk48LDO21Q8xawHEWadFjAx6SgTJ0rne5C6+bZ6ONsITt7VuG2e9L0iyftjLQf5+XULWuXr/A0Qx+oxC6rSEKoW2Dwv4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1575897064964922.4432709727274; Mon, 9 Dec 2019 05:11:04 -0800 (PST) Received: from localhost ([::1]:39882 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ieIoZ-0008CX-9E for importer@patchew.org; Mon, 09 Dec 2019 08:11:03 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:44963) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ieImd-0006Lo-1o for qemu-devel@nongnu.org; Mon, 09 Dec 2019 08:09:04 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ieImb-0006Jj-Hy for qemu-devel@nongnu.org; Mon, 09 Dec 2019 08:09:02 -0500 Received: from us-smtp-2.mimecast.com ([205.139.110.61]:51325 helo=us-smtp-delivery-1.mimecast.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ieImb-0006Gf-Db for qemu-devel@nongnu.org; Mon, 09 Dec 2019 08:09:01 -0500 Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-206-k8nQjiTnOnaPWTasmCgw9g-1; Mon, 09 Dec 2019 08:08:59 -0500 Received: from smtp.corp.redhat.com (int-mx04.intmail.prod.int.phx2.redhat.com [10.5.11.14]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id 4175E1005502 for ; Mon, 9 Dec 2019 13:08:58 +0000 (UTC) Received: from dell-r430-03.lab.eng.brq.redhat.com (dell-r430-03.lab.eng.brq.redhat.com [10.37.153.18]) by smtp.corp.redhat.com (Postfix) with ESMTP id 1B8125D9D6; Mon, 9 Dec 2019 13:08:56 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1575896940; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=cioeW4SSr09ObvzRXUyDz1xqJxs21g3MnA23WRs94Qw=; b=H7aW2AgPkUvx/f81ki6qHP8dUvkDdgP/7AnqnWXZl1uL6eUH+wlJ3JGc0YtUzz/FyOkq3v lJHZswdtCE8TSgkV6SrZtwjutmcQj4eOs5nngaFKAiV/uVzv38JMkSMJqLCqW3YWJmWtYV 8Ua+RHbdCi8geBeUqElBNqllKakSegc= From: Igor Mammedov To: qemu-devel@nongnu.org Subject: [PATCH for-5.0 v2 1/9] hw: add compat machines for 5.0 Date: Mon, 9 Dec 2019 14:08:54 +0100 Message-Id: <1575896942-331151-2-git-send-email-imammedo@redhat.com> In-Reply-To: <1575896942-331151-1-git-send-email-imammedo@redhat.com> References: <1575896942-331151-1-git-send-email-imammedo@redhat.com> X-Scanned-By: MIMEDefang 2.79 on 10.5.11.14 X-MC-Unique: k8nQjiTnOnaPWTasmCgw9g-1 X-Mimecast-Spam-Score: 0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 205.139.110.61 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: pbonzini@redhat.com, philmd@redhat.com, lersek@redhat.com, mst@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Cornelia Huck Add 5.0 machine types for arm/i440fx/q35/s390x/spapr. For i440fx and q35, unversioned cpu models are still translated to -v1; I'll leave changing this (if desired) to the respective maintainers. Signed-off-by: Cornelia Huck Signed-off-by: Igor Mammedov --- include/hw/boards.h | 3 +++ include/hw/i386/pc.h | 3 +++ hw/arm/virt.c | 7 ++++++- hw/core/machine.c | 3 +++ hw/i386/pc.c | 3 +++ hw/i386/pc_piix.c | 14 +++++++++++++- hw/i386/pc_q35.c | 13 ++++++++++++- hw/ppc/spapr.c | 15 +++++++++++++-- hw/s390x/s390-virtio-ccw.c | 14 +++++++++++++- 9 files changed, 69 insertions(+), 6 deletions(-) diff --git a/include/hw/boards.h b/include/hw/boards.h index de45087..24cbeec 100644 --- a/include/hw/boards.h +++ b/include/hw/boards.h @@ -329,6 +329,9 @@ struct MachineState { } \ type_init(machine_initfn##_register_types) =20 +extern GlobalProperty hw_compat_4_2[]; +extern const size_t hw_compat_4_2_len; + extern GlobalProperty hw_compat_4_1[]; extern const size_t hw_compat_4_1_len; =20 diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h index 1f86eba..61a998d 100644 --- a/include/hw/i386/pc.h +++ b/include/hw/i386/pc.h @@ -237,6 +237,9 @@ void pc_system_firmware_init(PCMachineState *pcms, Memo= ryRegion *rom_memory); void pc_madt_cpu_entry(AcpiDeviceIf *adev, int uid, const CPUArchIdList *apic_ids, GArray *entry); =20 +extern GlobalProperty pc_compat_4_2[]; +extern const size_t pc_compat_4_2_len; + extern GlobalProperty pc_compat_4_1[]; extern const size_t pc_compat_4_1_len; =20 diff --git a/hw/arm/virt.c b/hw/arm/virt.c index d4bedc2..02f654b 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -2147,10 +2147,15 @@ static void machvirt_machine_init(void) } type_init(machvirt_machine_init); =20 +static void virt_machine_5_0_options(MachineClass *mc) +{ +} +DEFINE_VIRT_MACHINE_AS_LATEST(5, 0) + static void virt_machine_4_2_options(MachineClass *mc) { } -DEFINE_VIRT_MACHINE_AS_LATEST(4, 2) +DEFINE_VIRT_MACHINE(4, 2) =20 static void virt_machine_4_1_options(MachineClass *mc) { diff --git a/hw/core/machine.c b/hw/core/machine.c index 1689ad3..21fe2d9 100644 --- a/hw/core/machine.c +++ b/hw/core/machine.c @@ -27,6 +27,9 @@ #include "hw/pci/pci.h" #include "hw/mem/nvdimm.h" =20 +GlobalProperty hw_compat_4_2[] =3D {}; +const size_t hw_compat_4_2_len =3D G_N_ELEMENTS(hw_compat_4_2); + GlobalProperty hw_compat_4_1[] =3D { { "virtio-pci", "x-pcie-flr-init", "off" }, }; diff --git a/hw/i386/pc.c b/hw/i386/pc.c index ac08e63..58867f9 100644 --- a/hw/i386/pc.c +++ b/hw/i386/pc.c @@ -103,6 +103,9 @@ =20 struct hpet_fw_config hpet_cfg =3D {.count =3D UINT8_MAX}; =20 +GlobalProperty pc_compat_4_2[] =3D {}; +const size_t pc_compat_4_2_len =3D G_N_ELEMENTS(pc_compat_4_2); + GlobalProperty pc_compat_4_1[] =3D {}; const size_t pc_compat_4_1_len =3D G_N_ELEMENTS(pc_compat_4_1); =20 diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c index 1bd70d1..846e70b 100644 --- a/hw/i386/pc_piix.c +++ b/hw/i386/pc_piix.c @@ -424,7 +424,7 @@ static void pc_i440fx_machine_options(MachineClass *m) machine_class_allow_dynamic_sysbus_dev(m, TYPE_RAMFB_DEVICE); } =20 -static void pc_i440fx_4_2_machine_options(MachineClass *m) +static void pc_i440fx_5_0_machine_options(MachineClass *m) { PCMachineClass *pcmc =3D PC_MACHINE_CLASS(m); pc_i440fx_machine_options(m); @@ -433,6 +433,18 @@ static void pc_i440fx_4_2_machine_options(MachineClass= *m) pcmc->default_cpu_version =3D 1; } =20 +DEFINE_I440FX_MACHINE(v5_0, "pc-i440fx-5.0", NULL, + pc_i440fx_5_0_machine_options); + +static void pc_i440fx_4_2_machine_options(MachineClass *m) +{ + pc_i440fx_5_0_machine_options(m); + m->alias =3D NULL; + m->is_default =3D 0; + compat_props_add(m->compat_props, hw_compat_4_2, hw_compat_4_2_len); + compat_props_add(m->compat_props, pc_compat_4_2, pc_compat_4_2_len); +} + DEFINE_I440FX_MACHINE(v4_2, "pc-i440fx-4.2", NULL, pc_i440fx_4_2_machine_options); =20 diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c index 385e5cf..ddd485d 100644 --- a/hw/i386/pc_q35.c +++ b/hw/i386/pc_q35.c @@ -348,7 +348,7 @@ static void pc_q35_machine_options(MachineClass *m) m->max_cpus =3D 288; } =20 -static void pc_q35_4_2_machine_options(MachineClass *m) +static void pc_q35_5_0_machine_options(MachineClass *m) { PCMachineClass *pcmc =3D PC_MACHINE_CLASS(m); pc_q35_machine_options(m); @@ -356,6 +356,17 @@ static void pc_q35_4_2_machine_options(MachineClass *m) pcmc->default_cpu_version =3D 1; } =20 +DEFINE_Q35_MACHINE(v5_0, "pc-q35-5.0", NULL, + pc_q35_5_0_machine_options); + +static void pc_q35_4_2_machine_options(MachineClass *m) +{ + pc_q35_5_0_machine_options(m); + m->alias =3D NULL; + compat_props_add(m->compat_props, hw_compat_4_2, hw_compat_4_2_len); + compat_props_add(m->compat_props, pc_compat_4_2, pc_compat_4_2_len); +} + DEFINE_Q35_MACHINE(v4_2, "pc-q35-4.2", NULL, pc_q35_4_2_machine_options); =20 diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c index e076f60..3ae7db1 100644 --- a/hw/ppc/spapr.c +++ b/hw/ppc/spapr.c @@ -4492,14 +4492,25 @@ static const TypeInfo spapr_machine_info =3D { type_init(spapr_machine_register_##suffix) =20 /* + * pseries-5.0 + */ +static void spapr_machine_5_0_class_options(MachineClass *mc) +{ + /* Defaults for the latest behaviour inherited from the base class */ +} + +DEFINE_SPAPR_MACHINE(5_0, "5.0", true); + +/* * pseries-4.2 */ static void spapr_machine_4_2_class_options(MachineClass *mc) { - /* Defaults for the latest behaviour inherited from the base class */ + spapr_machine_5_0_class_options(mc); + compat_props_add(mc->compat_props, hw_compat_4_2, hw_compat_4_2_len); } =20 -DEFINE_SPAPR_MACHINE(4_2, "4.2", true); +DEFINE_SPAPR_MACHINE(4_2, "4.2", false); =20 /* * pseries-4.1 diff --git a/hw/s390x/s390-virtio-ccw.c b/hw/s390x/s390-virtio-ccw.c index d3edeef..01e7e20 100644 --- a/hw/s390x/s390-virtio-ccw.c +++ b/hw/s390x/s390-virtio-ccw.c @@ -639,14 +639,26 @@ bool css_migration_enabled(void) } = \ type_init(ccw_machine_register_##suffix) =20 +static void ccw_machine_5_0_instance_options(MachineState *machine) +{ +} + +static void ccw_machine_5_0_class_options(MachineClass *mc) +{ +} +DEFINE_CCW_MACHINE(5_0, "5.0", true); + static void ccw_machine_4_2_instance_options(MachineState *machine) { + ccw_machine_5_0_instance_options(machine); } =20 static void ccw_machine_4_2_class_options(MachineClass *mc) { + ccw_machine_5_0_class_options(mc); + compat_props_add(mc->compat_props, hw_compat_4_2, hw_compat_4_2_len); } -DEFINE_CCW_MACHINE(4_2, "4.2", true); +DEFINE_CCW_MACHINE(4_2, "4.2", false); =20 static void ccw_machine_4_1_instance_options(MachineState *machine) { --=20 2.7.4 From nobody Mon Apr 29 12:55:39 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1575897241; cv=none; d=zohomail.com; s=zohoarc; b=hOS99hIGGP4YcFmlxn4cb+qb0oPH4LyH13PENDIEHqqMsDzoOt+byesmd0MIYt9ppq/oklK0rQ3Nw0et7sVJgODjL2qqTcRNGOq37kbAMYYn3pHXKXCEFooIMzvsvJ2OQ6IrREf4lLWbSWt9vDblGP0qId+zDuDEJPHl0AK/CrI= ARC-Message-Signature: i=1; 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Mon, 9 Dec 2019 13:09:01 +0000 (UTC) Received: from dell-r430-03.lab.eng.brq.redhat.com (dell-r430-03.lab.eng.brq.redhat.com [10.37.153.18]) by smtp.corp.redhat.com (Postfix) with ESMTP id 896DE5D9D6; Mon, 9 Dec 2019 13:08:58 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1575896944; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=Qlqu3alGMc4CJDsJ3LVLvIl3Av6Wwz2J4VOluHST5Jg=; b=EfRWQGmL6/R302qDj/F1pWAecCFfVddw206WYaybMYNyDLTEGlisj3HdTCl6DU6p78Uoex OOe9vY/q1eelr+MiwiSwwiSvIKDviTrh9YpR21ydvnu7FqqHMQMhXE2x0e/x2WajkQkOS6 jcqpxs46XNMDVdseebI5mE07XdrK+L0= From: Igor Mammedov To: qemu-devel@nongnu.org Subject: [PATCH for-5.0 v2 2/9] q35: implement 128K SMRAM at default SMBASE address Date: Mon, 9 Dec 2019 14:08:55 +0100 Message-Id: <1575896942-331151-3-git-send-email-imammedo@redhat.com> In-Reply-To: <1575896942-331151-1-git-send-email-imammedo@redhat.com> References: <1575896942-331151-1-git-send-email-imammedo@redhat.com> X-Scanned-By: MIMEDefang 2.79 on 10.5.11.14 X-MC-Unique: Bl9WAdN-Mc-Ecx6ghC2EOQ-1 X-Mimecast-Spam-Score: 0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 207.211.31.120 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: pbonzini@redhat.com, philmd@redhat.com, lersek@redhat.com, mst@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" It's not what real HW does, implementing which would be overkill [**] and would require complex cross stack changes (QEMU+firmware) to make it work. So considering that SMRAM is owned by MCH, for simplicity (ab)use reserved Q35 register, which allows QEMU and firmware easily init and make RAM at SMBASE available only from SMM context. Patch uses commit (2f295167e0 q35/mch: implement extended TSEG sizes) for inspiration and uses reserved register in config space at 0x9c offset [*] to extend q35 pci-host with ability to use 128K at 0x30000 as SMRAM and hide it (like TSEG) from non-SMM context. Usage: 1: write 0xff in the register 2: if the feature is supported, follow up read from the register should return 0x01. At this point RAM at 0x30000 is still available for SMI handler configuration from non-SMM context 3: writing 0x02 in the register, locks SMBASE area, making its contents available only from SMM context. In non-SMM context, reads return 0xff and writes are ignored. Further writes into the register are ignored until the system reset. *) https://www.mail-archive.com/qemu-devel@nongnu.org/msg455991.html **) https://www.mail-archive.com/qemu-devel@nongnu.org/msg646965.html Signed-off-by: Igor Mammedov Tested-by: Laszlo Ersek --- V2: - add a note in commit message/coed that used approach is QEMU hack to make impl. simple instead of going after VT-d approach which real HW does. (Paolo Bonzini ) - rebase on top of (hw: add compat machines for 5.0), and move compat property smbase-smram to pc_compat_4_2[] ("Laszlo Ersek" ) --- include/hw/pci-host/q35.h | 10 ++++++ hw/i386/pc.c | 4 ++- hw/pci-host/q35.c | 84 +++++++++++++++++++++++++++++++++++++++++++= ---- 3 files changed, 90 insertions(+), 8 deletions(-) diff --git a/include/hw/pci-host/q35.h b/include/hw/pci-host/q35.h index b3bcf2e..976fbae 100644 --- a/include/hw/pci-host/q35.h +++ b/include/hw/pci-host/q35.h @@ -32,6 +32,7 @@ #include "hw/acpi/ich9.h" #include "hw/pci-host/pam.h" #include "hw/i386/intel_iommu.h" +#include "qemu/units.h" =20 #define TYPE_Q35_HOST_DEVICE "q35-pcihost" #define Q35_HOST_DEVICE(obj) \ @@ -54,6 +55,8 @@ typedef struct MCHPCIState { MemoryRegion smram_region, open_high_smram; MemoryRegion smram, low_smram, high_smram; MemoryRegion tseg_blackhole, tseg_window; + MemoryRegion smbase_blackhole, smbase_window; + bool has_smram_at_smbase; Range pci_hole; uint64_t below_4g_mem_size; uint64_t above_4g_mem_size; @@ -97,6 +100,13 @@ typedef struct Q35PCIHost { #define MCH_HOST_BRIDGE_EXT_TSEG_MBYTES_QUERY 0xffff #define MCH_HOST_BRIDGE_EXT_TSEG_MBYTES_MAX 0xfff =20 +#define MCH_HOST_BRIDGE_SMBASE_SIZE (128 * KiB) +#define MCH_HOST_BRIDGE_SMBASE_ADDR 0x30000 +#define MCH_HOST_BRIDGE_F_SMBASE 0x9c +#define MCH_HOST_BRIDGE_F_SMBASE_QUERY 0xff +#define MCH_HOST_BRIDGE_F_SMBASE_IN_RAM 0x01 +#define MCH_HOST_BRIDGE_F_SMBASE_LCK 0x02 + #define MCH_HOST_BRIDGE_PCIEXBAR 0x60 /* 64bit register */ #define MCH_HOST_BRIDGE_PCIEXBAR_SIZE 8 /* 64bit register */ #define MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT 0xb0000000 diff --git a/hw/i386/pc.c b/hw/i386/pc.c index 58867f9..ff4d583 100644 --- a/hw/i386/pc.c +++ b/hw/i386/pc.c @@ -103,7 +103,9 @@ =20 struct hpet_fw_config hpet_cfg =3D {.count =3D UINT8_MAX}; =20 -GlobalProperty pc_compat_4_2[] =3D {}; +GlobalProperty pc_compat_4_2[] =3D { + { "mch", "smbase-smram", "off" }, +}; const size_t pc_compat_4_2_len =3D G_N_ELEMENTS(pc_compat_4_2); =20 GlobalProperty pc_compat_4_1[] =3D {}; diff --git a/hw/pci-host/q35.c b/hw/pci-host/q35.c index 158d270..6342f73 100644 --- a/hw/pci-host/q35.c +++ b/hw/pci-host/q35.c @@ -275,20 +275,20 @@ static const TypeInfo q35_host_info =3D { * MCH D0:F0 */ =20 -static uint64_t tseg_blackhole_read(void *ptr, hwaddr reg, unsigned size) +static uint64_t blackhole_read(void *ptr, hwaddr reg, unsigned size) { return 0xffffffff; } =20 -static void tseg_blackhole_write(void *opaque, hwaddr addr, uint64_t val, - unsigned width) +static void blackhole_write(void *opaque, hwaddr addr, uint64_t val, + unsigned width) { /* nothing */ } =20 -static const MemoryRegionOps tseg_blackhole_ops =3D { - .read =3D tseg_blackhole_read, - .write =3D tseg_blackhole_write, +static const MemoryRegionOps blackhole_ops =3D { + .read =3D blackhole_read, + .write =3D blackhole_write, .endianness =3D DEVICE_NATIVE_ENDIAN, .valid.min_access_size =3D 1, .valid.max_access_size =3D 4, @@ -430,6 +430,46 @@ static void mch_update_ext_tseg_mbytes(MCHPCIState *mc= h) } } =20 +static void mch_update_smbase_smram(MCHPCIState *mch) +{ + PCIDevice *pd =3D PCI_DEVICE(mch); + uint8_t *reg =3D pd->config + MCH_HOST_BRIDGE_F_SMBASE; + bool lck; + + if (!mch->has_smram_at_smbase) { + return; + } + + if (*reg =3D=3D MCH_HOST_BRIDGE_F_SMBASE_QUERY) { + pd->wmask[MCH_HOST_BRIDGE_F_SMBASE] =3D + MCH_HOST_BRIDGE_F_SMBASE_LCK; + *reg =3D MCH_HOST_BRIDGE_F_SMBASE_IN_RAM; + return; + } + + /* + * default/reset state, discard written value + * which will disable SMRAM balackhole at SMBASE + */ + if (pd->wmask[MCH_HOST_BRIDGE_F_SMBASE] =3D=3D 0xff) { + *reg =3D 0x00; + } + + memory_region_transaction_begin(); + if (*reg & MCH_HOST_BRIDGE_F_SMBASE_LCK) { + /* disable all writes */ + pd->wmask[MCH_HOST_BRIDGE_F_SMBASE] &=3D + ~MCH_HOST_BRIDGE_F_SMBASE_LCK; + *reg =3D MCH_HOST_BRIDGE_F_SMBASE_LCK; + lck =3D true; + } else { + lck =3D false; + } + memory_region_set_enabled(&mch->smbase_blackhole, lck); + memory_region_set_enabled(&mch->smbase_window, lck); + memory_region_transaction_commit(); +} + static void mch_write_config(PCIDevice *d, uint32_t address, uint32_t val, int len) { @@ -456,6 +496,10 @@ static void mch_write_config(PCIDevice *d, MCH_HOST_BRIDGE_EXT_TSEG_MBYTES_SIZE)) { mch_update_ext_tseg_mbytes(mch); } + + if (ranges_overlap(address, len, MCH_HOST_BRIDGE_F_SMBASE, 1)) { + mch_update_smbase_smram(mch); + } } =20 static void mch_update(MCHPCIState *mch) @@ -464,6 +508,7 @@ static void mch_update(MCHPCIState *mch) mch_update_pam(mch); mch_update_smram(mch); mch_update_ext_tseg_mbytes(mch); + mch_update_smbase_smram(mch); =20 /* * pci hole goes from end-of-low-ram to io-apic. @@ -514,6 +559,9 @@ static void mch_reset(DeviceState *qdev) MCH_HOST_BRIDGE_EXT_TSEG_MBYTES_QUERY); } =20 + d->config[MCH_HOST_BRIDGE_F_SMBASE] =3D 0; + d->wmask[MCH_HOST_BRIDGE_F_SMBASE] =3D 0xff; + mch_update(mch); } =20 @@ -563,7 +611,7 @@ static void mch_realize(PCIDevice *d, Error **errp) memory_region_add_subregion(&mch->smram, 0xfeda0000, &mch->high_smram); =20 memory_region_init_io(&mch->tseg_blackhole, OBJECT(mch), - &tseg_blackhole_ops, NULL, + &blackhole_ops, NULL, "tseg-blackhole", 0); memory_region_set_enabled(&mch->tseg_blackhole, false); memory_region_add_subregion_overlap(mch->system_memory, @@ -575,6 +623,27 @@ static void mch_realize(PCIDevice *d, Error **errp) memory_region_set_enabled(&mch->tseg_window, false); memory_region_add_subregion(&mch->smram, mch->below_4g_mem_size, &mch->tseg_window); + + /* + * This is not what hardware does, so it's QEMU specific hack. + * See commit message for details. + */ + memory_region_init_io(&mch->smbase_blackhole, OBJECT(mch), &blackhole_= ops, + NULL, "smbase-blackhole", + MCH_HOST_BRIDGE_SMBASE_SIZE); + memory_region_set_enabled(&mch->smbase_blackhole, false); + memory_region_add_subregion_overlap(mch->system_memory, + MCH_HOST_BRIDGE_SMBASE_ADDR, + &mch->smbase_blackhole, 1); + + memory_region_init_alias(&mch->smbase_window, OBJECT(mch), + "smbase-window", mch->ram_memory, + MCH_HOST_BRIDGE_SMBASE_ADDR, + MCH_HOST_BRIDGE_SMBASE_SIZE); + memory_region_set_enabled(&mch->smbase_window, false); + memory_region_add_subregion(&mch->smram, MCH_HOST_BRIDGE_SMBASE_ADDR, + &mch->smbase_window); + object_property_add_const_link(qdev_get_machine(), "smram", OBJECT(&mch->smram), &error_abort); =20 @@ -601,6 +670,7 @@ uint64_t mch_mcfg_base(void) static Property mch_props[] =3D { DEFINE_PROP_UINT16("extended-tseg-mbytes", MCHPCIState, ext_tseg_mbyte= s, 16), + DEFINE_PROP_BOOL("smbase-smram", MCHPCIState, has_smram_at_smbase, tru= e), DEFINE_PROP_END_OF_LIST(), }; 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Mon, 9 Dec 2019 13:09:02 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1575896949; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=Fr2KxWaxRXYFyyTmacQjYhempuw1vnJZ79bFGUkw7/w=; b=U+XIWinLsC17pMW3fOhZNFpy2Bm/90hevxO91u6PN5c1F/SRvXwviI1Vc4DbD+imqWuPJt yzcfIYDIqCdcAKxo3XOSwCJwHsh/YsYhnF6elK20PjKvdFWRCrtATnZcEsGBx+saVpAbF0 ax7HG8iw8OL9cfZ4rkVmFf0pp8nlZ9c= From: Igor Mammedov To: qemu-devel@nongnu.org Subject: [PATCH for-5.0 v2 3/9] tests: q35: MCH: add default SMBASE SMRAM lock test Date: Mon, 9 Dec 2019 14:08:56 +0100 Message-Id: <1575896942-331151-4-git-send-email-imammedo@redhat.com> In-Reply-To: <1575896942-331151-1-git-send-email-imammedo@redhat.com> References: <1575896942-331151-1-git-send-email-imammedo@redhat.com> X-Scanned-By: MIMEDefang 2.79 on 10.5.11.14 X-MC-Unique: dMvhhO8jNcCntmh46Wz5bg-1 X-Mimecast-Spam-Score: 0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 207.211.31.81 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: pbonzini@redhat.com, philmd@redhat.com, lersek@redhat.com, mst@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" test lockable SMRAM at default SMBASE feature, introduced by patch "q35: implement 128K SMRAM at default SMBASE address" Signed-off-by: Igor Mammedov --- tests/q35-test.c | 105 +++++++++++++++++++++++++++++++++++++++++++++++++++= ++++ 1 file changed, 105 insertions(+) diff --git a/tests/q35-test.c b/tests/q35-test.c index a68183d..dd02660 100644 --- a/tests/q35-test.c +++ b/tests/q35-test.c @@ -186,6 +186,109 @@ static void test_tseg_size(const void *data) qtest_quit(qts); } =20 +#define SMBASE 0x30000 +#define SMRAM_TEST_PATTERN 0x32 +#define SMRAM_TEST_RESET_PATTERN 0x23 + +static void test_smram_smbase_lock(void) +{ + QPCIBus *pcibus; + QPCIDevice *pcidev; + QDict *response; + QTestState *qts; + int i; + + qts =3D qtest_init("-M q35"); + + pcibus =3D qpci_new_pc(qts, NULL); + g_assert(pcibus !=3D NULL); + + pcidev =3D qpci_device_find(pcibus, 0); + g_assert(pcidev !=3D NULL); + + /* check that SMRAM is not enabled by default */ + g_assert(qpci_config_readb(pcidev, MCH_HOST_BRIDGE_F_SMBASE) =3D=3D 0); + qtest_writeb(qts, SMBASE, SMRAM_TEST_PATTERN); + g_assert_cmpint(qtest_readb(qts, SMBASE), =3D=3D, SMRAM_TEST_PATTERN); + + /* check that writinng junk to 0x9c before before negotiating is ignor= red */ + for (i =3D 0; i < 0xff; i++) { + qpci_config_writeb(pcidev, MCH_HOST_BRIDGE_F_SMBASE, i); + g_assert(qpci_config_readb(pcidev, MCH_HOST_BRIDGE_F_SMBASE) =3D= =3D 0); + } + + /* enable SMRAM at SMBASE */ + qpci_config_writeb(pcidev, MCH_HOST_BRIDGE_F_SMBASE, 0xff); + g_assert(qpci_config_readb(pcidev, MCH_HOST_BRIDGE_F_SMBASE) =3D=3D 0x= 01); + /* lock SMRAM at SMBASE */ + qpci_config_writeb(pcidev, MCH_HOST_BRIDGE_F_SMBASE, 0x02); + g_assert(qpci_config_readb(pcidev, MCH_HOST_BRIDGE_F_SMBASE) =3D=3D 0x= 02); + + /* check that SMRAM at SMBASE is locked and can't be unlocked */ + g_assert_cmpint(qtest_readb(qts, SMBASE), =3D=3D, 0xff); + for (i =3D 0; i <=3D 0xff; i++) { + /* make sure register is immutable */ + qpci_config_writeb(pcidev, MCH_HOST_BRIDGE_F_SMBASE, i); + g_assert(qpci_config_readb(pcidev, MCH_HOST_BRIDGE_F_SMBASE) =3D= =3D 0x02); + + /* RAM access should go inot black hole */ + qtest_writeb(qts, SMBASE, SMRAM_TEST_PATTERN); + g_assert_cmpint(qtest_readb(qts, SMBASE), =3D=3D, 0xff); + } + + /* reset */ + response =3D qtest_qmp(qts, "{'execute': 'system_reset', 'arguments': = {} }"); + g_assert(response); + g_assert(!qdict_haskey(response, "error")); + qobject_unref(response); + + /* check RAM at SMBASE is available after reset */ + g_assert_cmpint(qtest_readb(qts, SMBASE), =3D=3D, SMRAM_TEST_PATTERN); + g_assert(qpci_config_readb(pcidev, MCH_HOST_BRIDGE_F_SMBASE) =3D=3D 0); + qtest_writeb(qts, SMBASE, SMRAM_TEST_RESET_PATTERN); + g_assert_cmpint(qtest_readb(qts, SMBASE), =3D=3D, SMRAM_TEST_RESET_PAT= TERN); + + g_free(pcidev); + qpci_free_pc(pcibus); + + qtest_quit(qts); +} + +static void test_without_smram_base(void) +{ + QPCIBus *pcibus; + QPCIDevice *pcidev; + QTestState *qts; + int i; + + qts =3D qtest_init("-M pc-q35-4.1"); + + pcibus =3D qpci_new_pc(qts, NULL); + g_assert(pcibus !=3D NULL); + + pcidev =3D qpci_device_find(pcibus, 0); + g_assert(pcidev !=3D NULL); + + /* check that RAM accessible */ + qtest_writeb(qts, SMBASE, SMRAM_TEST_PATTERN); + g_assert_cmpint(qtest_readb(qts, SMBASE), =3D=3D, SMRAM_TEST_PATTERN); + + /* check that writing to 0x9c succeeds */ + for (i =3D 0; i <=3D 0xff; i++) { + qpci_config_writeb(pcidev, MCH_HOST_BRIDGE_F_SMBASE, i); + g_assert(qpci_config_readb(pcidev, MCH_HOST_BRIDGE_F_SMBASE) =3D= =3D i); + } + + /* check that RAM is still accessible */ + qtest_writeb(qts, SMBASE, SMRAM_TEST_PATTERN + 1); + g_assert_cmpint(qtest_readb(qts, SMBASE), =3D=3D, (SMRAM_TEST_PATTERN = + 1)); + + g_free(pcidev); + qpci_free_pc(pcibus); + + qtest_quit(qts); +} + int main(int argc, char **argv) { g_test_init(&argc, &argv, NULL); @@ -197,5 +300,7 @@ int main(int argc, char **argv) qtest_add_data_func("/q35/tseg-size/8mb", &tseg_8mb, test_tseg_size); qtest_add_data_func("/q35/tseg-size/ext/16mb", &tseg_ext_16mb, test_tseg_size); + qtest_add_func("/q35/smram/smbase_lock", test_smram_smbase_lock); + qtest_add_func("/q35/smram/legacy_smbase", test_without_smram_base); return g_test_run(); } --=20 2.7.4 From nobody Mon Apr 29 12:55:39 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1575897080; cv=none; d=zohomail.com; s=zohoarc; b=dTGTdfXQLJCYGHw7kEc8Gb9Fvf6Ij8KVnbbzep31DXZRF1d1I4/Mk2uZDPUrbdDD6Rk9Yk4iX9md540IGaxbGdmPUCpFgJt2IfUurTSy2dB4Tj1MsU4QC8VM/ZB3iPyXrhIM5OPYar5seEnCrpZ6bk/lvOjXTukW37wUjB1B5as= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1575897080; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To; 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Mon, 9 Dec 2019 13:09:05 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1575896951; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=9rTAsu61kfsjr+dyoO+ow9+AlkfoKZIwKFhn+b5wB8Y=; b=QsD2J5Hfz5gyCO8Tady1vQb+oRda8qnLXzRSq8UzgwZpvqPcInSrVkHMJ61vn70CkrSUnw yKzhu99GAIX0Mt6B4ThsUsB6WksgzXowZrRXKDT0U2H2UBjfM6ZEBUFKFiCGdLDLovEU3U LQ5U6ekVMcyCApDFO4rjDIcDFT0qAqI= From: Igor Mammedov To: qemu-devel@nongnu.org Subject: [PATCH for-5.0 v2 4/9] acpi: cpuhp: spec: clarify 'CPU selector' register usage and endianness Date: Mon, 9 Dec 2019 14:08:57 +0100 Message-Id: <1575896942-331151-5-git-send-email-imammedo@redhat.com> In-Reply-To: <1575896942-331151-1-git-send-email-imammedo@redhat.com> References: <1575896942-331151-1-git-send-email-imammedo@redhat.com> X-Scanned-By: MIMEDefang 2.79 on 10.5.11.14 X-MC-Unique: DiVD2t2ROOOgTONC2H5PHQ-1 X-Mimecast-Spam-Score: 0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 205.139.110.120 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: pbonzini@redhat.com, philmd@redhat.com, lersek@redhat.com, mst@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" * Move reserved registers to the top of the section, so reader would be aware of effects when reading registers description. * State registers endianness explicitly at the beginning of the section * Describe registers behavior in case of 'CPU selector' register contains value that doesn't point to a possible CPU. Signed-off-by: Igor Mammedov Reviewed-by: Laszlo Ersek --- docs/specs/acpi_cpu_hotplug.txt | 18 ++++++++++++------ 1 file changed, 12 insertions(+), 6 deletions(-) diff --git a/docs/specs/acpi_cpu_hotplug.txt b/docs/specs/acpi_cpu_hotplug.= txt index ee219c8..4e65286 100644 --- a/docs/specs/acpi_cpu_hotplug.txt +++ b/docs/specs/acpi_cpu_hotplug.txt @@ -30,6 +30,18 @@ Register block base address: Register block size: ACPI_CPU_HOTPLUG_REG_LEN =3D 12 =20 +All accesses to registers described below, imply little-endian byte order. + +Reserved resisters behavior: + - write accesses are ignored + - read accesses return all bits set to 0. + +The last stored value in 'CPU selector' must refer to a possible CPU, othe= rwise + - reads from any register return 0 + - writes to any other register are ignored until valid value is stored i= nto it +On QEMU start, 'CPU selector' is initialized to a valid value, on reset it +keeps the current value. + read access: offset: [0x0-0x3] reserved @@ -86,9 +98,3 @@ write access: ACPI_DEVICE_OST QMP event from QEMU to external applicati= ons with current values of OST event and status registers. other values: reserved - -Selecting CPU device beyond possible range has no effect on platform: - - write accesses to CPU hot-plug registers not documented above are - ignored - - read accesses to CPU hot-plug registers not documented above return - all bits set to 0. --=20 2.7.4 From nobody Mon Apr 29 12:55:39 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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Mon, 09 Dec 2019 08:09:11 -0500 Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-47-nc6LehCjPkSomqRE26Zpgw-1; Mon, 09 Dec 2019 08:09:09 -0500 Received: from smtp.corp.redhat.com (int-mx04.intmail.prod.int.phx2.redhat.com [10.5.11.14]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id 94AF618AAFA5 for ; Mon, 9 Dec 2019 13:09:08 +0000 (UTC) Received: from dell-r430-03.lab.eng.brq.redhat.com (dell-r430-03.lab.eng.brq.redhat.com [10.37.153.18]) by smtp.corp.redhat.com (Postfix) with ESMTP id 6AD245DA60; Mon, 9 Dec 2019 13:09:07 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1575896951; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=IXWUNvqNN5ClGR1wviwpy2v2AS3yXXwj2mo3UIvxF8s=; b=jTDke9nDyzThgnVMiw2CRWiS4v/2Iy1oD8CE0rvojpQB7IAG4pu0o8/T3gdaO2D00xuhfy GBO1U7Hy5/QUrZCALA73ZmYH6NyaTT2HCbyuyrjfyykc5PYe0HAgsroUQLzo4PYrtwQ2Pz eO7Q3IefxxYRC72AtX1JQzIZMRJ0fGQ= From: Igor Mammedov To: qemu-devel@nongnu.org Subject: [PATCH for-5.0 v2 5/9] acpi: cpuhp: spec: fix 'Command data' description Date: Mon, 9 Dec 2019 14:08:58 +0100 Message-Id: <1575896942-331151-6-git-send-email-imammedo@redhat.com> In-Reply-To: <1575896942-331151-1-git-send-email-imammedo@redhat.com> References: <1575896942-331151-1-git-send-email-imammedo@redhat.com> X-Scanned-By: MIMEDefang 2.79 on 10.5.11.14 X-MC-Unique: nc6LehCjPkSomqRE26Zpgw-1 X-Mimecast-Spam-Score: 0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 207.211.31.81 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: pbonzini@redhat.com, philmd@redhat.com, lersek@redhat.com, mst@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Correct returned value description in case 'Command field' =3D=3D 0x0, it's not PXM but CPU selector value with pending event In addition describe 0 blanket value in case of not supported 'Command field' value. Signed-off-by: Igor Mammedov Reviewed-by: Laszlo Ersek --- v2: * rephrase a docs little bit (Laszlo) --- docs/specs/acpi_cpu_hotplug.txt | 11 +++++------ 1 file changed, 5 insertions(+), 6 deletions(-) diff --git a/docs/specs/acpi_cpu_hotplug.txt b/docs/specs/acpi_cpu_hotplug.= txt index 4e65286..d510872 100644 --- a/docs/specs/acpi_cpu_hotplug.txt +++ b/docs/specs/acpi_cpu_hotplug.txt @@ -56,9 +56,8 @@ read access: 3-7: reserved and should be ignored by OSPM [0x5-0x7] reserved [0x8] Command data: (DWORD access) - in case of error or unsupported command reads is 0xFFFFFFFF - current 'Command field' value: - 0: returns PXM value corresponding to device + contains 0 unless value last stored in 'Command field' is one of: + 0: contains 'CPU selector' value of a CPU with pending event= [s] =20 write access: offset: @@ -81,9 +80,9 @@ write access: value: 0: selects a CPU device with inserting/removing events and following reads from 'Command data' register return - selected CPU (CPU selector value). If no CPU with events - found, the current CPU selector doesn't change and - corresponding insert/remove event flags are not set. + selected CPU ('CPU selector' value). + If no CPU with events found, the current 'CPU selector' doe= sn't + change and corresponding insert/remove event flags are not = modified. 1: following writes to 'Command data' register set OST event register in QEMU 2: following writes to 'Command data' register set OST status --=20 2.7.4 From nobody Mon Apr 29 12:55:39 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=redhat.com ARC-Seal: i=1; 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Mon, 09 Dec 2019 08:09:14 -0500 Received: from smtp.corp.redhat.com (int-mx04.intmail.prod.int.phx2.redhat.com [10.5.11.14]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id 534C9800D41 for ; Mon, 9 Dec 2019 13:09:12 +0000 (UTC) Received: from dell-r430-03.lab.eng.brq.redhat.com (dell-r430-03.lab.eng.brq.redhat.com [10.37.153.18]) by smtp.corp.redhat.com (Postfix) with ESMTP id DC35D5D9D6; Mon, 9 Dec 2019 13:09:08 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1575896956; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=N/zL+oUPazEV3yrIgIQGktVpOAKbjraCKyyj25RYVAw=; b=PT1YKFmGCpoAnU95opNPyEZq+weDLSoI2h6iNCP2th+s3qhAPUEcShPN1pPHR+nyLHzNVC ZJBJpaO8lDIuouIqa4xJ6vDb5E2dtBQIVcyBgRDKk4hx0rSm9j5eYZKUzhUB9NWdbtEj// 2u1zSKxcCFp1X9hSyExtlxczW4Du7l8= From: Igor Mammedov To: qemu-devel@nongnu.org Subject: [PATCH for-5.0 v2 6/9] acpi: cpuhp: spec: clarify store into 'Command data' when 'Command field' == 0 Date: Mon, 9 Dec 2019 14:08:59 +0100 Message-Id: <1575896942-331151-7-git-send-email-imammedo@redhat.com> In-Reply-To: <1575896942-331151-1-git-send-email-imammedo@redhat.com> References: <1575896942-331151-1-git-send-email-imammedo@redhat.com> X-Scanned-By: MIMEDefang 2.79 on 10.5.11.14 X-MC-Unique: EBxk-X8dPKeK6pft9d85Sg-1 X-Mimecast-Spam-Score: 0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 205.139.110.61 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: pbonzini@redhat.com, philmd@redhat.com, lersek@redhat.com, mst@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Write section of 'Command data' register should describe what happens when it's written into. Correct description in case the last stored 'Command field' value is equal to 0, to reflect that currently it's not supported. Signed-off-by: Igor Mammedov Reviewed-by: Laszlo Ersek --- docs/specs/acpi_cpu_hotplug.txt | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/docs/specs/acpi_cpu_hotplug.txt b/docs/specs/acpi_cpu_hotplug.= txt index d510872..8fb9ad2 100644 --- a/docs/specs/acpi_cpu_hotplug.txt +++ b/docs/specs/acpi_cpu_hotplug.txt @@ -90,8 +90,7 @@ write access: other values: reserved [0x6-0x7] reserved [0x8] Command data: (DWORD access) - current 'Command field' value: - 0: OSPM reads value of CPU selector + if last stored 'Command field' value: 1: stores value into OST event register 2: stores value into OST status register, triggers ACPI_DEVICE_OST QMP event from QEMU to external applicati= ons --=20 2.7.4 From nobody Mon Apr 29 12:55:39 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; 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Mon, 09 Dec 2019 08:09:22 -0500 Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-436-QCKrq1MoN9CvRmOErzDzfQ-1; Mon, 09 Dec 2019 08:09:16 -0500 Received: from smtp.corp.redhat.com (int-mx04.intmail.prod.int.phx2.redhat.com [10.5.11.14]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id 12C98107ACC5 for ; Mon, 9 Dec 2019 13:09:16 +0000 (UTC) Received: from dell-r430-03.lab.eng.brq.redhat.com (dell-r430-03.lab.eng.brq.redhat.com [10.37.153.18]) by smtp.corp.redhat.com (Postfix) with ESMTP id 9B8065D9D6; Mon, 9 Dec 2019 13:09:12 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1575896960; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=NUT0d0GnH83DN8tXNv0Pikp7gHUonN+Nyize4nt1XkU=; b=JhmO5szMjoL6VSO0u5juQqrwyXB1+Cz68yUwfB5om1MQNl8UvgSpvWCxK4kPMLC3cyZYqU sfgxUsCG0J9572e6XSBhXOarB1qI8voytAIjNlT3c7+8oel18rAScW672TVZw0+KO+pcL1 3PMhpm4os9aGRedrYcShudAAlRRuP2Y= From: Igor Mammedov To: qemu-devel@nongnu.org Subject: [PATCH for-5.0 v2 7/9] acpi: cpuhp: introduce 'Command data 2' field Date: Mon, 9 Dec 2019 14:09:00 +0100 Message-Id: <1575896942-331151-8-git-send-email-imammedo@redhat.com> In-Reply-To: <1575896942-331151-1-git-send-email-imammedo@redhat.com> References: <1575896942-331151-1-git-send-email-imammedo@redhat.com> X-Scanned-By: MIMEDefang 2.79 on 10.5.11.14 X-MC-Unique: QCKrq1MoN9CvRmOErzDzfQ-1 X-Mimecast-Spam-Score: 0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 205.139.110.120 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: pbonzini@redhat.com, philmd@redhat.com, lersek@redhat.com, mst@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" No functional change in practice, patch only aims to properly document (in spec and code) intended usage of the reserved space. The new field is to be used for 2 purposes: - detection of modern CPU hotplug interface using CPHP_GET_NEXT_CPU_WITH_EVENT_CMD command. procedure will be described in follow up patch: "acpi: cpuhp: spec: add typical usecases" - for returning upper 32 bits of architecture specific CPU ID, for new CPHP_GET_CPU_ID_CMD command added by follow up patch: "acpi: cpuhp: add CPHP_GET_CPU_ID_CMD command" Change is backward compatible with 4.2 and older machines, as field was unconditionally reserved and always returned 0x0 if modern CPU hotplug interface was enabled. Signed-off-by: Igor Mammedov Reviewed-by: Laszlo Ersek --- docs/specs/acpi_cpu_hotplug.txt | 5 ++++- hw/acpi/cpu.c | 11 +++++++++++ hw/acpi/trace-events | 1 + 3 files changed, 16 insertions(+), 1 deletion(-) diff --git a/docs/specs/acpi_cpu_hotplug.txt b/docs/specs/acpi_cpu_hotplug.= txt index 8fb9ad2..9879f9e 100644 --- a/docs/specs/acpi_cpu_hotplug.txt +++ b/docs/specs/acpi_cpu_hotplug.txt @@ -44,7 +44,10 @@ keeps the current value. =20 read access: offset: - [0x0-0x3] reserved + [0x0-0x3] Command data 2: (DWORD access) + if value last stored in 'Command field': + 0: reads as 0x0 + other values: reserved [0x4] CPU device status fields: (1 byte access) bits: 0: Device is enabled and may be used by guest diff --git a/hw/acpi/cpu.c b/hw/acpi/cpu.c index 87f30a3..d475c06 100644 --- a/hw/acpi/cpu.c +++ b/hw/acpi/cpu.c @@ -12,6 +12,7 @@ #define ACPI_CPU_FLAGS_OFFSET_RW 4 #define ACPI_CPU_CMD_OFFSET_WR 5 #define ACPI_CPU_CMD_DATA_OFFSET_RW 8 +#define ACPI_CPU_CMD_DATA2_OFFSET_R 0 =20 enum { CPHP_GET_NEXT_CPU_WITH_EVENT_CMD =3D 0, @@ -79,6 +80,16 @@ static uint64_t cpu_hotplug_rd(void *opaque, hwaddr addr= , unsigned size) } trace_cpuhp_acpi_read_cmd_data(cpu_st->selector, val); break; + case ACPI_CPU_CMD_DATA2_OFFSET_R: + switch (cpu_st->command) { + case CPHP_GET_NEXT_CPU_WITH_EVENT_CMD: + val =3D 0; + break; + default: + break; + } + trace_cpuhp_acpi_read_cmd_data2(cpu_st->selector, val); + break; default: break; } diff --git a/hw/acpi/trace-events b/hw/acpi/trace-events index 96b8273..afbc77d 100644 --- a/hw/acpi/trace-events +++ b/hw/acpi/trace-events @@ -23,6 +23,7 @@ cpuhp_acpi_read_flags(uint32_t idx, uint8_t flags) "idx[0= x%"PRIx32"] flags: 0x%" cpuhp_acpi_write_idx(uint32_t idx) "set active cpu idx: 0x%"PRIx32 cpuhp_acpi_write_cmd(uint32_t idx, uint8_t cmd) "idx[0x%"PRIx32"] cmd: 0x%= "PRIx8 cpuhp_acpi_read_cmd_data(uint32_t idx, uint32_t data) "idx[0x%"PRIx32"] da= ta: 0x%"PRIx32 +cpuhp_acpi_read_cmd_data2(uint32_t idx, uint32_t data) "idx[0x%"PRIx32"] d= ata: 0x%"PRIx32 cpuhp_acpi_cpu_has_events(uint32_t idx, bool ins, bool rm) "idx[0x%"PRIx32= "] inserting: %d, removing: %d" cpuhp_acpi_clear_inserting_evt(uint32_t idx) "idx[0x%"PRIx32"]" cpuhp_acpi_clear_remove_evt(uint32_t idx) "idx[0x%"PRIx32"]" --=20 2.7.4 From nobody Mon Apr 29 12:55:39 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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Mon, 09 Dec 2019 08:09:26 -0500 Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-151-oCvewKo4NNy6_3WeX1hJ7Q-1; Mon, 09 Dec 2019 08:09:18 -0500 Received: from smtp.corp.redhat.com (int-mx04.intmail.prod.int.phx2.redhat.com [10.5.11.14]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id 7C88318AAFA1 for ; Mon, 9 Dec 2019 13:09:17 +0000 (UTC) Received: from dell-r430-03.lab.eng.brq.redhat.com (dell-r430-03.lab.eng.brq.redhat.com [10.37.153.18]) by smtp.corp.redhat.com (Postfix) with ESMTP id 56D525D9D6; Mon, 9 Dec 2019 13:09:16 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1575896965; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=B7uZeO4NcyE8AIY+HXwj6iY7M5kyj0Ki4tjCJ8qqRSA=; b=KPg5iIbXAcbIMZhsKXFoLYDk+/geCtkPFcPUmmy/reErmZ1Ce/spSkgUlEBHjKxuuyhkyT QHnBPN3IhjPJzC0oamAvvTg15UQLh0TLh7JDyG4boMv0bYV0g5QwZDSvBGK6wnXmgPH33W bQojGVCnlC0idX4Ky6tgTd59A5SRGd8= From: Igor Mammedov To: qemu-devel@nongnu.org Subject: [PATCH for-5.0 v2 8/9] acpi: cpuhp: spec: add typical usecases Date: Mon, 9 Dec 2019 14:09:01 +0100 Message-Id: <1575896942-331151-9-git-send-email-imammedo@redhat.com> In-Reply-To: <1575896942-331151-1-git-send-email-imammedo@redhat.com> References: <1575896942-331151-1-git-send-email-imammedo@redhat.com> X-Scanned-By: MIMEDefang 2.79 on 10.5.11.14 X-MC-Unique: oCvewKo4NNy6_3WeX1hJ7Q-1 X-Mimecast-Spam-Score: 0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 207.211.31.120 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: pbonzini@redhat.com, philmd@redhat.com, lersek@redhat.com, mst@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Document work-flows for * enabling/detecting modern CPU hotplug interface * finding a CPU with pending 'insert/remove' event * enumerating present and possible CPUs Signed-off-by: Igor Mammedov Reviewed-by: Laszlo Ersek --- v2: - fix indent of "other values" that's just above being added "Typical usecases:" section - unindent "Typical usecases" to put it into right scope (Laszlo) - squash in ammended (using CPHP_GET_NEXT_CPU_WITH_EVENT_CMD) "acpi: cpuhp: spec: document procedure for enabling modern CPU hotplug" (Laszlo) --- docs/specs/acpi_cpu_hotplug.txt | 51 +++++++++++++++++++++++++++++++++++++= +--- 1 file changed, 48 insertions(+), 3 deletions(-) diff --git a/docs/specs/acpi_cpu_hotplug.txt b/docs/specs/acpi_cpu_hotplug.= txt index 9879f9e..cb99cf3 100644 --- a/docs/specs/acpi_cpu_hotplug.txt +++ b/docs/specs/acpi_cpu_hotplug.txt @@ -15,14 +15,14 @@ CPU present bitmap for: PIIX-PM (IO port 0xaf00-0xaf1f, 1-byte access) One bit per CPU. Bit position reflects corresponding CPU APIC ID. Read-o= nly. The first DWORD in bitmap is used in write mode to switch from legacy - to new CPU hotplug interface, write 0 into it to do switch. + to modern CPU hotplug interface, write 0 into it to do switch. --------------------------------------------------------------- QEMU sets corresponding CPU bit on hot-add event and issues SCI with GPE.2 event set. CPU present map is read by ACPI BIOS GPE.2 handler to notify OS about CPU hot-add events. CPU hot-remove isn't supported. =20 =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D -ACPI CPU hotplug interface registers: +Modern ACPI CPU hotplug interface registers: ------------------------------------- Register block base address: ICH9-LPC IO port 0x0cd8 @@ -67,6 +67,7 @@ write access: [0x0-0x3] CPU selector: (DWORD access) selects active CPU device. All following accesses to other registers will read/store data from/to selected CPU. + Valid values: [0 .. max_cpus) [0x4] CPU device control fields: (1 byte access) bits: 0: reserved, OSPM must clear it before writing to register. @@ -98,4 +99,48 @@ write access: 2: stores value into OST status register, triggers ACPI_DEVICE_OST QMP event from QEMU to external applicati= ons with current values of OST event and status registers. - other values: reserved + other values: reserved + +Typical usecases: + - (x86) Detecting and enabling modern CPU hotplug interface. + QEMU starts with legacy CPU hotplug interface enabled. Detecting and + switching to modern interface is based on the 2 legacy CPU hotplug f= eatures: + 1. Writes into CPU bitmap are ignored. + 2. CPU bitmap always has bit#0 set, corresponding to boot CPU. + + Use following steps to detect and enable modern CPU hotplug interfac= e: + 1. Store 0x0 to the 'CPU selector' register, + attempting to switch to modern mode + 2. Store 0x0 to the 'CPU selector' register, + to ensure valid selector value + 3. Store 0x0 to the 'Command field' register, + 4. Read the 'Command data 2' register. + If read value is 0x0, the modern interface is enabled. + Otherwise legacy or no CPU hotplug interface available + + - Get a cpu with pending event + 1. Store 0x0 to the 'CPU selector' register. + 2. Store 0x0 to the 'Command field' register. + 3. Read the 'CPU device status fields' register. + 4. If both bit#1 and bit#2 are clear in the value read, there is no = CPU + with a pending event and selected CPU remains unchanged. + 5. Otherwise, read the 'Command data' register. The value read is the + selector of the CPU with the pending event (which is already + selected). + + - Enumerate CPUs present/non present CPUs + 01. Set the present CPU count to 0. + 02. Set the iterator to 0. + 03. Store 0x0 to the 'CPU selector' register, to ensure that it's in + a valid state and that access to other registers won't be ignore= d. + 04. Store 0x0 to the 'Command field' register to make 'Command data' + register return 'CPU selector' value of selected CPU + 05. Read the 'CPU device status fields' register. + 06. If bit#0 is set, increment the present CPU count. + 07. Increment the iterator. + 08. Store the iterator to the 'CPU selector' register. + 09. Read the 'Command data' register. + 10. If the value read is not zero, goto 05. + 11. Otherwise store 0x0 to the 'CPU selector' register, to put it + into a valid state and exit. + The iterator at this point equals "max_cpus". --=20 2.7.4 From nobody Mon Apr 29 12:55:39 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1575897518; cv=none; d=zohomail.com; s=zohoarc; b=GT2LDa/rerwWK4/EF1783fNCFeJDTeA/AgERGuCN5iJi7WDnMpc/I1J2ZnXHBaLICfPzog68FGQeXnx26t3n9EhvcR6h3IFLM/pQRDmVKXEELOe4YQHXbe7f5rMH4e0wKZc0Rl7NfEd0sHUtNXKoC61nsHvZXj137C1fjMacG10= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; 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Mon, 9 Dec 2019 13:09:18 +0000 (UTC) Received: from dell-r430-03.lab.eng.brq.redhat.com (dell-r430-03.lab.eng.brq.redhat.com [10.37.153.18]) by smtp.corp.redhat.com (Postfix) with ESMTP id C59515D9D6; Mon, 9 Dec 2019 13:09:17 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1575896962; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=Hrv7w8oWl4v3zXpCbYG5A0WNpbhVP5sF5WD50lFPsPw=; b=MkIz07HGSllncnM3y980ppHC0Ol8SFkk33QWGNIOZ3n2+S/GaWnnM9RSdH1YBogWnH8k0s gCWAJ4/9jM9soxd98Rd8QusBrHl9O9jXW7IZLrDCraKh6k3wRNah3ofL9Rjzphxdh5AtgX ehrAS14idLUuzLfSRIBuIGM2GJ7m8GA= From: Igor Mammedov To: qemu-devel@nongnu.org Subject: [PATCH for-5.0 v2 9/9] acpi: cpuhp: add CPHP_GET_CPU_ID_CMD command Date: Mon, 9 Dec 2019 14:09:02 +0100 Message-Id: <1575896942-331151-10-git-send-email-imammedo@redhat.com> In-Reply-To: <1575896942-331151-1-git-send-email-imammedo@redhat.com> References: <1575896942-331151-1-git-send-email-imammedo@redhat.com> X-Scanned-By: MIMEDefang 2.79 on 10.5.11.14 X-MC-Unique: VTTKusSIPR6YK4w95mlRhA-1 X-Mimecast-Spam-Score: 0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 205.139.110.120 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: pbonzini@redhat.com, philmd@redhat.com, lersek@redhat.com, mst@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Firmware can enumerate present at boot APs by broadcasting wakeup IPI, so that woken up secondary CPUs could register them-selves. However in CPU hotplug case, it would need to know architecture specific CPU IDs for possible and hotplugged CPUs so it could prepare environment for and wake hotplugged AP. Reuse and extend existing CPU hotplug interface to return architecture specific ID for currently selected CPU in 2 registers: - lower 32 bits in ACPI_CPU_CMD_DATA_OFFSET_RW - upper 32 bits in ACPI_CPU_CMD_DATA2_OFFSET_R On x86, firmware will use CPHP_GET_CPU_ID_CMD for fetching the APIC ID when handling hotplug SMI. Later, CPHP_GET_CPU_ID_CMD will be used on ARM to retrieve MPIDR, which serves the similar to APIC ID purpose. Signed-off-by: Igor Mammedov Reviewed-by: Laszlo Ersek --- v1: - s/ACPI_CPU_CMD_DATA2_OFFSET_RW/ACPI_CPU_CMD_DATA2_OFFSET_R/. v2: - ACPI_CPU_CMD_DATA2_OFFSET_R moved into separate patch that adds 'Command data 2' field separately - ammend commit message --- docs/specs/acpi_cpu_hotplug.txt | 3 +++ hw/acpi/cpu.c | 7 +++++++ 2 files changed, 10 insertions(+) diff --git a/docs/specs/acpi_cpu_hotplug.txt b/docs/specs/acpi_cpu_hotplug.= txt index cb99cf3..a8ce5e7 100644 --- a/docs/specs/acpi_cpu_hotplug.txt +++ b/docs/specs/acpi_cpu_hotplug.txt @@ -47,6 +47,7 @@ read access: [0x0-0x3] Command data 2: (DWORD access) if value last stored in 'Command field': 0: reads as 0x0 + 3: upper 32 bits of architecture specific CPU ID value other values: reserved [0x4] CPU device status fields: (1 byte access) bits: @@ -61,6 +62,8 @@ read access: [0x8] Command data: (DWORD access) contains 0 unless value last stored in 'Command field' is one of: 0: contains 'CPU selector' value of a CPU with pending event= [s] + 3: lower 32 bits of architecture specific CPU ID value + (in x86 case: APIC ID) =20 write access: offset: diff --git a/hw/acpi/cpu.c b/hw/acpi/cpu.c index d475c06..e2c957c 100644 --- a/hw/acpi/cpu.c +++ b/hw/acpi/cpu.c @@ -18,6 +18,7 @@ enum { CPHP_GET_NEXT_CPU_WITH_EVENT_CMD =3D 0, CPHP_OST_EVENT_CMD =3D 1, CPHP_OST_STATUS_CMD =3D 2, + CPHP_GET_CPU_ID_CMD =3D 3, CPHP_CMD_MAX }; =20 @@ -75,6 +76,9 @@ static uint64_t cpu_hotplug_rd(void *opaque, hwaddr addr,= unsigned size) case CPHP_GET_NEXT_CPU_WITH_EVENT_CMD: val =3D cpu_st->selector; break; + case CPHP_GET_CPU_ID_CMD: + val =3D cdev->arch_id & 0xFFFFFFFF; + break; default: break; } @@ -85,6 +89,9 @@ static uint64_t cpu_hotplug_rd(void *opaque, hwaddr addr,= unsigned size) case CPHP_GET_NEXT_CPU_WITH_EVENT_CMD: val =3D 0; break; + case CPHP_GET_CPU_ID_CMD: + val =3D cdev->arch_id >> 32; + break; default: break; } --=20 2.7.4