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Violators will be prosecuted; (version=TLSv1/SSLv3 cipher=AES256-GCM-SHA384 bits=256/256) Fri, 6 Dec 2019 18:43:56 -0000 Received: from d06av23.portsmouth.uk.ibm.com (d06av23.portsmouth.uk.ibm.com [9.149.105.59]) by b06cxnps4075.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id xB6Ihtft12058854 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Fri, 6 Dec 2019 18:43:55 GMT Received: from d06av23.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 42644A404D; Fri, 6 Dec 2019 18:43:55 +0000 (GMT) Received: from d06av23.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id CA976A4040; Fri, 6 Dec 2019 18:43:54 +0000 (GMT) Received: from bahia.lan (unknown [9.145.42.200]) by d06av23.portsmouth.uk.ibm.com (Postfix) with ESMTP; Fri, 6 Dec 2019 18:43:54 +0000 (GMT) Subject: [for-5.0 PATCH 1/3] cpu: Introduce CPUReset callback typedef From: Greg Kurz To: Eduardo Habkost Date: Fri, 06 Dec 2019 19:43:54 +0100 In-Reply-To: <157565782864.3897844.627720481210693346.stgit@bahia.lan> References: <157565782864.3897844.627720481210693346.stgit@bahia.lan> User-Agent: StGit/unknown-version MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 x-cbid: 19120618-0020-0000-0000-000003951162 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 19120618-0021-0000-0000-000021EC461D Message-Id: <157565783446.3897844.13799667957070272380.stgit@bahia.lan> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.95,18.0.572 definitions=2019-12-06_06:2019-12-05,2019-12-06 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 mlxscore=0 lowpriorityscore=0 bulkscore=0 spamscore=0 suspectscore=0 adultscore=0 malwarescore=0 impostorscore=0 clxscore=1034 mlxlogscore=999 phishscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-1910280000 definitions=main-1912060152 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [generic] [fuzzy] X-Received-From: 148.163.156.1 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Laurent Vivier , Peter Maydell , David Hildenbrand , Cornelia Huck , qemu-devel@nongnu.org, Alistair Francis , Paolo Bonzini , Philippe =?utf-8?q?Mathieu-Daud=C3=A9?= , David Gibson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Use it in include/hw/core/cpu.h and convert all targets to use it as well with: perl -pi \ -e 's/void\s+\(\*(parent_reset)\)\(CPUState\s+\*\w+\)/CPUReset \1/;' \ $(git ls-files 'target/*.h') Signed-off-by: Greg Kurz Acked-by: David Gibson Reviewed-by: Alistair Francis --- include/hw/core/cpu.h | 4 +++- target/alpha/cpu-qom.h | 2 +- target/arm/cpu-qom.h | 2 +- target/cris/cpu-qom.h | 2 +- target/hppa/cpu-qom.h | 2 +- target/i386/cpu-qom.h | 2 +- target/lm32/cpu-qom.h | 2 +- target/m68k/cpu-qom.h | 2 +- target/microblaze/cpu-qom.h | 2 +- target/mips/cpu-qom.h | 2 +- target/moxie/cpu.h | 2 +- target/nios2/cpu.h | 2 +- target/openrisc/cpu.h | 2 +- target/ppc/cpu-qom.h | 2 +- target/riscv/cpu.h | 2 +- target/s390x/cpu-qom.h | 2 +- target/sh4/cpu-qom.h | 2 +- target/sparc/cpu-qom.h | 2 +- target/tilegx/cpu.h | 2 +- target/tricore/cpu-qom.h | 2 +- target/xtensa/cpu-qom.h | 2 +- 21 files changed, 23 insertions(+), 21 deletions(-) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index 77c6f0529903..047e3972ecaf 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -74,6 +74,8 @@ typedef struct CPUWatchpoint CPUWatchpoint; =20 struct TranslationBlock; =20 +typedef void (*CPUReset)(CPUState *cpu); + /** * CPUClass: * @class_by_name: Callback to map -cpu command line model name to an @@ -165,7 +167,7 @@ typedef struct CPUClass { ObjectClass *(*class_by_name)(const char *cpu_model); void (*parse_features)(const char *typename, char *str, Error **errp); =20 - void (*reset)(CPUState *cpu); + CPUReset reset; int reset_dump_flags; bool (*has_work)(CPUState *cpu); void (*do_interrupt)(CPUState *cpu); diff --git a/target/alpha/cpu-qom.h b/target/alpha/cpu-qom.h index 6f0a0adb9efa..0c974805481b 100644 --- a/target/alpha/cpu-qom.h +++ b/target/alpha/cpu-qom.h @@ -44,7 +44,7 @@ typedef struct AlphaCPUClass { /*< public >*/ =20 DeviceRealize parent_realize; - void (*parent_reset)(CPUState *cpu); + CPUReset parent_reset; } AlphaCPUClass; =20 typedef struct AlphaCPU AlphaCPU; diff --git a/target/arm/cpu-qom.h b/target/arm/cpu-qom.h index 7f5b244bde35..aeaa84afcc9a 100644 --- a/target/arm/cpu-qom.h +++ b/target/arm/cpu-qom.h @@ -51,7 +51,7 @@ typedef struct ARMCPUClass { =20 const ARMCPUInfo *info; DeviceRealize parent_realize; - void (*parent_reset)(CPUState *cpu); + CPUReset parent_reset; } ARMCPUClass; =20 typedef struct ARMCPU ARMCPU; diff --git a/target/cris/cpu-qom.h b/target/cris/cpu-qom.h index 308c1f95bdf6..079ffe6bda0a 100644 --- a/target/cris/cpu-qom.h +++ b/target/cris/cpu-qom.h @@ -45,7 +45,7 @@ typedef struct CRISCPUClass { /*< public >*/ =20 DeviceRealize parent_realize; - void (*parent_reset)(CPUState *cpu); + CPUReset parent_reset; =20 uint32_t vr; } CRISCPUClass; diff --git a/target/hppa/cpu-qom.h b/target/hppa/cpu-qom.h index 6367dc479391..5c129de148a8 100644 --- a/target/hppa/cpu-qom.h +++ b/target/hppa/cpu-qom.h @@ -44,7 +44,7 @@ typedef struct HPPACPUClass { /*< public >*/ =20 DeviceRealize parent_realize; - void (*parent_reset)(CPUState *cpu); + CPUReset parent_reset; } HPPACPUClass; =20 typedef struct HPPACPU HPPACPU; diff --git a/target/i386/cpu-qom.h b/target/i386/cpu-qom.h index 0efab2fc670f..1e962518e68e 100644 --- a/target/i386/cpu-qom.h +++ b/target/i386/cpu-qom.h @@ -71,7 +71,7 @@ typedef struct X86CPUClass { =20 DeviceRealize parent_realize; DeviceUnrealize parent_unrealize; - void (*parent_reset)(CPUState *cpu); + CPUReset parent_reset; } X86CPUClass; =20 typedef struct X86CPU X86CPU; diff --git a/target/lm32/cpu-qom.h b/target/lm32/cpu-qom.h index dc9ac9ac9f7b..e105a315aa3e 100644 --- a/target/lm32/cpu-qom.h +++ b/target/lm32/cpu-qom.h @@ -44,7 +44,7 @@ typedef struct LM32CPUClass { /*< public >*/ =20 DeviceRealize parent_realize; - void (*parent_reset)(CPUState *cpu); + CPUReset parent_reset; } LM32CPUClass; =20 typedef struct LM32CPU LM32CPU; diff --git a/target/m68k/cpu-qom.h b/target/m68k/cpu-qom.h index b56da8a21374..0a196775e5d1 100644 --- a/target/m68k/cpu-qom.h +++ b/target/m68k/cpu-qom.h @@ -44,7 +44,7 @@ typedef struct M68kCPUClass { /*< public >*/ =20 DeviceRealize parent_realize; - void (*parent_reset)(CPUState *cpu); + CPUReset parent_reset; } M68kCPUClass; =20 typedef struct M68kCPU M68kCPU; diff --git a/target/microblaze/cpu-qom.h b/target/microblaze/cpu-qom.h index 49b07cc697b9..7a4ff4a11e33 100644 --- a/target/microblaze/cpu-qom.h +++ b/target/microblaze/cpu-qom.h @@ -44,7 +44,7 @@ typedef struct MicroBlazeCPUClass { /*< public >*/ =20 DeviceRealize parent_realize; - void (*parent_reset)(CPUState *cpu); + CPUReset parent_reset; } MicroBlazeCPUClass; =20 typedef struct MicroBlazeCPU MicroBlazeCPU; diff --git a/target/mips/cpu-qom.h b/target/mips/cpu-qom.h index a430c0fe4bbf..818401a501cb 100644 --- a/target/mips/cpu-qom.h +++ b/target/mips/cpu-qom.h @@ -48,7 +48,7 @@ typedef struct MIPSCPUClass { /*< public >*/ =20 DeviceRealize parent_realize; - void (*parent_reset)(CPUState *cpu); + CPUReset parent_reset; const struct mips_def_t *cpu_def; } MIPSCPUClass; =20 diff --git a/target/moxie/cpu.h b/target/moxie/cpu.h index 01dca548e5d5..20dafc80f6ac 100644 --- a/target/moxie/cpu.h +++ b/target/moxie/cpu.h @@ -69,7 +69,7 @@ typedef struct MoxieCPUClass { /*< public >*/ =20 DeviceRealize parent_realize; - void (*parent_reset)(CPUState *cpu); + CPUReset parent_reset; } MoxieCPUClass; =20 /** diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h index 361b06ffeb61..59a07a5d0ee0 100644 --- a/target/nios2/cpu.h +++ b/target/nios2/cpu.h @@ -50,7 +50,7 @@ typedef struct Nios2CPUClass { /*< public >*/ =20 DeviceRealize parent_realize; - void (*parent_reset)(CPUState *cpu); + CPUReset parent_reset; } Nios2CPUClass; =20 #define TARGET_HAS_ICE 1 diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h index 0ad02eab7946..d77976ccce7f 100644 --- a/target/openrisc/cpu.h +++ b/target/openrisc/cpu.h @@ -48,7 +48,7 @@ typedef struct OpenRISCCPUClass { /*< public >*/ =20 DeviceRealize parent_realize; - void (*parent_reset)(CPUState *cpu); + CPUReset parent_reset; } OpenRISCCPUClass; =20 #define TARGET_INSN_START_EXTRA_WORDS 1 diff --git a/target/ppc/cpu-qom.h b/target/ppc/cpu-qom.h index e499575dc873..9a20e5a1bfea 100644 --- a/target/ppc/cpu-qom.h +++ b/target/ppc/cpu-qom.h @@ -166,7 +166,7 @@ typedef struct PowerPCCPUClass { =20 DeviceRealize parent_realize; DeviceUnrealize parent_unrealize; - void (*parent_reset)(CPUState *cpu); + CPUReset parent_reset; void (*parent_parse_features)(const char *type, char *str, Error **err= p); =20 uint32_t pvr; diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index e59343e13c02..2246f95b3f33 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -185,7 +185,7 @@ typedef struct RISCVCPUClass { CPUClass parent_class; /*< public >*/ DeviceRealize parent_realize; - void (*parent_reset)(CPUState *cpu); + CPUReset parent_reset; } RISCVCPUClass; =20 /** diff --git a/target/s390x/cpu-qom.h b/target/s390x/cpu-qom.h index b809ec8418e0..cc23edc92198 100644 --- a/target/s390x/cpu-qom.h +++ b/target/s390x/cpu-qom.h @@ -55,7 +55,7 @@ typedef struct S390CPUClass { const char *desc; =20 DeviceRealize parent_realize; - void (*parent_reset)(CPUState *cpu); + CPUReset parent_reset; void (*load_normal)(CPUState *cpu); void (*cpu_reset)(CPUState *cpu); void (*initial_cpu_reset)(CPUState *cpu); diff --git a/target/sh4/cpu-qom.h b/target/sh4/cpu-qom.h index 0c56d055bada..35732a367427 100644 --- a/target/sh4/cpu-qom.h +++ b/target/sh4/cpu-qom.h @@ -51,7 +51,7 @@ typedef struct SuperHCPUClass { /*< public >*/ =20 DeviceRealize parent_realize; - void (*parent_reset)(CPUState *cpu); + CPUReset parent_reset; =20 uint32_t pvr; uint32_t prr; diff --git a/target/sparc/cpu-qom.h b/target/sparc/cpu-qom.h index 7442e2768e88..93165bd24f1c 100644 --- a/target/sparc/cpu-qom.h +++ b/target/sparc/cpu-qom.h @@ -49,7 +49,7 @@ typedef struct SPARCCPUClass { /*< public >*/ =20 DeviceRealize parent_realize; - void (*parent_reset)(CPUState *cpu); + CPUReset parent_reset; sparc_def_t *cpu_def; } SPARCCPUClass; =20 diff --git a/target/tilegx/cpu.h b/target/tilegx/cpu.h index 9cbec247d238..68bd509898d4 100644 --- a/target/tilegx/cpu.h +++ b/target/tilegx/cpu.h @@ -118,7 +118,7 @@ typedef struct TileGXCPUClass { /*< public >*/ =20 DeviceRealize parent_realize; - void (*parent_reset)(CPUState *cpu); + CPUReset parent_reset; } TileGXCPUClass; =20 /** diff --git a/target/tricore/cpu-qom.h b/target/tricore/cpu-qom.h index 7c1e130b4ede..f613452b00e0 100644 --- a/target/tricore/cpu-qom.h +++ b/target/tricore/cpu-qom.h @@ -36,7 +36,7 @@ typedef struct TriCoreCPUClass { /*< public >*/ =20 DeviceRealize parent_realize; - void (*parent_reset)(CPUState *cpu); + CPUReset parent_reset; } TriCoreCPUClass; =20 typedef struct TriCoreCPU TriCoreCPU; diff --git a/target/xtensa/cpu-qom.h b/target/xtensa/cpu-qom.h index 9ac54241bd69..685d7b8d823a 100644 --- a/target/xtensa/cpu-qom.h +++ b/target/xtensa/cpu-qom.h @@ -56,7 +56,7 @@ typedef struct XtensaCPUClass { /*< public >*/ =20 DeviceRealize parent_realize; - void (*parent_reset)(CPUState *cpu); + CPUReset parent_reset; =20 const XtensaConfig *config; } XtensaCPUClass; From nobody Sun May 5 22:58:32 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1575658088; cv=none; d=zohomail.com; s=zohoarc; b=nUz3q0y9kWE3FvlSrzRS2ku6jgJDcUYo0UMoG/GWATQAt+rCMktZfG7LSR9ELK09zCgV58hpkicb6K7JDNLVukyuQeBpWvoIbeYZ19Tpc07mGjfv6wt3QIUdwsCe8Z2weG2nwBOTisuPdrfbVrrBd96Y5jFNUqF9mSpWQXACV1c= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1575658088; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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Violators will be prosecuted; (version=TLSv1/SSLv3 cipher=AES256-GCM-SHA384 bits=256/256) Fri, 6 Dec 2019 18:44:01 -0000 Received: from d06av24.portsmouth.uk.ibm.com (d06av24.portsmouth.uk.ibm.com [9.149.105.60]) by b06avi18626390.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id xB6IhKxj49152398 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Fri, 6 Dec 2019 18:43:20 GMT Received: from d06av24.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 01E2B4203F; Fri, 6 Dec 2019 18:44:01 +0000 (GMT) Received: from d06av24.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 9C60142041; Fri, 6 Dec 2019 18:44:00 +0000 (GMT) Received: from bahia.lan (unknown [9.145.42.200]) by d06av24.portsmouth.uk.ibm.com (Postfix) with ESMTP; Fri, 6 Dec 2019 18:44:00 +0000 (GMT) Subject: [for-5.0 PATCH 2/3] cpu: Introduce cpu_class_set_parent_reset() From: Greg Kurz To: Eduardo Habkost Date: Fri, 06 Dec 2019 19:44:00 +0100 In-Reply-To: <157565782864.3897844.627720481210693346.stgit@bahia.lan> References: <157565782864.3897844.627720481210693346.stgit@bahia.lan> User-Agent: StGit/unknown-version MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 x-cbid: 19120618-4275-0000-0000-0000038C7C40 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 19120618-4276-0000-0000-000038A025FE Message-Id: <157565784026.3897844.6515055734977835356.stgit@bahia.lan> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.95,18.0.572 definitions=2019-12-06_06:2019-12-05,2019-12-06 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 suspectscore=0 phishscore=0 priorityscore=1501 spamscore=0 malwarescore=0 adultscore=0 bulkscore=0 clxscore=1034 mlxlogscore=777 lowpriorityscore=0 mlxscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-1910280000 definitions=main-1912060152 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [generic] [fuzzy] X-Received-From: 148.163.156.1 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Laurent Vivier , Peter Maydell , David Hildenbrand , Cornelia Huck , qemu-devel@nongnu.org, Alistair Francis , Paolo Bonzini , Philippe =?utf-8?q?Mathieu-Daud=C3=A9?= , David Gibson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Similarly to what we already do with qdev, use a helper to overload the reset QOM methods of the parent in children classes, for clarity. Signed-off-by: Greg Kurz Reviewed-by: Alistair Francis Reviewed-by: Cornelia Huck Reviewed-by: David Gibson --- hw/core/cpu.c | 8 ++++++++ include/hw/core/cpu.h | 4 ++++ 2 files changed, 12 insertions(+) diff --git a/hw/core/cpu.c b/hw/core/cpu.c index db1a03c6bbb3..6dad2c8488a9 100644 --- a/hw/core/cpu.c +++ b/hw/core/cpu.c @@ -239,6 +239,14 @@ void cpu_dump_statistics(CPUState *cpu, int flags) } } =20 +void cpu_class_set_parent_reset(CPUClass *cc, + CPUReset child_reset, + CPUReset *parent_reset) +{ + *parent_reset =3D cc->reset; + cc->reset =3D child_reset; +} + void cpu_reset(CPUState *cpu) { CPUClass *klass =3D CPU_GET_CLASS(cpu); diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index 047e3972ecaf..6680f4b047f4 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -1137,6 +1137,10 @@ void cpu_exec_unrealizefn(CPUState *cpu); */ bool target_words_bigendian(void); =20 +void cpu_class_set_parent_reset(CPUClass *cc, + CPUReset child_reset, + CPUReset *parent_reset); + #ifdef NEED_CPU_H =20 #ifdef CONFIG_SOFTMMU From nobody Sun May 5 22:58:32 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1575658117; cv=none; d=zohomail.com; s=zohoarc; b=m5Lri2n9qPuQ6CGE/ekHXKCuxHUO5j6krqNAQ/o6pF/dK/gEOI3wyaKTDes8bFT0BrieTC6++pTNmJvaqFVn4IIBC+GjSw0KbU3FLvtJEMoo3Gr1zffvx5nKWLlaqWalNj1wpPXIMBz7FqTQ5/+Nah18cBI8ezHvYy9aagXBT90= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1575658117; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=peJVK0iDLAaEpxUpaNVkUrNC+ccXrwk4TMPwNQxWfpM=; b=XwHwkGA0BRCjFrNpFy1K38QvW6M+QBH8gmRz+tMOmjD3ddhy8w2zX5kziT77QaFOg5E2hYl3kq/2z0545AYvrjrBAIm/Tle2wx4FWbj9samP4pfvzUejlbWfGyNuI2QbmC2NwogOAhxv7x1tZ/lgFuhq5qsOReY4BMsjJhhNUWA= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 157565811795036.182972876368126; Fri, 6 Dec 2019 10:48:37 -0800 (PST) Received: from localhost ([::1]:43844 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1idIea-0004ns-AQ for importer@patchew.org; Fri, 06 Dec 2019 13:48:36 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:51337) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1idIaR-00023X-DU for qemu-devel@nongnu.org; Fri, 06 Dec 2019 13:44:21 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1idIaP-0003Fj-1w for qemu-devel@nongnu.org; Fri, 06 Dec 2019 13:44:19 -0500 Received: from mx0a-001b2d01.pphosted.com ([148.163.156.1]:24422) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1idIaM-0003E9-Tu for qemu-devel@nongnu.org; Fri, 06 Dec 2019 13:44:15 -0500 Received: from pps.filterd (m0098399.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id xB6IhUDw013571 for ; Fri, 6 Dec 2019 13:44:13 -0500 Received: from e06smtp02.uk.ibm.com (e06smtp02.uk.ibm.com [195.75.94.98]) by mx0a-001b2d01.pphosted.com with ESMTP id 2wq9hmrhny-1 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=NOT) for ; Fri, 06 Dec 2019 13:44:13 -0500 Received: from localhost by e06smtp02.uk.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; (version=TLSv1/SSLv3 cipher=AES256-GCM-SHA384 bits=256/256) Fri, 6 Dec 2019 18:44:07 -0000 Received: from d06av25.portsmouth.uk.ibm.com (d06av25.portsmouth.uk.ibm.com [9.149.105.61]) by b06cxnps3075.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id xB6Ii6Ah58458270 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Fri, 6 Dec 2019 18:44:06 GMT Received: from d06av25.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id CA76511C04A; Fri, 6 Dec 2019 18:44:06 +0000 (GMT) Received: from d06av25.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 651C011C04C; Fri, 6 Dec 2019 18:44:06 +0000 (GMT) Received: from bahia.lan (unknown [9.145.42.200]) by d06av25.portsmouth.uk.ibm.com (Postfix) with ESMTP; Fri, 6 Dec 2019 18:44:06 +0000 (GMT) Subject: [for-5.0 PATCH 3/3] cpu: Use cpu_class_set_parent_reset() From: Greg Kurz To: Eduardo Habkost Date: Fri, 06 Dec 2019 19:44:06 +0100 In-Reply-To: <157565782864.3897844.627720481210693346.stgit@bahia.lan> References: <157565782864.3897844.627720481210693346.stgit@bahia.lan> User-Agent: StGit/unknown-version MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 x-cbid: 19120618-0008-0000-0000-0000033E595B X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 19120618-0009-0000-0000-00004A5D8177 Message-Id: <157565784603.3897844.16391025294328116481.stgit@bahia.lan> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.95,18.0.572 definitions=2019-12-06_06:2019-12-05,2019-12-06 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 bulkscore=0 lowpriorityscore=0 adultscore=0 suspectscore=0 impostorscore=0 clxscore=1034 spamscore=0 mlxlogscore=999 phishscore=0 mlxscore=0 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-1910280000 definitions=main-1912060152 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [generic] [fuzzy] X-Received-From: 148.163.156.1 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Laurent Vivier , Peter Maydell , David Hildenbrand , Cornelia Huck , qemu-devel@nongnu.org, Alistair Francis , Paolo Bonzini , Philippe =?utf-8?q?Mathieu-Daud=C3=A9?= , David Gibson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Convert all targets to use cpu_class_set_parent_reset() with the following coccinelle script: @@ type CPUParentClass; CPUParentClass *pcc; CPUClass *cc; identifier parent_fn; identifier child_fn; @@ +cpu_class_set_parent_reset(cc, child_fn, &pcc->parent_fn); -pcc->parent_fn =3D cc->reset; ... -cc->reset =3D child_fn; Signed-off-by: Greg Kurz Acked-by: David Gibson Reviewed-by: Alistair Francis --- target/arm/cpu.c | 3 +-- target/cris/cpu.c | 3 +-- target/i386/cpu.c | 3 +-- target/lm32/cpu.c | 3 +-- target/m68k/cpu.c | 3 +-- target/microblaze/cpu.c | 3 +-- target/mips/cpu.c | 3 +-- target/moxie/cpu.c | 3 +-- target/nios2/cpu.c | 3 +-- target/openrisc/cpu.c | 3 +-- target/ppc/translate_init.inc.c | 3 +-- target/riscv/cpu.c | 3 +-- target/s390x/cpu.c | 3 +-- target/sh4/cpu.c | 3 +-- target/sparc/cpu.c | 3 +-- target/tilegx/cpu.c | 3 +-- target/tricore/cpu.c | 3 +-- target/xtensa/cpu.c | 3 +-- 18 files changed, 18 insertions(+), 36 deletions(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 7a4ac9339bf9..712a9425fdf5 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -2625,8 +2625,7 @@ static void arm_cpu_class_init(ObjectClass *oc, void = *data) &acc->parent_realize); dc->props =3D arm_cpu_properties; =20 - acc->parent_reset =3D cc->reset; - cc->reset =3D arm_cpu_reset; + cpu_class_set_parent_reset(cc, arm_cpu_reset, &acc->parent_reset); =20 cc->class_by_name =3D arm_cpu_class_by_name; cc->has_work =3D arm_cpu_has_work; diff --git a/target/cris/cpu.c b/target/cris/cpu.c index 7adfd6caf4ed..486675e3822f 100644 --- a/target/cris/cpu.c +++ b/target/cris/cpu.c @@ -256,8 +256,7 @@ static void cris_cpu_class_init(ObjectClass *oc, void *= data) device_class_set_parent_realize(dc, cris_cpu_realizefn, &ccc->parent_realize); =20 - ccc->parent_reset =3D cc->reset; - cc->reset =3D cris_cpu_reset; + cpu_class_set_parent_reset(cc, cris_cpu_reset, &ccc->parent_reset); =20 cc->class_by_name =3D cris_cpu_class_by_name; cc->has_work =3D cris_cpu_has_work; diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 69f518a21a9b..57d36931725d 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -7049,8 +7049,7 @@ static void x86_cpu_common_class_init(ObjectClass *oc= , void *data) &xcc->parent_unrealize); dc->props =3D x86_cpu_properties; =20 - xcc->parent_reset =3D cc->reset; - cc->reset =3D x86_cpu_reset; + cpu_class_set_parent_reset(cc, x86_cpu_reset, &xcc->parent_reset); cc->reset_dump_flags =3D CPU_DUMP_FPU | CPU_DUMP_CCOP; =20 cc->class_by_name =3D x86_cpu_class_by_name; diff --git a/target/lm32/cpu.c b/target/lm32/cpu.c index b35537de6285..687bf35e6588 100644 --- a/target/lm32/cpu.c +++ b/target/lm32/cpu.c @@ -218,8 +218,7 @@ static void lm32_cpu_class_init(ObjectClass *oc, void *= data) =20 device_class_set_parent_realize(dc, lm32_cpu_realizefn, &lcc->parent_realize); - lcc->parent_reset =3D cc->reset; - cc->reset =3D lm32_cpu_reset; + cpu_class_set_parent_reset(cc, lm32_cpu_reset, &lcc->parent_reset); =20 cc->class_by_name =3D lm32_cpu_class_by_name; cc->has_work =3D lm32_cpu_has_work; diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c index e6596de29c2c..176d95e6fcfb 100644 --- a/target/m68k/cpu.c +++ b/target/m68k/cpu.c @@ -257,8 +257,7 @@ static void m68k_cpu_class_init(ObjectClass *c, void *d= ata) =20 device_class_set_parent_realize(dc, m68k_cpu_realizefn, &mcc->parent_realize); - mcc->parent_reset =3D cc->reset; - cc->reset =3D m68k_cpu_reset; + cpu_class_set_parent_reset(cc, m68k_cpu_reset, &mcc->parent_reset); =20 cc->class_by_name =3D m68k_cpu_class_by_name; cc->has_work =3D m68k_cpu_has_work; diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index 9cfd7445e7da..71d88f603b2e 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -292,8 +292,7 @@ static void mb_cpu_class_init(ObjectClass *oc, void *da= ta) =20 device_class_set_parent_realize(dc, mb_cpu_realizefn, &mcc->parent_realize); - mcc->parent_reset =3D cc->reset; - cc->reset =3D mb_cpu_reset; + cpu_class_set_parent_reset(cc, mb_cpu_reset, &mcc->parent_reset); =20 cc->class_by_name =3D mb_cpu_class_by_name; cc->has_work =3D mb_cpu_has_work; diff --git a/target/mips/cpu.c b/target/mips/cpu.c index bbcf7ca4635c..6cd6b9650baa 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -189,8 +189,7 @@ static void mips_cpu_class_init(ObjectClass *c, void *d= ata) =20 device_class_set_parent_realize(dc, mips_cpu_realizefn, &mcc->parent_realize); - mcc->parent_reset =3D cc->reset; - cc->reset =3D mips_cpu_reset; + cpu_class_set_parent_reset(cc, mips_cpu_reset, &mcc->parent_reset); =20 cc->class_by_name =3D mips_cpu_class_by_name; cc->has_work =3D mips_cpu_has_work; diff --git a/target/moxie/cpu.c b/target/moxie/cpu.c index 48996d0554f2..cf47bc709b54 100644 --- a/target/moxie/cpu.c +++ b/target/moxie/cpu.c @@ -101,8 +101,7 @@ static void moxie_cpu_class_init(ObjectClass *oc, void = *data) =20 device_class_set_parent_realize(dc, moxie_cpu_realizefn, &mcc->parent_realize); - mcc->parent_reset =3D cc->reset; - cc->reset =3D moxie_cpu_reset; + cpu_class_set_parent_reset(cc, moxie_cpu_reset, &mcc->parent_reset); =20 cc->class_by_name =3D moxie_cpu_class_by_name; =20 diff --git a/target/nios2/cpu.c b/target/nios2/cpu.c index ca9c7a6df5d1..bbdbc0c6fbf0 100644 --- a/target/nios2/cpu.c +++ b/target/nios2/cpu.c @@ -188,8 +188,7 @@ static void nios2_cpu_class_init(ObjectClass *oc, void = *data) device_class_set_parent_realize(dc, nios2_cpu_realizefn, &ncc->parent_realize); dc->props =3D nios2_properties; - ncc->parent_reset =3D cc->reset; - cc->reset =3D nios2_cpu_reset; + cpu_class_set_parent_reset(cc, nios2_cpu_reset, &ncc->parent_reset); =20 cc->class_by_name =3D nios2_cpu_class_by_name; cc->has_work =3D nios2_cpu_has_work; diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c index 506aec6bfba5..5cd04dafab69 100644 --- a/target/openrisc/cpu.c +++ b/target/openrisc/cpu.c @@ -150,8 +150,7 @@ static void openrisc_cpu_class_init(ObjectClass *oc, vo= id *data) =20 device_class_set_parent_realize(dc, openrisc_cpu_realizefn, &occ->parent_realize); - occ->parent_reset =3D cc->reset; - cc->reset =3D openrisc_cpu_reset; + cpu_class_set_parent_reset(cc, openrisc_cpu_reset, &occ->parent_reset); =20 cc->class_by_name =3D openrisc_cpu_class_by_name; cc->has_work =3D openrisc_cpu_has_work; diff --git a/target/ppc/translate_init.inc.c b/target/ppc/translate_init.in= c.c index ba726dec4d00..e5773a99fffd 100644 --- a/target/ppc/translate_init.inc.c +++ b/target/ppc/translate_init.inc.c @@ -10614,8 +10614,7 @@ static void ppc_cpu_class_init(ObjectClass *oc, voi= d *data) pcc->interrupts_big_endian =3D ppc_cpu_interrupts_big_endian_always; dc->props =3D ppc_cpu_properties; =20 - pcc->parent_reset =3D cc->reset; - cc->reset =3D ppc_cpu_reset; + cpu_class_set_parent_reset(cc, ppc_cpu_reset, &pcc->parent_reset); =20 cc->class_by_name =3D ppc_cpu_class_by_name; pcc->parent_parse_features =3D cc->parse_features; diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index d37861a4305b..d6f187272859 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -462,8 +462,7 @@ static void riscv_cpu_class_init(ObjectClass *c, void *= data) device_class_set_parent_realize(dc, riscv_cpu_realize, &mcc->parent_realize); =20 - mcc->parent_reset =3D cc->reset; - cc->reset =3D riscv_cpu_reset; + cpu_class_set_parent_reset(cc, riscv_cpu_reset, &mcc->parent_reset); =20 cc->class_by_name =3D riscv_cpu_class_by_name; cc->has_work =3D riscv_cpu_has_work; diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c index 3abe7e80fd0a..cf7cf5655fbc 100644 --- a/target/s390x/cpu.c +++ b/target/s390x/cpu.c @@ -469,13 +469,12 @@ static void s390_cpu_class_init(ObjectClass *oc, void= *data) dc->props =3D s390x_cpu_properties; dc->user_creatable =3D true; =20 - scc->parent_reset =3D cc->reset; + cpu_class_set_parent_reset(cc, s390_cpu_full_reset, &scc->parent_reset= ); #if !defined(CONFIG_USER_ONLY) scc->load_normal =3D s390_cpu_load_normal; #endif scc->cpu_reset =3D s390_cpu_reset; scc->initial_cpu_reset =3D s390_cpu_initial_reset; - cc->reset =3D s390_cpu_full_reset; cc->class_by_name =3D s390_cpu_class_by_name, cc->has_work =3D s390_cpu_has_work; #ifdef CONFIG_TCG diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c index d0a7707991fe..70c8d8170ff3 100644 --- a/target/sh4/cpu.c +++ b/target/sh4/cpu.c @@ -214,8 +214,7 @@ static void superh_cpu_class_init(ObjectClass *oc, void= *data) device_class_set_parent_realize(dc, superh_cpu_realizefn, &scc->parent_realize); =20 - scc->parent_reset =3D cc->reset; - cc->reset =3D superh_cpu_reset; + cpu_class_set_parent_reset(cc, superh_cpu_reset, &scc->parent_reset); =20 cc->class_by_name =3D superh_cpu_class_by_name; cc->has_work =3D superh_cpu_has_work; diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c index bc659295520f..9c306e52717e 100644 --- a/target/sparc/cpu.c +++ b/target/sparc/cpu.c @@ -859,8 +859,7 @@ static void sparc_cpu_class_init(ObjectClass *oc, void = *data) &scc->parent_realize); dc->props =3D sparc_cpu_properties; =20 - scc->parent_reset =3D cc->reset; - cc->reset =3D sparc_cpu_reset; + cpu_class_set_parent_reset(cc, sparc_cpu_reset, &scc->parent_reset); =20 cc->class_by_name =3D sparc_cpu_class_by_name; cc->parse_features =3D sparc_cpu_parse_features; diff --git a/target/tilegx/cpu.c b/target/tilegx/cpu.c index 2b2a7ccc313f..cd422a0467a0 100644 --- a/target/tilegx/cpu.c +++ b/target/tilegx/cpu.c @@ -142,8 +142,7 @@ static void tilegx_cpu_class_init(ObjectClass *oc, void= *data) device_class_set_parent_realize(dc, tilegx_cpu_realizefn, &tcc->parent_realize); =20 - tcc->parent_reset =3D cc->reset; - cc->reset =3D tilegx_cpu_reset; + cpu_class_set_parent_reset(cc, tilegx_cpu_reset, &tcc->parent_reset); =20 cc->class_by_name =3D tilegx_cpu_class_by_name; cc->has_work =3D tilegx_cpu_has_work; diff --git a/target/tricore/cpu.c b/target/tricore/cpu.c index df807c1d7437..85bc9f03a1ee 100644 --- a/target/tricore/cpu.c +++ b/target/tricore/cpu.c @@ -153,8 +153,7 @@ static void tricore_cpu_class_init(ObjectClass *c, void= *data) device_class_set_parent_realize(dc, tricore_cpu_realizefn, &mcc->parent_realize); =20 - mcc->parent_reset =3D cc->reset; - cc->reset =3D tricore_cpu_reset; + cpu_class_set_parent_reset(cc, tricore_cpu_reset, &mcc->parent_reset); cc->class_by_name =3D tricore_cpu_class_by_name; cc->has_work =3D tricore_cpu_has_work; =20 diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c index c65dcf9dd782..4856aee8eca6 100644 --- a/target/xtensa/cpu.c +++ b/target/xtensa/cpu.c @@ -184,8 +184,7 @@ static void xtensa_cpu_class_init(ObjectClass *oc, void= *data) device_class_set_parent_realize(dc, xtensa_cpu_realizefn, &xcc->parent_realize); =20 - xcc->parent_reset =3D cc->reset; - cc->reset =3D xtensa_cpu_reset; + cpu_class_set_parent_reset(cc, xtensa_cpu_reset, &xcc->parent_reset); =20 cc->class_by_name =3D xtensa_cpu_class_by_name; cc->has_work =3D xtensa_cpu_has_work;