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Wed, 4 Dec 2019 17:05:46 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1575479149; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=btr7K23+0gTsOQ/e0CZWco+TYkTxbuqnfzzErRG/fuI=; b=I49tAFJRHj6dgmILn4yD7FGiKEApxQgDwBtOs3qaZq5OwDqoWbesYNRs1/gfE4H61OLe7E DduEoKdxiB92fUdOKcl9QhIC9rdfWKkJY72l+a8z0gDOJpSaLS6WwiaRn1pLtIv+vIAiQg HEI8VCt9yBzo/oR/q0MMKtLPkVeM4Q4= From: Igor Mammedov To: qemu-devel@nongnu.org Subject: [PATCH for-5.0 1/8] q35: implement 128K SMRAM at default SMBASE address Date: Wed, 4 Dec 2019 18:05:40 +0100 Message-Id: <1575479147-6641-2-git-send-email-imammedo@redhat.com> In-Reply-To: <1575479147-6641-1-git-send-email-imammedo@redhat.com> References: <1575479147-6641-1-git-send-email-imammedo@redhat.com> X-Scanned-By: MIMEDefang 2.79 on 10.5.11.15 X-MC-Unique: 4gpTlyl_Nem-h6wDz9mo1w-1 X-Mimecast-Spam-Score: 0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 205.139.110.120 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: pbonzini@redhat.com, philmd@redhat.com, lersek@redhat.com, mst@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Use commit (2f295167e0 q35/mch: implement extended TSEG sizes) for inspiration and (ab)use reserved register in config space at 0x9c offset [*] to extend q35 pci-host with ability to use 128K at 0x30000 as SMRAM and hide it (like TSEG) from non-SMM context. Usage: 1: write 0xff in the register 2: if the feature is supported, follow up read from the register should return 0x01. At this point RAM at 0x30000 is still available for SMI handler configuration from non-SMM context 3: writing 0x02 in the register, locks SMBASE area, making its contents available only from SMM context. In non-SMM context, reads return 0xff and writes are ignored. Further writes into the register are ignored until the system reset. *) https://www.mail-archive.com/qemu-devel@nongnu.org/msg455991.html Signed-off-by: Igor Mammedov --- include/hw/pci-host/q35.h | 10 ++++++ hw/i386/pc.c | 4 ++- hw/pci-host/q35.c | 80 ++++++++++++++++++++++++++++++++++++++++++-= ---- 3 files changed, 86 insertions(+), 8 deletions(-) diff --git a/include/hw/pci-host/q35.h b/include/hw/pci-host/q35.h index b3bcf2e..976fbae 100644 --- a/include/hw/pci-host/q35.h +++ b/include/hw/pci-host/q35.h @@ -32,6 +32,7 @@ #include "hw/acpi/ich9.h" #include "hw/pci-host/pam.h" #include "hw/i386/intel_iommu.h" +#include "qemu/units.h" =20 #define TYPE_Q35_HOST_DEVICE "q35-pcihost" #define Q35_HOST_DEVICE(obj) \ @@ -54,6 +55,8 @@ typedef struct MCHPCIState { MemoryRegion smram_region, open_high_smram; MemoryRegion smram, low_smram, high_smram; MemoryRegion tseg_blackhole, tseg_window; + MemoryRegion smbase_blackhole, smbase_window; + bool has_smram_at_smbase; Range pci_hole; uint64_t below_4g_mem_size; uint64_t above_4g_mem_size; @@ -97,6 +100,13 @@ typedef struct Q35PCIHost { #define MCH_HOST_BRIDGE_EXT_TSEG_MBYTES_QUERY 0xffff #define MCH_HOST_BRIDGE_EXT_TSEG_MBYTES_MAX 0xfff =20 +#define MCH_HOST_BRIDGE_SMBASE_SIZE (128 * KiB) +#define MCH_HOST_BRIDGE_SMBASE_ADDR 0x30000 +#define MCH_HOST_BRIDGE_F_SMBASE 0x9c +#define MCH_HOST_BRIDGE_F_SMBASE_QUERY 0xff +#define MCH_HOST_BRIDGE_F_SMBASE_IN_RAM 0x01 +#define MCH_HOST_BRIDGE_F_SMBASE_LCK 0x02 + #define MCH_HOST_BRIDGE_PCIEXBAR 0x60 /* 64bit register */ #define MCH_HOST_BRIDGE_PCIEXBAR_SIZE 8 /* 64bit register */ #define MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT 0xb0000000 diff --git a/hw/i386/pc.c b/hw/i386/pc.c index ac08e63..9c4b4ac 100644 --- a/hw/i386/pc.c +++ b/hw/i386/pc.c @@ -103,7 +103,9 @@ =20 struct hpet_fw_config hpet_cfg =3D {.count =3D UINT8_MAX}; =20 -GlobalProperty pc_compat_4_1[] =3D {}; +GlobalProperty pc_compat_4_1[] =3D { + { "mch", "smbase-smram", "off" }, +}; const size_t pc_compat_4_1_len =3D G_N_ELEMENTS(pc_compat_4_1); =20 GlobalProperty pc_compat_4_0[] =3D {}; diff --git a/hw/pci-host/q35.c b/hw/pci-host/q35.c index 158d270..c1bd9f7 100644 --- a/hw/pci-host/q35.c +++ b/hw/pci-host/q35.c @@ -275,20 +275,20 @@ static const TypeInfo q35_host_info =3D { * MCH D0:F0 */ =20 -static uint64_t tseg_blackhole_read(void *ptr, hwaddr reg, unsigned size) +static uint64_t blackhole_read(void *ptr, hwaddr reg, unsigned size) { return 0xffffffff; } =20 -static void tseg_blackhole_write(void *opaque, hwaddr addr, uint64_t val, - unsigned width) +static void blackhole_write(void *opaque, hwaddr addr, uint64_t val, + unsigned width) { /* nothing */ } =20 -static const MemoryRegionOps tseg_blackhole_ops =3D { - .read =3D tseg_blackhole_read, - .write =3D tseg_blackhole_write, +static const MemoryRegionOps blackhole_ops =3D { + .read =3D blackhole_read, + .write =3D blackhole_write, .endianness =3D DEVICE_NATIVE_ENDIAN, .valid.min_access_size =3D 1, .valid.max_access_size =3D 4, @@ -430,6 +430,46 @@ static void mch_update_ext_tseg_mbytes(MCHPCIState *mc= h) } } =20 +static void mch_update_smbase_smram(MCHPCIState *mch) +{ + PCIDevice *pd =3D PCI_DEVICE(mch); + uint8_t *reg =3D pd->config + MCH_HOST_BRIDGE_F_SMBASE; + bool lck; + + if (!mch->has_smram_at_smbase) { + return; + } + + if (*reg =3D=3D MCH_HOST_BRIDGE_F_SMBASE_QUERY) { + pd->wmask[MCH_HOST_BRIDGE_F_SMBASE] =3D + MCH_HOST_BRIDGE_F_SMBASE_LCK; + *reg =3D MCH_HOST_BRIDGE_F_SMBASE_IN_RAM; + return; + } + + /* + * default/reset state, discard written value + * which will disable SMRAM balackhole at SMBASE + */ + if (pd->wmask[MCH_HOST_BRIDGE_F_SMBASE] =3D=3D 0xff) { + *reg =3D 0x00; + } + + memory_region_transaction_begin(); + if (*reg & MCH_HOST_BRIDGE_F_SMBASE_LCK) { + /* disable all writes */ + pd->wmask[MCH_HOST_BRIDGE_F_SMBASE] &=3D + ~MCH_HOST_BRIDGE_F_SMBASE_LCK; + *reg =3D MCH_HOST_BRIDGE_F_SMBASE_LCK; + lck =3D true; + } else { + lck =3D false; + } + memory_region_set_enabled(&mch->smbase_blackhole, lck); + memory_region_set_enabled(&mch->smbase_window, lck); + memory_region_transaction_commit(); +} + static void mch_write_config(PCIDevice *d, uint32_t address, uint32_t val, int len) { @@ -456,6 +496,10 @@ static void mch_write_config(PCIDevice *d, MCH_HOST_BRIDGE_EXT_TSEG_MBYTES_SIZE)) { mch_update_ext_tseg_mbytes(mch); } + + if (ranges_overlap(address, len, MCH_HOST_BRIDGE_F_SMBASE, 1)) { + mch_update_smbase_smram(mch); + } } =20 static void mch_update(MCHPCIState *mch) @@ -464,6 +508,7 @@ static void mch_update(MCHPCIState *mch) mch_update_pam(mch); mch_update_smram(mch); mch_update_ext_tseg_mbytes(mch); + mch_update_smbase_smram(mch); =20 /* * pci hole goes from end-of-low-ram to io-apic. @@ -514,6 +559,9 @@ static void mch_reset(DeviceState *qdev) MCH_HOST_BRIDGE_EXT_TSEG_MBYTES_QUERY); } =20 + d->config[MCH_HOST_BRIDGE_F_SMBASE] =3D 0; + d->wmask[MCH_HOST_BRIDGE_F_SMBASE] =3D 0xff; + mch_update(mch); } =20 @@ -563,7 +611,7 @@ static void mch_realize(PCIDevice *d, Error **errp) memory_region_add_subregion(&mch->smram, 0xfeda0000, &mch->high_smram); =20 memory_region_init_io(&mch->tseg_blackhole, OBJECT(mch), - &tseg_blackhole_ops, NULL, + &blackhole_ops, NULL, "tseg-blackhole", 0); memory_region_set_enabled(&mch->tseg_blackhole, false); memory_region_add_subregion_overlap(mch->system_memory, @@ -575,6 +623,23 @@ static void mch_realize(PCIDevice *d, Error **errp) memory_region_set_enabled(&mch->tseg_window, false); memory_region_add_subregion(&mch->smram, mch->below_4g_mem_size, &mch->tseg_window); + + memory_region_init_io(&mch->smbase_blackhole, OBJECT(mch), &blackhole_= ops, + NULL, "smbase-blackhole", + MCH_HOST_BRIDGE_SMBASE_SIZE); + memory_region_set_enabled(&mch->smbase_blackhole, false); + memory_region_add_subregion_overlap(mch->system_memory, + MCH_HOST_BRIDGE_SMBASE_ADDR, + &mch->smbase_blackhole, 1); + + memory_region_init_alias(&mch->smbase_window, OBJECT(mch), + "smbase-window", mch->ram_memory, + MCH_HOST_BRIDGE_SMBASE_ADDR, + MCH_HOST_BRIDGE_SMBASE_SIZE); + memory_region_set_enabled(&mch->smbase_window, false); + memory_region_add_subregion(&mch->smram, MCH_HOST_BRIDGE_SMBASE_ADDR, + &mch->smbase_window); + object_property_add_const_link(qdev_get_machine(), "smram", OBJECT(&mch->smram), &error_abort); =20 @@ -601,6 +666,7 @@ uint64_t mch_mcfg_base(void) static Property mch_props[] =3D { DEFINE_PROP_UINT16("extended-tseg-mbytes", MCHPCIState, ext_tseg_mbyte= s, 16), + DEFINE_PROP_BOOL("smbase-smram", MCHPCIState, has_smram_at_smbase, tru= e), DEFINE_PROP_END_OF_LIST(), }; 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Wed, 4 Dec 2019 17:05:47 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1575479151; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=Fr2KxWaxRXYFyyTmacQjYhempuw1vnJZ79bFGUkw7/w=; b=AM1mjPzasMAv2g2zc4Agdx4FpkDgm9RVTfhwLVsD2y5naKYEebTgOvN34awmbfLwLoye6I 1R+JkLql8iJsrNcNfVzWoY/hIYVZ6Y4Dgm80kBziZZ9bLlQR0Sq761SuxPccaAkjaN2txt nKMHyz5NBue2QPMTZGiGdJckYgs+2jk= From: Igor Mammedov To: qemu-devel@nongnu.org Subject: [PATCH for-5.0 2/8] tests: q35: MCH: add default SMBASE SMRAM lock test Date: Wed, 4 Dec 2019 18:05:41 +0100 Message-Id: <1575479147-6641-3-git-send-email-imammedo@redhat.com> In-Reply-To: <1575479147-6641-1-git-send-email-imammedo@redhat.com> References: <1575479147-6641-1-git-send-email-imammedo@redhat.com> X-Scanned-By: MIMEDefang 2.79 on 10.5.11.15 X-MC-Unique: Sx1WtDh6NoCVgC_zR9ZfUg-1 X-Mimecast-Spam-Score: 0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 205.139.110.61 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: pbonzini@redhat.com, philmd@redhat.com, lersek@redhat.com, mst@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" test lockable SMRAM at default SMBASE feature, introduced by patch "q35: implement 128K SMRAM at default SMBASE address" Signed-off-by: Igor Mammedov --- tests/q35-test.c | 105 +++++++++++++++++++++++++++++++++++++++++++++++++++= ++++ 1 file changed, 105 insertions(+) diff --git a/tests/q35-test.c b/tests/q35-test.c index a68183d..dd02660 100644 --- a/tests/q35-test.c +++ b/tests/q35-test.c @@ -186,6 +186,109 @@ static void test_tseg_size(const void *data) qtest_quit(qts); } =20 +#define SMBASE 0x30000 +#define SMRAM_TEST_PATTERN 0x32 +#define SMRAM_TEST_RESET_PATTERN 0x23 + +static void test_smram_smbase_lock(void) +{ + QPCIBus *pcibus; + QPCIDevice *pcidev; + QDict *response; + QTestState *qts; + int i; + + qts =3D qtest_init("-M q35"); + + pcibus =3D qpci_new_pc(qts, NULL); + g_assert(pcibus !=3D NULL); + + pcidev =3D qpci_device_find(pcibus, 0); + g_assert(pcidev !=3D NULL); + + /* check that SMRAM is not enabled by default */ + g_assert(qpci_config_readb(pcidev, MCH_HOST_BRIDGE_F_SMBASE) =3D=3D 0); + qtest_writeb(qts, SMBASE, SMRAM_TEST_PATTERN); + g_assert_cmpint(qtest_readb(qts, SMBASE), =3D=3D, SMRAM_TEST_PATTERN); + + /* check that writinng junk to 0x9c before before negotiating is ignor= red */ + for (i =3D 0; i < 0xff; i++) { + qpci_config_writeb(pcidev, MCH_HOST_BRIDGE_F_SMBASE, i); + g_assert(qpci_config_readb(pcidev, MCH_HOST_BRIDGE_F_SMBASE) =3D= =3D 0); + } + + /* enable SMRAM at SMBASE */ + qpci_config_writeb(pcidev, MCH_HOST_BRIDGE_F_SMBASE, 0xff); + g_assert(qpci_config_readb(pcidev, MCH_HOST_BRIDGE_F_SMBASE) =3D=3D 0x= 01); + /* lock SMRAM at SMBASE */ + qpci_config_writeb(pcidev, MCH_HOST_BRIDGE_F_SMBASE, 0x02); + g_assert(qpci_config_readb(pcidev, MCH_HOST_BRIDGE_F_SMBASE) =3D=3D 0x= 02); + + /* check that SMRAM at SMBASE is locked and can't be unlocked */ + g_assert_cmpint(qtest_readb(qts, SMBASE), =3D=3D, 0xff); + for (i =3D 0; i <=3D 0xff; i++) { + /* make sure register is immutable */ + qpci_config_writeb(pcidev, MCH_HOST_BRIDGE_F_SMBASE, i); + g_assert(qpci_config_readb(pcidev, MCH_HOST_BRIDGE_F_SMBASE) =3D= =3D 0x02); + + /* RAM access should go inot black hole */ + qtest_writeb(qts, SMBASE, SMRAM_TEST_PATTERN); + g_assert_cmpint(qtest_readb(qts, SMBASE), =3D=3D, 0xff); + } + + /* reset */ + response =3D qtest_qmp(qts, "{'execute': 'system_reset', 'arguments': = {} }"); + g_assert(response); + g_assert(!qdict_haskey(response, "error")); + qobject_unref(response); + + /* check RAM at SMBASE is available after reset */ + g_assert_cmpint(qtest_readb(qts, SMBASE), =3D=3D, SMRAM_TEST_PATTERN); + g_assert(qpci_config_readb(pcidev, MCH_HOST_BRIDGE_F_SMBASE) =3D=3D 0); + qtest_writeb(qts, SMBASE, SMRAM_TEST_RESET_PATTERN); + g_assert_cmpint(qtest_readb(qts, SMBASE), =3D=3D, SMRAM_TEST_RESET_PAT= TERN); + + g_free(pcidev); + qpci_free_pc(pcibus); + + qtest_quit(qts); +} + +static void test_without_smram_base(void) +{ + QPCIBus *pcibus; + QPCIDevice *pcidev; + QTestState *qts; + int i; + + qts =3D qtest_init("-M pc-q35-4.1"); + + pcibus =3D qpci_new_pc(qts, NULL); + g_assert(pcibus !=3D NULL); + + pcidev =3D qpci_device_find(pcibus, 0); + g_assert(pcidev !=3D NULL); + + /* check that RAM accessible */ + qtest_writeb(qts, SMBASE, SMRAM_TEST_PATTERN); + g_assert_cmpint(qtest_readb(qts, SMBASE), =3D=3D, SMRAM_TEST_PATTERN); + + /* check that writing to 0x9c succeeds */ + for (i =3D 0; i <=3D 0xff; i++) { + qpci_config_writeb(pcidev, MCH_HOST_BRIDGE_F_SMBASE, i); + g_assert(qpci_config_readb(pcidev, MCH_HOST_BRIDGE_F_SMBASE) =3D= =3D i); + } + + /* check that RAM is still accessible */ + qtest_writeb(qts, SMBASE, SMRAM_TEST_PATTERN + 1); + g_assert_cmpint(qtest_readb(qts, SMBASE), =3D=3D, (SMRAM_TEST_PATTERN = + 1)); + + g_free(pcidev); + qpci_free_pc(pcibus); + + qtest_quit(qts); +} + int main(int argc, char **argv) { g_test_init(&argc, &argv, NULL); @@ -197,5 +300,7 @@ int main(int argc, char **argv) qtest_add_data_func("/q35/tseg-size/8mb", &tseg_8mb, test_tseg_size); qtest_add_data_func("/q35/tseg-size/ext/16mb", &tseg_ext_16mb, test_tseg_size); + qtest_add_func("/q35/smram/smbase_lock", test_smram_smbase_lock); + qtest_add_func("/q35/smram/legacy_smbase", test_without_smram_base); return g_test_run(); } --=20 2.7.4 From nobody Mon May 20 02:17:49 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1575481019; cv=none; d=zohomail.com; s=zohoarc; b=FbBYUwmddk1D8ltP5lsghYv9D1qEQTe2Mk8AlCj+KSgRM007FF2FiiiEgDxG9hHBrIRO5FXgRf2Z0raeR7mc9nnZiNOGNr6TnUgXOZUIL0L2D32A+w+REcXhDCoI3l4XnmpDDAlEEHb5Aa48ZGcQRDrqVKg9plDctuGMdUj1Cnk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1575481019; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To; 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Wed, 4 Dec 2019 17:05:49 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1575479154; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=mc1RI1X6a9TI2HtaGuOb+i8lvqAVJiC3NOsuJudvhDI=; b=NYY4mCcJEaagKXwV3xMCCxoC96kCqQOX0C+GS7QmBkd0ZK2NXOnLe9fo25WH+sbgRKZF7+ znZC5Ht6xVFupG1n2JFiEzXB1SbVekj5tc7Xj0mwiOWP8iHBupYIO0YntyZQ98YbQR/IbP vYB9vi/fSjYtoBT0eH/K6aFOcM/ibfw= From: Igor Mammedov To: qemu-devel@nongnu.org Subject: [PATCH for-5.0 3/8] acpi: cpuhp: spec: clarify 'CPU selector' register usage and endianness Date: Wed, 4 Dec 2019 18:05:42 +0100 Message-Id: <1575479147-6641-4-git-send-email-imammedo@redhat.com> In-Reply-To: <1575479147-6641-1-git-send-email-imammedo@redhat.com> References: <1575479147-6641-1-git-send-email-imammedo@redhat.com> X-Scanned-By: MIMEDefang 2.79 on 10.5.11.15 X-MC-Unique: KBjbhOBNNSOoZlMNalx3Lg-1 X-Mimecast-Spam-Score: 0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 207.211.31.81 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: pbonzini@redhat.com, philmd@redhat.com, lersek@redhat.com, mst@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" * Move reserved registers to the top of the section, so reader would be aware of effects when reading registers description. * State registers endianness explicitly at the beginning of the section * Describe registers behavior in case of 'CPU selector' register contains value that doesn't point to a possible CPU. Signed-off-by: Igor Mammedov Reviewed-by: Laszlo Ersek --- docs/specs/acpi_cpu_hotplug.txt | 18 ++++++++++++------ 1 file changed, 12 insertions(+), 6 deletions(-) diff --git a/docs/specs/acpi_cpu_hotplug.txt b/docs/specs/acpi_cpu_hotplug.= txt index ee219c8..4e65286 100644 --- a/docs/specs/acpi_cpu_hotplug.txt +++ b/docs/specs/acpi_cpu_hotplug.txt @@ -30,6 +30,18 @@ Register block base address: Register block size: ACPI_CPU_HOTPLUG_REG_LEN =3D 12 =20 +All accesses to registers described below, imply little-endian byte order. + +Reserved resisters behavior: + - write accesses are ignored + - read accesses return all bits set to 0. + +The last stored value in 'CPU selector' must refer to a possible CPU, othe= rwise + - reads from any register return 0 + - writes to any other register are ignored until valid value is stored i= nto it +On QEMU start, 'CPU selector' is initialized to a valid value, on reset it +keeps the current value. + read access: offset: [0x0-0x3] reserved @@ -86,9 +98,3 @@ write access: ACPI_DEVICE_OST QMP event from QEMU to external applicati= ons with current values of OST event and status registers. other values: reserved - -Selecting CPU device beyond possible range has no effect on platform: - - write accesses to CPU hot-plug registers not documented above are - ignored - - read accesses to CPU hot-plug registers not documented above return - all bits set to 0. --=20 2.7.4 From nobody Mon May 20 02:17:49 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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Wed, 04 Dec 2019 12:05:55 -0500 Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-319-lmhufn2RMsCU4oBblq3VQA-1; Wed, 04 Dec 2019 12:05:53 -0500 Received: from smtp.corp.redhat.com (int-mx05.intmail.prod.int.phx2.redhat.com [10.5.11.15]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id 296562F62 for ; Wed, 4 Dec 2019 17:05:52 +0000 (UTC) Received: from dell-r430-03.lab.eng.brq.redhat.com (dell-r430-03.lab.eng.brq.redhat.com [10.37.153.18]) by smtp.corp.redhat.com (Postfix) with ESMTP id 0031F5D6BB; Wed, 4 Dec 2019 17:05:50 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1575479154; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=AmtJFfkmZoVSC0j56rxKfGHOSvgzvHCtD4Ssg0Urk/g=; b=fKcYg3cHMhudhbvPhxkwgF+23vkF3rjkW2S3aAlNIp5a1HC0rZvG3NcILP1CSAcnQN5ucJ ZpktRbzH2+NKrOBr0EVHIKTknBvdvdr8vZIKWF6YCaO0kTTtqzPNPyf5Id1ULU4azp+q26 dhBtbNdipELJoncyPOFQ6lQgOG1uVZY= From: Igor Mammedov To: qemu-devel@nongnu.org Subject: [PATCH for-5.0 4/8] acpi: cpuhp: spec: fix 'Command data' description Date: Wed, 4 Dec 2019 18:05:43 +0100 Message-Id: <1575479147-6641-5-git-send-email-imammedo@redhat.com> In-Reply-To: <1575479147-6641-1-git-send-email-imammedo@redhat.com> References: <1575479147-6641-1-git-send-email-imammedo@redhat.com> X-Scanned-By: MIMEDefang 2.79 on 10.5.11.15 X-MC-Unique: lmhufn2RMsCU4oBblq3VQA-1 X-Mimecast-Spam-Score: 0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 207.211.31.81 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: pbonzini@redhat.com, philmd@redhat.com, lersek@redhat.com, mst@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Correct returned value description in case 'Command field' =3D=3D 0x0, it's in not PXM but CPU selector value with pending event In addition describe 0 blanket value in case of not supported 'Command field' value. Signed-off-by: Igor Mammedov Reviewed-by: Laszlo Ersek --- docs/specs/acpi_cpu_hotplug.txt | 11 +++++------ 1 file changed, 5 insertions(+), 6 deletions(-) diff --git a/docs/specs/acpi_cpu_hotplug.txt b/docs/specs/acpi_cpu_hotplug.= txt index 4e65286..19c508f 100644 --- a/docs/specs/acpi_cpu_hotplug.txt +++ b/docs/specs/acpi_cpu_hotplug.txt @@ -56,9 +56,8 @@ read access: 3-7: reserved and should be ignored by OSPM [0x5-0x7] reserved [0x8] Command data: (DWORD access) - in case of error or unsupported command reads is 0xFFFFFFFF - current 'Command field' value: - 0: returns PXM value corresponding to device + contains 0 unless last stored in 'Command field' value is one of: + 0: contains 'CPU selector' value of a CPU with pending event= [s] =20 write access: offset: @@ -81,9 +80,9 @@ write access: value: 0: selects a CPU device with inserting/removing events and following reads from 'Command data' register return - selected CPU (CPU selector value). If no CPU with events - found, the current CPU selector doesn't change and - corresponding insert/remove event flags are not set. + selected CPU ('CPU selector' value). + If no CPU with events found, the current 'CPU selector' doe= sn't + change and corresponding insert/remove event flags are not = set. 1: following writes to 'Command data' register set OST event register in QEMU 2: following writes to 'Command data' register set OST status --=20 2.7.4 From nobody Mon May 20 02:17:49 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=redhat.com ARC-Seal: i=1; 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Wed, 04 Dec 2019 12:05:54 -0500 Received: from smtp.corp.redhat.com (int-mx05.intmail.prod.int.phx2.redhat.com [10.5.11.15]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id 98A468005BD for ; Wed, 4 Dec 2019 17:05:53 +0000 (UTC) Received: from dell-r430-03.lab.eng.brq.redhat.com (dell-r430-03.lab.eng.brq.redhat.com [10.37.153.18]) by smtp.corp.redhat.com (Postfix) with ESMTP id 70EA05D6BB; Wed, 4 Dec 2019 17:05:52 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1575479156; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=bXbQwjDHyNCMl8rJIrMoSPCd56xgDRpG9pGaUNNzZ30=; b=AThr9AdX/5QB4u9Gju0d0hng8Ln9ODGQuPWEAaAJZZ2iNo3N5dDZH9Rcsdgtd73L1aB+Hi wejno4nMREkOcjZcUMJTGq5h74qLWEbwUL7j0QOnuTUuPNcS5mJEDqMBk1qqJCktX3evbj 4uEQTfzQ+poXdXmI9zw/MCA11qxW41k= From: Igor Mammedov To: qemu-devel@nongnu.org Subject: [PATCH for-5.0 5/8] acpi: cpuhp: spec: clarify store into 'Command data' when 'Command field' == 0 Date: Wed, 4 Dec 2019 18:05:44 +0100 Message-Id: <1575479147-6641-6-git-send-email-imammedo@redhat.com> In-Reply-To: <1575479147-6641-1-git-send-email-imammedo@redhat.com> References: <1575479147-6641-1-git-send-email-imammedo@redhat.com> X-Scanned-By: MIMEDefang 2.79 on 10.5.11.15 X-MC-Unique: BfhPu8IyMkSxhURd1efckw-1 X-Mimecast-Spam-Score: 0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 205.139.110.61 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: pbonzini@redhat.com, philmd@redhat.com, lersek@redhat.com, mst@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Write section of 'Command data' register should describe what happens when it's written into. Correct description in case the last stored 'Command field' value equals to 0, to reflect that currently it's not supported. Signed-off-by: Igor Mammedov Reviewed-by: Laszlo Ersek --- docs/specs/acpi_cpu_hotplug.txt | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/docs/specs/acpi_cpu_hotplug.txt b/docs/specs/acpi_cpu_hotplug.= txt index 19c508f..f3c552d 100644 --- a/docs/specs/acpi_cpu_hotplug.txt +++ b/docs/specs/acpi_cpu_hotplug.txt @@ -90,8 +90,7 @@ write access: other values: reserved [0x6-0x7] reserved [0x8] Command data: (DWORD access) - current 'Command field' value: - 0: OSPM reads value of CPU selector + if last stored 'Command field' value: 1: stores value into OST event register 2: stores value into OST status register, triggers ACPI_DEVICE_OST QMP event from QEMU to external applicati= ons --=20 2.7.4 From nobody Mon May 20 02:17:49 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; 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Wed, 04 Dec 2019 12:05:58 -0500 Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-147-JFkVjHXSN--ThxFbu4Kv-g-1; Wed, 04 Dec 2019 12:05:56 -0500 Received: from smtp.corp.redhat.com (int-mx05.intmail.prod.int.phx2.redhat.com [10.5.11.15]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id 183CF1005512 for ; Wed, 4 Dec 2019 17:05:55 +0000 (UTC) Received: from dell-r430-03.lab.eng.brq.redhat.com (dell-r430-03.lab.eng.brq.redhat.com [10.37.153.18]) by smtp.corp.redhat.com (Postfix) with ESMTP id E14B35D6BB; Wed, 4 Dec 2019 17:05:53 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1575479157; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=2YgmH04qOhqZ1gIRxsoKF0FXDgFaY1TPFDkxlQAG7NI=; b=dP0PhhVVKf9+iesnUAIvXCFJfKc4IAPiWPXkY2zELEoAGJzc9DPhBp8B/NuJA46B5/+oU+ gzrnGU+M6oNrJ7NgsUSeucLRvmLwfQsVpLTS4j3A9zf0exBmr3QvP5AyPkwM5INlALQwsm Gx/E84AXbnryZiVYNcLr4mdaa82K80Y= From: Igor Mammedov To: qemu-devel@nongnu.org Subject: [PATCH for-5.0 6/8] acpi: cpuhp: spec: add typical usecases Date: Wed, 4 Dec 2019 18:05:45 +0100 Message-Id: <1575479147-6641-7-git-send-email-imammedo@redhat.com> In-Reply-To: <1575479147-6641-1-git-send-email-imammedo@redhat.com> References: <1575479147-6641-1-git-send-email-imammedo@redhat.com> X-Scanned-By: MIMEDefang 2.79 on 10.5.11.15 X-MC-Unique: JFkVjHXSN--ThxFbu4Kv-g-1 X-Mimecast-Spam-Score: 0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 207.211.31.120 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: pbonzini@redhat.com, philmd@redhat.com, lersek@redhat.com, mst@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Document work-flows for * finding a CPU with pending 'insert/remove' event * enumerating present and possible CPUs Signed-off-by: Igor Mammedov Reviewed-by: Laszlo Ersek --- docs/specs/acpi_cpu_hotplug.txt | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/docs/specs/acpi_cpu_hotplug.txt b/docs/specs/acpi_cpu_hotplug.= txt index f3c552d..58c16c6 100644 --- a/docs/specs/acpi_cpu_hotplug.txt +++ b/docs/specs/acpi_cpu_hotplug.txt @@ -64,6 +64,7 @@ write access: [0x0-0x3] CPU selector: (DWORD access) selects active CPU device. All following accesses to other registers will read/store data from/to selected CPU. + Valid values: [0 .. max_cpus) [0x4] CPU device control fields: (1 byte access) bits: 0: reserved, OSPM must clear it before writing to register. @@ -96,3 +97,31 @@ write access: ACPI_DEVICE_OST QMP event from QEMU to external applicati= ons with current values of OST event and status registers. other values: reserved + + Typical usecases: + - Get a cpu with pending event + 1. Store 0x0 to the 'CPU selector' register. + 2. Store 0x0 to the 'Command field' register. + 3. Read the 'CPU device status fields' register. + 4. If both bit#1 and bit#2 are clear in the value read, there is= no CPU + with a pending event and selected CPU remains unchanged. + 5. Otherwise, read the 'Command data' register. The value read i= s the + selector of the CPU with the pending event (which is already + selected). + + - Enumerate CPUs present/non present CPUs + 01. Set the present CPU count to 0. + 02. Set the iterator to 0. + 03. Store 0x0 to the 'CPU selector' register, to ensure that it'= s in + a valid state and that access to other registers won't be ig= nored. + 04. Store 0x0 to the 'Command field' register to make 'Command d= ata' + register return 'CPU selector' value of selected CPU + 05. Read the 'CPU device status fields' register. + 06. If bit#0 is set, increment the present CPU count. + 07. Increment the iterator. + 08. Store the iterator to the 'CPU selector' register. + 09. Read the 'Command data' register. + 10. If the value read is not zero, goto 05. + 11. Otherwise store 0x0 to the 'CPU selector' register, to put it + into a valid state and exit. + The iterator at this point equals "max_cpus". --=20 2.7.4 From nobody Mon May 20 02:17:49 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1575479362; cv=none; d=zohomail.com; s=zohoarc; b=ivF+dvnFnxOUtma23Y9bQqe67LDS6eAI5Gabm4y1xUVmzM53/9xkbdcdGnC2KM3C1AJ4djx+Hvw3E1qijqgXYpDhT54bpmJy0JhnxSixbDwxB1MyCRk9ay7AP3FJnQvmZbt4p0yIKkQ2CQdby9ctsxG5D4YdUHYiiLZhDijp3DM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; 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Wed, 4 Dec 2019 17:05:56 +0000 (UTC) Received: from dell-r430-03.lab.eng.brq.redhat.com (dell-r430-03.lab.eng.brq.redhat.com [10.37.153.18]) by smtp.corp.redhat.com (Postfix) with ESMTP id 60EB25D6BB; Wed, 4 Dec 2019 17:05:55 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1575479162; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=hpMeJfL69t01dB4rXZUwcJ1cv+AEgkBhVyd3WRXvwJU=; b=Id6dyCzjq9JyubOKC0s5mg2nE3zsx2BDwkUXEgNN04BCuUJfjHgcspD+1/BZO6lpJ9t+kA bcctx15kjdcchkkGrH3aHEiiqbvVQHGTM2cL3wWLLpupbz4dbI346icNLHqz7YTY1Qp02N IrJM+DovloHm0T21BHDrlShrZiZSJtQ= From: Igor Mammedov To: qemu-devel@nongnu.org Subject: [PATCH for-5.0 7/8] acpi: cpuhp: add CPHP_GET_CPU_ID_CMD command Date: Wed, 4 Dec 2019 18:05:46 +0100 Message-Id: <1575479147-6641-8-git-send-email-imammedo@redhat.com> In-Reply-To: <1575479147-6641-1-git-send-email-imammedo@redhat.com> References: <1575479147-6641-1-git-send-email-imammedo@redhat.com> X-Scanned-By: MIMEDefang 2.79 on 10.5.11.15 X-MC-Unique: sBpHFzriMd-tDBZyFVDzRQ-1 X-Mimecast-Spam-Score: 0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 205.139.110.61 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: pbonzini@redhat.com, philmd@redhat.com, lersek@redhat.com, mst@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Extend CPU hotplug interface to return architecture specific identifier for current CPU in 2 registers: - lower 32 bits existing ACPI_CPU_CMD_DATA_OFFSET_RW - upper 32 bits in new ACPI_CPU_CMD_DATA2_OFFSET_R at offset 0. Target user is UEFI firmware, which needs a way to enumerate all CPUs (including possible CPUs) to allocate and initialize CPU structures on boot. (for x86: it needs APIC ID and later command will be used to retrieve ARM's MPIDR which serves the similar to APIC ID purpose) The new ACPI_CPU_CMD_DATA2_OFFSET_R register will also be used to detect presence of modern CPU hotplug, which will be described in follow up patch. Signed-off-by: Igor Mammedov --- v1: - s/ACPI_CPU_CMD_DATA2_OFFSET_RW/ACPI_CPU_CMD_DATA2_OFFSET_R/. --- docs/specs/acpi_cpu_hotplug.txt | 10 ++++++++-- hw/acpi/cpu.c | 15 +++++++++++++++ hw/acpi/trace-events | 1 + 3 files changed, 24 insertions(+), 2 deletions(-) diff --git a/docs/specs/acpi_cpu_hotplug.txt b/docs/specs/acpi_cpu_hotplug.= txt index 58c16c6..bb33144 100644 --- a/docs/specs/acpi_cpu_hotplug.txt +++ b/docs/specs/acpi_cpu_hotplug.txt @@ -44,7 +44,11 @@ keeps the current value. =20 read access: offset: - [0x0-0x3] reserved + [0x0-0x3] Command data 2: (DWORD access) + if last stored 'Command field' value: + 3: upper 32 bits of architecture specific identifying CP= U value + (n x86 case: 0x0) + other values: reserved [0x4] CPU device status fields: (1 byte access) bits: 0: Device is enabled and may be used by guest @@ -96,7 +100,9 @@ write access: 2: stores value into OST status register, triggers ACPI_DEVICE_OST QMP event from QEMU to external applicati= ons with current values of OST event and status registers. - other values: reserved + 3: lower 32 bit of architecture specific identifier + (in x86 case: APIC ID) + other values: reserved =20 Typical usecases: - Get a cpu with pending event diff --git a/hw/acpi/cpu.c b/hw/acpi/cpu.c index 87f30a3..87813ce 100644 --- a/hw/acpi/cpu.c +++ b/hw/acpi/cpu.c @@ -12,11 +12,13 @@ #define ACPI_CPU_FLAGS_OFFSET_RW 4 #define ACPI_CPU_CMD_OFFSET_WR 5 #define ACPI_CPU_CMD_DATA_OFFSET_RW 8 +#define ACPI_CPU_CMD_DATA2_OFFSET_R 0 =20 enum { CPHP_GET_NEXT_CPU_WITH_EVENT_CMD =3D 0, CPHP_OST_EVENT_CMD =3D 1, CPHP_OST_STATUS_CMD =3D 2, + CPHP_GET_CPU_ID_CMD =3D 3, CPHP_CMD_MAX }; =20 @@ -74,11 +76,24 @@ static uint64_t cpu_hotplug_rd(void *opaque, hwaddr add= r, unsigned size) case CPHP_GET_NEXT_CPU_WITH_EVENT_CMD: val =3D cpu_st->selector; break; + case CPHP_GET_CPU_ID_CMD: + val =3D cdev->arch_id & 0xFFFFFFFF; + break; default: break; } trace_cpuhp_acpi_read_cmd_data(cpu_st->selector, val); break; + case ACPI_CPU_CMD_DATA2_OFFSET_R: + switch (cpu_st->command) { + case CPHP_GET_CPU_ID_CMD: + val =3D cdev->arch_id >> 32; + break; + default: + break; + } + trace_cpuhp_acpi_read_cmd_data2(cpu_st->selector, val); + break; default: break; } diff --git a/hw/acpi/trace-events b/hw/acpi/trace-events index 96b8273..afbc77d 100644 --- a/hw/acpi/trace-events +++ b/hw/acpi/trace-events @@ -23,6 +23,7 @@ cpuhp_acpi_read_flags(uint32_t idx, uint8_t flags) "idx[0= x%"PRIx32"] flags: 0x%" cpuhp_acpi_write_idx(uint32_t idx) "set active cpu idx: 0x%"PRIx32 cpuhp_acpi_write_cmd(uint32_t idx, uint8_t cmd) "idx[0x%"PRIx32"] cmd: 0x%= "PRIx8 cpuhp_acpi_read_cmd_data(uint32_t idx, uint32_t data) "idx[0x%"PRIx32"] da= ta: 0x%"PRIx32 +cpuhp_acpi_read_cmd_data2(uint32_t idx, uint32_t data) "idx[0x%"PRIx32"] d= ata: 0x%"PRIx32 cpuhp_acpi_cpu_has_events(uint32_t idx, bool ins, bool rm) "idx[0x%"PRIx32= "] inserting: %d, removing: %d" cpuhp_acpi_clear_inserting_evt(uint32_t idx) "idx[0x%"PRIx32"]" cpuhp_acpi_clear_remove_evt(uint32_t idx) "idx[0x%"PRIx32"]" --=20 2.7.4 From nobody Mon May 20 02:17:49 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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Wed, 04 Dec 2019 12:06:08 -0500 Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-278-0Rwf_ThgOKmzxVGdVfLX0A-1; Wed, 04 Dec 2019 12:05:58 -0500 Received: from smtp.corp.redhat.com (int-mx05.intmail.prod.int.phx2.redhat.com [10.5.11.15]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id 0625C1083E8F for ; Wed, 4 Dec 2019 17:05:58 +0000 (UTC) Received: from dell-r430-03.lab.eng.brq.redhat.com (dell-r430-03.lab.eng.brq.redhat.com [10.37.153.18]) by smtp.corp.redhat.com (Postfix) with ESMTP id D207F5D6BB; Wed, 4 Dec 2019 17:05:56 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1575479167; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=TqJTzapMD48SAnuXvSZ6ni4aF2WLRnsexaD2qQGsFgo=; b=g6aFAtesY2pBQrtrvwU3x2QOn9nxIdCY1yC2KdiusEcmdmoYCIj3l4ceLbSXXfP/XDgTBT 6rr7Zuqyff8Irh8z5mBk9atajSzptp0kjx+zVZhXqHD0Bi5LvaQm5OWjPC7w59Gud9onWo CZb2RsFSXTPZoUv8G/KnVi51YIV2cfA= From: Igor Mammedov To: qemu-devel@nongnu.org Subject: [PATCH for-5.0 8/8] acpi: cpuhp: spec: document procedure for enabling modern CPU hotplug Date: Wed, 4 Dec 2019 18:05:47 +0100 Message-Id: <1575479147-6641-9-git-send-email-imammedo@redhat.com> In-Reply-To: <1575479147-6641-1-git-send-email-imammedo@redhat.com> References: <1575479147-6641-1-git-send-email-imammedo@redhat.com> X-Scanned-By: MIMEDefang 2.79 on 10.5.11.15 X-MC-Unique: 0Rwf_ThgOKmzxVGdVfLX0A-1 X-Mimecast-Spam-Score: 0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 205.139.110.120 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: pbonzini@redhat.com, philmd@redhat.com, lersek@redhat.com, mst@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Describe how to enable and detect modern CPU hotplug interface. Detection part is based on new CPHP_GET_CPU_ID_CMD command, introduced by "acpi: cpuhp: add CPHP_GET_CPU_ID_CMD command" patch. Signed-off-by: Igor Mammedov --- docs/specs/acpi_cpu_hotplug.txt | 22 ++++++++++++++++++++-- 1 file changed, 20 insertions(+), 2 deletions(-) diff --git a/docs/specs/acpi_cpu_hotplug.txt b/docs/specs/acpi_cpu_hotplug.= txt index bb33144..667b264 100644 --- a/docs/specs/acpi_cpu_hotplug.txt +++ b/docs/specs/acpi_cpu_hotplug.txt @@ -15,14 +15,14 @@ CPU present bitmap for: PIIX-PM (IO port 0xaf00-0xaf1f, 1-byte access) One bit per CPU. Bit position reflects corresponding CPU APIC ID. Read-o= nly. The first DWORD in bitmap is used in write mode to switch from legacy - to new CPU hotplug interface, write 0 into it to do switch. + to modern CPU hotplug interface, write 0 into it to do switch. --------------------------------------------------------------- QEMU sets corresponding CPU bit on hot-add event and issues SCI with GPE.2 event set. CPU present map is read by ACPI BIOS GPE.2 handler to notify OS about CPU hot-add events. CPU hot-remove isn't supported. =20 =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D -ACPI CPU hotplug interface registers: +Modern ACPI CPU hotplug interface registers: ------------------------------------- Register block base address: ICH9-LPC IO port 0x0cd8 @@ -105,6 +105,24 @@ write access: other values: reserved =20 Typical usecases: + - (x86) Detecting and enabling modern CPU hotplug interface. + QEMU starts with legacy CPU hotplug interface enabled. Detecting= and + switching to modern interface is based on the 2 legacy CPU hotpl= ug features: + 1. Writes into CPU bitmap are ignored. + 2. CPU bitmap always has bit#0 set, corresponding to boot CPU. + + Use following steps to detect and enable modern CPU hotplug inte= rface: + 1. Store 0x0 to the 'CPU selector' register, + attempting to switch to modern mode + 2. Store 0x0 to the 'CPU selector' register, + to ensure valid selector value + 3. Store 0x3 to the 'Command field' register, + sets the 'Command data 2' register into architecture specif= ic + CPU identifier mode + 4. Read the 'Command data 2' register. + If read value is 0x0, the modern interface is enabled. + Otherwise legacy or no CPU hotplug interface available + - Get a cpu with pending event 1. Store 0x0 to the 'CPU selector' register. 2. Store 0x0 to the 'Command field' register. --=20 2.7.4