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Wed, 4 Dec 2019 14:56:22 +0100 Received: (from sveith@localhost) by sveith-desktop.aka.corp.amazon.com (8.15.2/8.15.2/Submit) id xB4DuMcV029395; Wed, 4 Dec 2019 14:56:22 +0100 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amazon.de; i=@amazon.de; q=dns/txt; s=amazon201209; t=1575467786; x=1607003786; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=903Oin9iiuc+khCz3xboU318uHpQzskDGrltjVjcCSM=; b=FfLvHL4rlHS3OTiics/U3hMmZjFuBmt6+Mx/jDoVpOWeE04uCSpgsZvU 4TqaJ0Uu0kt19Z0o2DVqQqvFn8tYIiEDySqUi/HUckopc0cInm3/OF9ds 4dvnk4WFnk2nyJ0Y2lkf3I3b8OyHhdnwWAaUAysi1P+ryZK936629hjUt Q=; IronPort-SDR: 14zrM5qDK+M1wIRKinaJl1On6utbiyQqfM9hpWiDqLLMvFtDYSLempEbZ898yszACoWOIFSjRH onZAOInhjG7w== X-IronPort-AV: E=Sophos;i="5.69,277,1571702400"; d="scan'208";a="7621894" From: Simon Veith To: qemu-devel@nongnu.org, qemu-arm@nongnu.org Cc: Simon Veith , Eric Auger Subject: [PATCH 3/5] hw/arm/smmuv3: Align stream table base address to table size Date: Wed, 4 Dec 2019 14:55:46 +0100 Message-Id: <1575467748-28898-4-git-send-email-sveith@amazon.de> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1575467748-28898-1-git-send-email-sveith@amazon.de> References: <1575467748-28898-1-git-send-email-sveith@amazon.de> Precedence: Bulk X-detected-operating-system: by eggs.gnu.org: FreeBSD 9.x [fuzzy] X-Received-From: 52.95.48.154 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @amazon.de) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Per the specification, and as observed in hardware, the SMMUv3 aligns the SMMU_STRTAB_BASE address to the size of the table by masking out the respective least significant bits in the ADDR field. Apply this masking logic to our smmu_find_ste() lookup function per the specification. ref. ARM IHI 0070C, section 6.3.23. Signed-off-by: Simon Veith Cc: Eric Auger Cc: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org --- hw/arm/smmuv3.c | 29 +++++++++++++++++++++++++---- 1 file changed, 25 insertions(+), 4 deletions(-) diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c index aad4639..2d6c275 100644 --- a/hw/arm/smmuv3.c +++ b/hw/arm/smmuv3.c @@ -376,8 +376,9 @@ bad_ste: static int smmu_find_ste(SMMUv3State *s, uint32_t sid, STE *ste, SMMUEventInfo *event) { - dma_addr_t addr; + dma_addr_t addr, strtab_base; uint32_t log2size; + int strtab_size_shift; int ret; =20 trace_smmuv3_find_ste(sid, s->features, s->sid_split); @@ -391,10 +392,23 @@ static int smmu_find_ste(SMMUv3State *s, uint32_t sid= , STE *ste, } if (s->features & SMMU_FEATURE_2LVL_STE) { int l1_ste_offset, l2_ste_offset, max_l2_ste, span; - dma_addr_t strtab_base, l1ptr, l2ptr; + dma_addr_t l1ptr, l2ptr; STEDesc l1std; =20 - strtab_base =3D s->strtab_base & SMMU_BASE_ADDR_MASK; + /* + * Align strtab base address to table size. For this purpose, assu= me it + * is not bounded by SMMU_IDR1_SIDSIZE. + */ + strtab_size_shift =3D log2size - s->sid_split - 1 + 3; + if (strtab_size_shift < DMA_ADDR_BITS) { + if (strtab_size_shift < 5) { + strtab_size_shift =3D 5; + } + strtab_base =3D s->strtab_base & SMMU_BASE_ADDR_MASK & + ~((1ULL << strtab_size_shift) - 1); + } else { + strtab_base =3D 0; + } l1_ste_offset =3D sid >> s->sid_split; l2_ste_offset =3D sid & ((1 << s->sid_split) - 1); l1ptr =3D (dma_addr_t)(strtab_base + l1_ste_offset * sizeof(l1std)= ); @@ -433,7 +447,14 @@ static int smmu_find_ste(SMMUv3State *s, uint32_t sid,= STE *ste, } addr =3D l2ptr + l2_ste_offset * sizeof(*ste); } else { - addr =3D (s->strtab_base & SMMU_BASE_ADDR_MASK) + sid * sizeof(*st= e); + strtab_size_shift =3D log2size + 5; + if (strtab_size_shift < DMA_ADDR_BITS) { + strtab_base =3D s->strtab_base & SMMU_BASE_ADDR_MASK & + ~((1ULL << strtab_size_shift) - 1); + } else { + strtab_base =3D 0; + } + addr =3D strtab_base + sid * sizeof(*ste); } =20 if (smmu_get_ste(s, addr, ste, event)) { --=20 2.7.4