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[147.11.224.80]) by smtp.gmail.com with ESMTPSA id r10sm12968577pgn.68.2019.11.16.07.08.54 (version=TLS1 cipher=AES128-SHA bits=128/128); Sat, 16 Nov 2019 07:08:55 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:subject:date:message-id; bh=5YsOfTa1cfXjS3bx9/f+FRPYPJZ5Mz1/XjfoAdU9Gaw=; b=WrUuZOsZIJpSAj4KH6vcCCeKJF0hgi9FjhNH3kRLTQsAf680Hoyo6kPCiCINukVy/5 fkUfiK5Wx44ph1rFnaeOAU0pdrlLL71SYmBCG3ciRNAZ9QsdhQVoPRLUtennt2vSlBtc Ci+1mx9vP/dPW0sburarfSqBaEbJ2/P2DA6hCAVCNBpBhLyF7SxEEMjqN6VXu1Nb3pW9 qwWXbhRf6O6+3G2dErk11Kr7mdUpUwb/90d4ID4TN2BzyQJoUwZQKGELojSYxZ4FKAtk 4JkJJmMIKSdJfcSGrKNvEX3JyDeZRVw6vWFFNn4NCZhLMiFjaihGK4Blzm1Vn2o4fYiM jriw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id; bh=5YsOfTa1cfXjS3bx9/f+FRPYPJZ5Mz1/XjfoAdU9Gaw=; b=N73twSDl3KOfCxo02KvnX9aOZRebbznOvkJOuZF8VXadOQ4/SgJxpJ5mBCBaxkpjVe brvjOzRtYYIcCYJli4prsV9oQcrUGXx/6IQ4Tb8YVN47IvFggzwo7SSvP2RKfQqBxyZQ o0UdRLzwUpXt+/vRLwTqlVeggf9rmyXdtxwoAA7VeFhki9TFt6i9nIKqJeEEW8Qrds0a f/EqjJ0tUbDOKHZmcAcG99DSVoeMBpBpeywDvp/ypUM/Hf709I5Pg4+0Bq9DMWIJsgPJ 7133T1qj8tl8Z6fi+wl1JrxWTeIqy0fOn0uvEhekISyY7Bfp2LsEwK9YEiHXeegXr9K5 pI6A== X-Gm-Message-State: APjAAAUSYMDYcIEvYVzE3lRN52Co31lCehoIOhgdAI3lBUcWrWzGs8VB WgEmyfSKZaaZ5tuWfYnAmnc= X-Google-Smtp-Source: APXvYqwndQR7n+Jw7DU5rc+tt5/OtxMXnIogW9BvCRNQVXE+4/PeTv9aN/m+6BNy3vxzA/6v+tsUUA== X-Received: by 2002:a63:9d41:: with SMTP id i62mr23324215pgd.310.1573916935725; Sat, 16 Nov 2019 07:08:55 -0800 (PST) From: Bin Meng To: Alistair Francis , Bastian Koppelmann , Palmer Dabbelt , Sagar Karandikar , qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH] riscv: sifive_u: Add a "serial" property for board serial number Date: Sat, 16 Nov 2019 07:08:50 -0800 Message-Id: <1573916930-19068-1-git-send-email-bmeng.cn@gmail.com> X-Mailer: git-send-email 1.7.1 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::443 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @gmail.com) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" At present the board serial number is hard-coded to 1, and passed to OTP model during initialization. Firmware (FSBL, U-Boot) uses the serial number to generate a unique MAC address for the on-chip ethernet controller. When multiple QEMU 'sifive_u' instances are created and connected to the same subnet, they all have the same MAC address hence it creates a unusable network. A new "serial" property is introduced to specify the board serial number. When not given, the default serial number 1 is used. Signed-off-by: Bin Meng Reviewed-by: Alistair Francis Reviewed-by: Palmer Dabbelt --- hw/riscv/sifive_u.c | 21 ++++++++++++++++++++- include/hw/riscv/sifive_u.h | 1 + 2 files changed, 21 insertions(+), 1 deletion(-) diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index 9552abf..e1a5536 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -34,6 +34,7 @@ #include "qemu/log.h" #include "qemu/error-report.h" #include "qapi/error.h" +#include "qapi/visitor.h" #include "hw/boards.h" #include "hw/loader.h" #include "hw/sysbus.h" @@ -401,6 +402,7 @@ static void riscv_sifive_u_init(MachineState *machine) static void riscv_sifive_u_soc_init(Object *obj) { MachineState *ms =3D MACHINE(qdev_get_machine()); + SiFiveUState *us =3D RISCV_U_MACHINE(ms); SiFiveUSoCState *s =3D RISCV_U_SOC(obj); =20 object_initialize_child(obj, "e-cluster", &s->e_cluster, @@ -433,7 +435,7 @@ static void riscv_sifive_u_soc_init(Object *obj) TYPE_SIFIVE_U_PRCI); sysbus_init_child_obj(obj, "otp", &s->otp, sizeof(s->otp), TYPE_SIFIVE_U_OTP); - qdev_prop_set_uint32(DEVICE(&s->otp), "serial", OTP_SERIAL); + qdev_prop_set_uint32(DEVICE(&s->otp), "serial", us->serial); sysbus_init_child_obj(obj, "gem", &s->gem, sizeof(s->gem), TYPE_CADENCE_GEM); } @@ -452,6 +454,18 @@ static void sifive_u_set_start_in_flash(Object *obj, b= ool value, Error **errp) s->start_in_flash =3D value; } =20 +static void sifive_u_get_serial(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + visit_type_uint32(v, name, (uint32_t *)opaque, errp); +} + +static void sifive_u_set_serial(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + visit_type_uint32(v, name, (uint32_t *)opaque, errp); +} + static void riscv_sifive_u_machine_instance_init(Object *obj) { SiFiveUState *s =3D RISCV_U_MACHINE(obj); @@ -463,6 +477,11 @@ static void riscv_sifive_u_machine_instance_init(Objec= t *obj) "Set on to tell QEMU's ROM to jump to = " \ "flash. Otherwise QEMU will jump to DR= AM", NULL); + + s->serial =3D OTP_SERIAL; + object_property_add(obj, "serial", "uint32", sifive_u_get_serial, + sifive_u_set_serial, NULL, &s->serial, NULL); + object_property_set_description(obj, "serial", "Board serial number", = NULL); } =20 static void riscv_sifive_u_soc_realize(DeviceState *dev, Error **errp) diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h index 82667b5..7cf742e 100644 --- a/include/hw/riscv/sifive_u.h +++ b/include/hw/riscv/sifive_u.h @@ -59,6 +59,7 @@ typedef struct SiFiveUState { int fdt_size; =20 bool start_in_flash; + uint32_t serial; } SiFiveUState; =20 enum { --=20 2.7.4