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X-Received-From: 2a00:1450:4864:20::436 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Move it out of pc.c since it is strictly tied to TCG. This is almost exclusively code movement, the next patch will implement IGNNE. Signed-off-by: Paolo Bonzini --- hw/i386/pc.c | 17 +++-------------- hw/i386/pc_piix.c | 4 +++- hw/i386/pc_q35.c | 4 +++- include/hw/i386/pc.h | 1 - target/i386/cpu.h | 3 ++- target/i386/fpu_helper.c | 26 +++++++++++++++++++++++++- 6 files changed, 36 insertions(+), 19 deletions(-) diff --git a/hw/i386/pc.c b/hw/i386/pc.c index 5fce60c..66d865b 100644 --- a/hw/i386/pc.c +++ b/hw/i386/pc.c @@ -381,23 +381,12 @@ static uint64_t ioport80_read(void *opaque, hwaddr ad= dr, unsigned size) } =20 /* MSDOS compatibility mode FPU exception support */ -static qemu_irq ferr_irq; - -void pc_register_ferr_irq(qemu_irq irq) -{ - ferr_irq =3D irq; -} - -/* XXX: add IGNNE support */ -void cpu_set_ferr(CPUX86State *s) -{ - qemu_irq_raise(ferr_irq); -} - static void ioportF0_write(void *opaque, hwaddr addr, uint64_t data, unsigned size) { - qemu_irq_lower(ferr_irq); + if (tcg_enabled()) { + cpu_clear_ferr(); + } } =20 static uint64_t ioportF0_read(void *opaque, hwaddr addr, unsigned size) diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c index 3a4a64a..c15929a 100644 --- a/hw/i386/pc_piix.c +++ b/hw/i386/pc_piix.c @@ -213,7 +213,9 @@ static void pc_init1(MachineState *machine, ioapic_init_gsi(gsi_state, "i440fx"); } =20 - pc_register_ferr_irq(x86ms->gsi[13]); + if (tcg_enabled()) { + x86_register_ferr_irq(x86ms->gsi[13]); + } =20 pc_vga_init(isa_bus, pcmc->pci_enabled ? pci_bus : NULL); =20 diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c index def3bc2..b9c3e18 100644 --- a/hw/i386/pc_q35.c +++ b/hw/i386/pc_q35.c @@ -261,7 +261,9 @@ static void pc_q35_init(MachineState *machine) ioapic_init_gsi(gsi_state, "q35"); } =20 - pc_register_ferr_irq(x86ms->gsi[13]); + if (tcg_enabled()) { + x86_register_ferr_irq(x86ms->gsi[13]); + } =20 assert(pcms->vmport !=3D ON_OFF_AUTO__MAX); if (pcms->vmport =3D=3D ON_OFF_AUTO_AUTO) { diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h index 5923318..f040a72 100644 --- a/include/hw/i386/pc.h +++ b/include/hw/i386/pc.h @@ -176,7 +176,6 @@ void vmmouse_set_data(const uint32_t *data); extern int fd_bootchk; =20 bool pc_machine_is_smm_enabled(PCMachineState *pcms); -void pc_register_ferr_irq(qemu_irq irq); void pc_acpi_smi_interrupt(void *opaque, int irq, int level); =20 void pc_hot_add_cpu(MachineState *ms, const int64_t id, Error **errp); diff --git a/target/i386/cpu.h b/target/i386/cpu.h index b772e82..01e052b 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -1761,7 +1761,8 @@ int cpu_x86_support_mca_broadcast(CPUX86State *env); =20 int cpu_get_pic_interrupt(CPUX86State *s); /* MSDOS compatibility mode FPU exception support */ -void cpu_set_ferr(CPUX86State *s); +void x86_register_ferr_irq(qemu_irq irq); +void cpu_clear_ferr(void); /* mpx_helper.c */ void cpu_sync_bndcs_hflags(CPUX86State *env); =20 diff --git a/target/i386/fpu_helper.c b/target/i386/fpu_helper.c index 005f1f6..4db0059 100644 --- a/target/i386/fpu_helper.c +++ b/target/i386/fpu_helper.c @@ -26,6 +26,10 @@ #include "exec/cpu_ldst.h" #include "fpu/softfloat.h" =20 +#ifdef CONFIG_SOFTMMU +#include "hw/irq.h" +#endif + #define FPU_RC_MASK 0xc00 #define FPU_RC_NEAR 0x000 #define FPU_RC_DOWN 0x400 @@ -58,6 +62,26 @@ #define floatx80_l2e make_floatx80(0x3fff, 0xb8aa3b295c17f0bcLL) #define floatx80_l2t make_floatx80(0x4000, 0xd49a784bcd1b8afeLL) =20 +#if !defined(CONFIG_USER_ONLY) +static qemu_irq ferr_irq; + +void x86_register_ferr_irq(qemu_irq irq) +{ + ferr_irq =3D irq; +} + +void cpu_clear_ferr(void) +{ + qemu_irq_lower(ferr_irq); +} + +static void cpu_set_ferr(void) +{ + qemu_irq_raise(ferr_irq); +} +#endif + + static inline void fpush(CPUX86State *env) { env->fpstt =3D (env->fpstt - 1) & 7; @@ -137,7 +161,7 @@ static void fpu_raise_exception(CPUX86State *env, uintp= tr_t retaddr) } #if !defined(CONFIG_USER_ONLY) else { - cpu_set_ferr(env); + cpu_set_ferr(); } #endif } --=20 1.8.3.1