From nobody Wed Nov 12 18:11:31 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1572023225; cv=none; d=zoho.com; s=zohoarc; b=C4PCEqioJ8NSysinw8u7xjV3+34mEeXS9dPi0HUW+U09iGTY9v3ny8skQ9x2UBcidOFF0ZKvoSq0DxUFs4C0XM89pAwW2TOQNkfzSvry7FK64gcn/HyEjuEAsIgZyjG8ifKR7okVXF78jSVeZthBtvDDqiLWoLGhAHL+i6YjXQA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1572023225; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To; bh=bEsPKDdpLpAg5hi1SwgRFrswcNW189AUv4r+dPzB668=; b=J0tdgdFuW5LdRby1E+VZWWNZ1HGF6pWFm1wqpumemyXp+T0FjJJjNk00OMx8YI4Bkoxm5yjTsNiIFLwA6NbS4cHtRtm8qSdNTv7TRl0fL+o4qS8Pfjrm6QISWJ1VSbwPt/n2ca3gSGANc3lAk4x9E3FzR6ejz6bqRRERxtwFQbE= ARC-Authentication-Results: i=1; mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 15720232256441016.8512578579163; Fri, 25 Oct 2019 10:07:05 -0700 (PDT) Received: from localhost ([::1]:34756 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iO33H-0007h3-8p for importer@patchew.org; Fri, 25 Oct 2019 13:07:04 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:40562) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iO2ib-0004w6-En for qemu-devel@nongnu.org; Fri, 25 Oct 2019 12:45:46 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iO2iW-0002ES-HF for qemu-devel@nongnu.org; Fri, 25 Oct 2019 12:45:41 -0400 Received: from mx2.rt-rk.com ([89.216.37.149]:34448 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1iO2iW-0002DO-6K for qemu-devel@nongnu.org; Fri, 25 Oct 2019 12:45:36 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id B76C31A221C; Fri, 25 Oct 2019 18:44:29 +0200 (CEST) Received: from rtrkw774-lin.domain.local (rtrkw774-lin.domain.local [10.10.14.106]) by mail.rt-rk.com (Postfix) with ESMTPSA id 890411A2232; Fri, 25 Oct 2019 18:44:29 +0200 (CEST) X-Virus-Scanned: amavisd-new at rt-rk.com From: Aleksandar Markovic To: qemu-devel@nongnu.org Subject: [PULL 08/20] target/mips: msa: Split helpers for HADD_. Date: Fri, 25 Oct 2019 18:44:10 +0200 Message-Id: <1572021862-28273-9-git-send-email-aleksandar.markovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1572021862-28273-1-git-send-email-aleksandar.markovic@rt-rk.com> References: <1572021862-28273-1-git-send-email-aleksandar.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 89.216.37.149 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, amarkovic@wavecomp.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Aleksandar Markovic Achieves clearer code and slightly better performance. Reviewed-by: Aleksandar Rikalo Signed-off-by: Aleksandar Markovic Message-Id: <1571826227-10583-9-git-send-email-aleksandar.markovic@rt-rk.co= m> --- target/mips/helper.h | 10 +++- target/mips/msa_helper.c | 131 ++++++++++++++++++++++++++++++++++++++-----= ---- target/mips/translate.c | 32 +++++++++--- 3 files changed, 141 insertions(+), 32 deletions(-) diff --git a/target/mips/helper.h b/target/mips/helper.h index ce01e97..f25ba90 100644 --- a/target/mips/helper.h +++ b/target/mips/helper.h @@ -847,6 +847,14 @@ DEF_HELPER_4(msa_addv_h, void, env, i32, i32, i32) DEF_HELPER_4(msa_addv_w, void, env, i32, i32, i32) DEF_HELPER_4(msa_addv_d, void, env, i32, i32, i32) =20 +DEF_HELPER_4(msa_hadd_s_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_hadd_s_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_hadd_s_d, void, env, i32, i32, i32) + +DEF_HELPER_4(msa_hadd_u_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_hadd_u_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_hadd_u_d, void, env, i32, i32, i32) + DEF_HELPER_4(msa_ave_s_b, void, env, i32, i32, i32) DEF_HELPER_4(msa_ave_s_h, void, env, i32, i32, i32) DEF_HELPER_4(msa_ave_s_w, void, env, i32, i32, i32) @@ -1024,8 +1032,6 @@ DEF_HELPER_5(msa_pckod_df, void, env, i32, i32, i32, = i32) DEF_HELPER_5(msa_vshf_df, void, env, i32, i32, i32, i32) DEF_HELPER_5(msa_srar_df, void, env, i32, i32, i32, i32) DEF_HELPER_5(msa_srlr_df, void, env, i32, i32, i32, i32) -DEF_HELPER_5(msa_hadd_s_df, void, env, i32, i32, i32, i32) -DEF_HELPER_5(msa_hadd_u_df, void, env, i32, i32, i32, i32) DEF_HELPER_5(msa_hsub_s_df, void, env, i32, i32, i32, i32) DEF_HELPER_5(msa_hsub_u_df, void, env, i32, i32, i32, i32) =20 diff --git a/target/mips/msa_helper.c b/target/mips/msa_helper.c index c31f46c..f5d3737 100644 --- a/target/mips/msa_helper.c +++ b/target/mips/msa_helper.c @@ -1184,6 +1184,113 @@ void helper_msa_addv_d(CPUMIPSState *env, } =20 =20 +#define SIGNED_EVEN(a, df) \ + ((((int64_t)(a)) << (64 - DF_BITS(df) / 2)) >> (64 - DF_BITS(df) /= 2)) + +#define UNSIGNED_EVEN(a, df) \ + ((((uint64_t)(a)) << (64 - DF_BITS(df) / 2)) >> (64 - DF_BITS(df) = / 2)) + +#define SIGNED_ODD(a, df) \ + ((((int64_t)(a)) << (64 - DF_BITS(df))) >> (64 - DF_BITS(df) / 2)) + +#define UNSIGNED_ODD(a, df) \ + ((((uint64_t)(a)) << (64 - DF_BITS(df))) >> (64 - DF_BITS(df) / 2)) + + +static inline int64_t msa_hadd_s_df(uint32_t df, int64_t arg1, int64_t arg= 2) +{ + return SIGNED_ODD(arg1, df) + SIGNED_EVEN(arg2, df); +} + +void helper_msa_hadd_s_h(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); + + pwd->h[0] =3D msa_hadd_s_df(DF_HALF, pws->h[0], pwt->h[0]); + pwd->h[1] =3D msa_hadd_s_df(DF_HALF, pws->h[1], pwt->h[1]); + pwd->h[2] =3D msa_hadd_s_df(DF_HALF, pws->h[2], pwt->h[2]); + pwd->h[3] =3D msa_hadd_s_df(DF_HALF, pws->h[3], pwt->h[3]); + pwd->h[4] =3D msa_hadd_s_df(DF_HALF, pws->h[4], pwt->h[4]); + pwd->h[5] =3D msa_hadd_s_df(DF_HALF, pws->h[5], pwt->h[5]); + pwd->h[6] =3D msa_hadd_s_df(DF_HALF, pws->h[6], pwt->h[6]); + pwd->h[7] =3D msa_hadd_s_df(DF_HALF, pws->h[7], pwt->h[7]); +} + +void helper_msa_hadd_s_w(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); + + pwd->w[0] =3D msa_hadd_s_df(DF_WORD, pws->w[0], pwt->w[0]); + pwd->w[1] =3D msa_hadd_s_df(DF_WORD, pws->w[1], pwt->w[1]); + pwd->w[2] =3D msa_hadd_s_df(DF_WORD, pws->w[2], pwt->w[2]); + pwd->w[3] =3D msa_hadd_s_df(DF_WORD, pws->w[3], pwt->w[3]); +} + +void helper_msa_hadd_s_d(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); + + pwd->d[0] =3D msa_hadd_s_df(DF_DOUBLE, pws->d[0], pwt->d[0]); + pwd->d[1] =3D msa_hadd_s_df(DF_DOUBLE, pws->d[1], pwt->d[1]); +} + + +static inline int64_t msa_hadd_u_df(uint32_t df, int64_t arg1, int64_t arg= 2) +{ + return UNSIGNED_ODD(arg1, df) + UNSIGNED_EVEN(arg2, df); +} + +void helper_msa_hadd_u_h(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); + + pwd->h[0] =3D msa_hadd_u_df(DF_HALF, pws->h[0], pwt->h[0]); + pwd->h[1] =3D msa_hadd_u_df(DF_HALF, pws->h[1], pwt->h[1]); + pwd->h[2] =3D msa_hadd_u_df(DF_HALF, pws->h[2], pwt->h[2]); + pwd->h[3] =3D msa_hadd_u_df(DF_HALF, pws->h[3], pwt->h[3]); + pwd->h[4] =3D msa_hadd_u_df(DF_HALF, pws->h[4], pwt->h[4]); + pwd->h[5] =3D msa_hadd_u_df(DF_HALF, pws->h[5], pwt->h[5]); + pwd->h[6] =3D msa_hadd_u_df(DF_HALF, pws->h[6], pwt->h[6]); + pwd->h[7] =3D msa_hadd_u_df(DF_HALF, pws->h[7], pwt->h[7]); +} + +void helper_msa_hadd_u_w(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); + + pwd->w[0] =3D msa_hadd_u_df(DF_WORD, pws->w[0], pwt->w[0]); + pwd->w[1] =3D msa_hadd_u_df(DF_WORD, pws->w[1], pwt->w[1]); + pwd->w[2] =3D msa_hadd_u_df(DF_WORD, pws->w[2], pwt->w[2]); + pwd->w[3] =3D msa_hadd_u_df(DF_WORD, pws->w[3], pwt->w[3]); +} + +void helper_msa_hadd_u_d(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); + + pwd->d[0] =3D msa_hadd_u_df(DF_DOUBLE, pws->d[0], pwt->d[0]); + pwd->d[1] =3D msa_hadd_u_df(DF_DOUBLE, pws->d[1], pwt->d[1]); +} + + /* * Int Average * ----------- @@ -3727,18 +3834,6 @@ static inline int64_t msa_mulv_df(uint32_t df, int64= _t arg1, int64_t arg2) return arg1 * arg2; } =20 -#define SIGNED_EVEN(a, df) \ - ((((int64_t)(a)) << (64 - DF_BITS(df) / 2)) >> (64 - DF_BITS(df) /= 2)) - -#define UNSIGNED_EVEN(a, df) \ - ((((uint64_t)(a)) << (64 - DF_BITS(df) / 2)) >> (64 - DF_BITS(df) = / 2)) - -#define SIGNED_ODD(a, df) \ - ((((int64_t)(a)) << (64 - DF_BITS(df))) >> (64 - DF_BITS(df) / 2)) - -#define UNSIGNED_ODD(a, df) \ - ((((uint64_t)(a)) << (64 - DF_BITS(df))) >> (64 - DF_BITS(df) / 2)) - #define SIGNED_EXTRACT(e, o, a, df) \ do { \ e =3D SIGNED_EVEN(a, df); \ @@ -3815,16 +3910,6 @@ static inline void msa_sld_df(uint32_t df, wr_t *pwd, } } =20 -static inline int64_t msa_hadd_s_df(uint32_t df, int64_t arg1, int64_t arg= 2) -{ - return SIGNED_ODD(arg1, df) + SIGNED_EVEN(arg2, df); -} - -static inline int64_t msa_hadd_u_df(uint32_t df, int64_t arg1, int64_t arg= 2) -{ - return UNSIGNED_ODD(arg1, df) + UNSIGNED_EVEN(arg2, df); -} - static inline int64_t msa_hsub_s_df(uint32_t df, int64_t arg1, int64_t arg= 2) { return SIGNED_ODD(arg1, df) - SIGNED_EVEN(arg2, df); @@ -3925,8 +4010,6 @@ MSA_BINOP_DF(dotp_s) MSA_BINOP_DF(dotp_u) MSA_BINOP_DF(srar) MSA_BINOP_DF(srlr) -MSA_BINOP_DF(hadd_s) -MSA_BINOP_DF(hadd_u) MSA_BINOP_DF(hsub_s) MSA_BINOP_DF(hsub_u) =20 diff --git a/target/mips/translate.c b/target/mips/translate.c index 14f9891..9e8e973 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -28990,6 +28990,32 @@ static void gen_msa_3r(CPUMIPSState *env, DisasCon= text *ctx) break; } switch (MASK_MSA_3R(ctx->opcode)) { + case OPC_HADD_S_df: + switch (df) { + case DF_HALF: + gen_helper_msa_hadd_s_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_hadd_s_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_hadd_s_d(cpu_env, twd, tws, twt); + break; + } + break; + case OPC_HADD_U_df: + switch (df) { + case DF_HALF: + gen_helper_msa_hadd_u_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_hadd_u_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_hadd_u_d(cpu_env, twd, tws, twt); + break; + } + break; case OPC_DOTP_S_df: gen_helper_msa_dotp_s_df(cpu_env, tdf, twd, tws, twt); break; @@ -29005,15 +29031,9 @@ static void gen_msa_3r(CPUMIPSState *env, DisasCon= text *ctx) case OPC_DPSUB_S_df: gen_helper_msa_dpsub_s_df(cpu_env, tdf, twd, tws, twt); break; - case OPC_HADD_S_df: - gen_helper_msa_hadd_s_df(cpu_env, tdf, twd, tws, twt); - break; case OPC_DPSUB_U_df: gen_helper_msa_dpsub_u_df(cpu_env, tdf, twd, tws, twt); break; - case OPC_HADD_U_df: - gen_helper_msa_hadd_u_df(cpu_env, tdf, twd, tws, twt); - break; case OPC_HSUB_S_df: gen_helper_msa_hsub_s_df(cpu_env, tdf, twd, tws, twt); break; --=20 2.7.4