From nobody Wed Nov 12 18:09:33 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1572022695; cv=none; d=zoho.com; s=zohoarc; b=gfLcdp1sZHuNL6rpqXWMRItv7yZms5tunDRFhRYyiR0QcwLn4O66j3ZC2j7fyLDOlMypdZVeqLJNpJMxcMabRMMVxaCZaX2LXRLv0enDRzLE/IaY8TQpGtF8RYWKJuAn3woDZrJJWuWR8tcmuEAEcy3lIDm46o2g4QPUtF+vQ4g= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1572022695; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To; bh=3QSVOgX44WTcorBsUZDE2lAq5wkw/RnFRa8wcwN702g=; b=VCGWWsuNPoNpr2z5r472Wn0dSf/6r/jDvTBS5N39uaSbC0Wll3goc4uZYENPblwxWxwhvYSPJHo2NKFyvZXmIk9Ms67DHAEkV+HLMWysUoiPZUUXru4QXoWA/836SbZ9RDu44FyQlCxycCcpf1MhZowt/i5L0xkcJ12Luu3p/Kw= ARC-Authentication-Results: i=1; mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1572022695669646.7898502686643; Fri, 25 Oct 2019 09:58:15 -0700 (PDT) Received: from localhost ([::1]:34690 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iO2uj-0000Fv-PR for importer@patchew.org; Fri, 25 Oct 2019 12:58:13 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:40527) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iO2iZ-0004rc-LM for qemu-devel@nongnu.org; Fri, 25 Oct 2019 12:45:44 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iO2iV-0002DC-4v for qemu-devel@nongnu.org; Fri, 25 Oct 2019 12:45:39 -0400 Received: from mx2.rt-rk.com ([89.216.37.149]:60633 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1iO2iU-0001XX-PR for qemu-devel@nongnu.org; Fri, 25 Oct 2019 12:45:35 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id 6691D1A2276; Fri, 25 Oct 2019 18:44:29 +0200 (CEST) Received: from rtrkw774-lin.domain.local (rtrkw774-lin.domain.local [10.10.14.106]) by mail.rt-rk.com (Postfix) with ESMTPSA id 3BD241A21D5; Fri, 25 Oct 2019 18:44:29 +0200 (CEST) X-Virus-Scanned: amavisd-new at rt-rk.com From: Aleksandar Markovic To: qemu-devel@nongnu.org Subject: [PULL 01/20] target/mips: Clean up helper.c Date: Fri, 25 Oct 2019 18:44:03 +0200 Message-Id: <1572021862-28273-2-git-send-email-aleksandar.markovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1572021862-28273-1-git-send-email-aleksandar.markovic@rt-rk.com> References: <1572021862-28273-1-git-send-email-aleksandar.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 89.216.37.149 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, amarkovic@wavecomp.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Aleksandar Markovic Mostly fix errors and warnings reported by 'checkpatch.pl -f'. Cc: Markus Armbruster Reviewed-by: Aleksandar Rikalo Signed-off-by: Aleksandar Markovic Message-Id: <1571826227-10583-2-git-send-email-aleksandar.markovic@rt-rk.co= m> --- target/mips/helper.c | 123 +++++++++++++++++++++++++++++++----------------= ---- 1 file changed, 74 insertions(+), 49 deletions(-) diff --git a/target/mips/helper.c b/target/mips/helper.c index a2b6459..781930a 100644 --- a/target/mips/helper.c +++ b/target/mips/helper.c @@ -39,8 +39,8 @@ enum { #if !defined(CONFIG_USER_ONLY) =20 /* no MMU emulation */ -int no_mmu_map_address (CPUMIPSState *env, hwaddr *physical, int *prot, - target_ulong address, int rw, int access_type) +int no_mmu_map_address(CPUMIPSState *env, hwaddr *physical, int *prot, + target_ulong address, int rw, int access_type) { *physical =3D address; *prot =3D PAGE_READ | PAGE_WRITE | PAGE_EXEC; @@ -48,26 +48,28 @@ int no_mmu_map_address (CPUMIPSState *env, hwaddr *phys= ical, int *prot, } =20 /* fixed mapping MMU emulation */ -int fixed_mmu_map_address (CPUMIPSState *env, hwaddr *physical, int *prot, - target_ulong address, int rw, int access_type) +int fixed_mmu_map_address(CPUMIPSState *env, hwaddr *physical, int *prot, + target_ulong address, int rw, int access_type) { if (address <=3D (int32_t)0x7FFFFFFFUL) { - if (!(env->CP0_Status & (1 << CP0St_ERL))) + if (!(env->CP0_Status & (1 << CP0St_ERL))) { *physical =3D address + 0x40000000UL; - else + } else { *physical =3D address; - } else if (address <=3D (int32_t)0xBFFFFFFFUL) + } + } else if (address <=3D (int32_t)0xBFFFFFFFUL) { *physical =3D address & 0x1FFFFFFF; - else + } else { *physical =3D address; + } =20 *prot =3D PAGE_READ | PAGE_WRITE | PAGE_EXEC; return TLBRET_MATCH; } =20 /* MIPS32/MIPS64 R4000-style MMU emulation */ -int r4k_map_address (CPUMIPSState *env, hwaddr *physical, int *prot, - target_ulong address, int rw, int access_type) +int r4k_map_address(CPUMIPSState *env, hwaddr *physical, int *prot, + target_ulong address, int rw, int access_type) { uint16_t ASID =3D env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask; int i; @@ -99,8 +101,9 @@ int r4k_map_address (CPUMIPSState *env, hwaddr *physical= , int *prot, if (rw !=3D MMU_DATA_STORE || (n ? tlb->D1 : tlb->D0)) { *physical =3D tlb->PFN[n] | (address & (mask >> 1)); *prot =3D PAGE_READ; - if (n ? tlb->D1 : tlb->D0) + if (n ? tlb->D1 : tlb->D0) { *prot |=3D PAGE_WRITE; + } if (!(n ? tlb->XI1 : tlb->XI0)) { *prot |=3D PAGE_EXEC; } @@ -130,7 +133,7 @@ static int is_seg_am_mapped(unsigned int am, bool eu, i= nt mmu_idx) int32_t adetlb_mask; =20 switch (mmu_idx) { - case 3 /* ERL */: + case 3: /* ERL */ /* If EU is set, always unmapped */ if (eu) { return 0; @@ -204,7 +207,7 @@ static int get_segctl_physical_address(CPUMIPSState *en= v, hwaddr *physical, pa & ~(hwaddr)segmask); } =20 -static int get_physical_address (CPUMIPSState *env, hwaddr *physical, +static int get_physical_address(CPUMIPSState *env, hwaddr *physical, int *prot, target_ulong real_address, int rw, int access_type, int mmu_idx) { @@ -252,14 +255,15 @@ static int get_physical_address (CPUMIPSState *env, h= waddr *physical, } else { segctl =3D env->CP0_SegCtl2 >> 16; } - ret =3D get_segctl_physical_address(env, physical, prot, real_addr= ess, rw, - access_type, mmu_idx, segctl, - 0x3FFFFFFF); + ret =3D get_segctl_physical_address(env, physical, prot, + real_address, rw, access_type, + mmu_idx, segctl, 0x3FFFFFFF); #if defined(TARGET_MIPS64) } else if (address < 0x4000000000000000ULL) { /* xuseg */ if (UX && address <=3D (0x3FFFFFFFFFFFFFFFULL & env->SEGMask)) { - ret =3D env->tlb->map_address(env, physical, prot, real_addres= s, rw, access_type); + ret =3D env->tlb->map_address(env, physical, prot, + real_address, rw, access_type); } else { ret =3D TLBRET_BADADDR; } @@ -267,7 +271,8 @@ static int get_physical_address (CPUMIPSState *env, hwa= ddr *physical, /* xsseg */ if ((supervisor_mode || kernel_mode) && SX && address <=3D (0x7FFFFFFFFFFFFFFFULL & env->SEGMask)) { - ret =3D env->tlb->map_address(env, physical, prot, real_addres= s, rw, access_type); + ret =3D env->tlb->map_address(env, physical, prot, + real_address, rw, access_type); } else { ret =3D TLBRET_BADADDR; } @@ -307,7 +312,8 @@ static int get_physical_address (CPUMIPSState *env, hwa= ddr *physical, /* xkseg */ if (kernel_mode && KX && address <=3D (0xFFFFFFFF7FFFFFFFULL & env->SEGMask)) { - ret =3D env->tlb->map_address(env, physical, prot, real_addres= s, rw, access_type); + ret =3D env->tlb->map_address(env, physical, prot, + real_address, rw, access_type); } else { ret =3D TLBRET_BADADDR; } @@ -328,8 +334,10 @@ static int get_physical_address (CPUMIPSState *env, hw= addr *physical, access_type, mmu_idx, env->CP0_SegCtl0 >> 16, 0x1FFFFF= FF); } else { - /* kseg3 */ - /* XXX: debug segment is not emulated */ + /* + * kseg3 + * XXX: debug segment is not emulated + */ ret =3D get_segctl_physical_address(env, physical, prot, real_addr= ess, rw, access_type, mmu_idx, env->CP0_SegCtl0, 0x1FFFFFFF); @@ -515,9 +523,9 @@ static void raise_mmu_exception(CPUMIPSState *env, targ= et_ulong address, #if defined(TARGET_MIPS64) env->CP0_EntryHi &=3D env->SEGMask; env->CP0_XContext =3D - /* PTEBase */ (env->CP0_XContext & ((~0ULL) << (env->SEGBITS - 7= ))) | - /* R */ (extract64(address, 62, 2) << (env->SEGBITS - 9)) | - /* BadVPN2 */ (extract64(address, 13, env->SEGBITS - 13) << 4); + (env->CP0_XContext & ((~0ULL) << (env->SEGBITS - 7))) | /* PTEBase= */ + (extract64(address, 62, 2) << (env->SEGBITS - 9)) | /* R = */ + (extract64(address, 13, env->SEGBITS - 13) << 4); /* BadVPN2= */ #endif cs->exception_index =3D exception; env->error_code =3D error_code; @@ -945,7 +953,8 @@ bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, int= size, } =20 #ifndef CONFIG_USER_ONLY -hwaddr cpu_mips_translate_address(CPUMIPSState *env, target_ulong address,= int rw) +hwaddr cpu_mips_translate_address(CPUMIPSState *env, target_ulong address, + int rw) { hwaddr physical; int prot; @@ -1005,7 +1014,7 @@ static const char * const excp_names[EXCP_LAST + 1] = =3D { }; #endif =20 -target_ulong exception_resume_pc (CPUMIPSState *env) +target_ulong exception_resume_pc(CPUMIPSState *env) { target_ulong bad_pc; target_ulong isa_mode; @@ -1013,8 +1022,10 @@ target_ulong exception_resume_pc (CPUMIPSState *env) isa_mode =3D !!(env->hflags & MIPS_HFLAG_M16); bad_pc =3D env->active_tc.PC | isa_mode; if (env->hflags & MIPS_HFLAG_BMASK) { - /* If the exception was raised from a delay slot, come back to - the jump. */ + /* + * If the exception was raised from a delay slot, come back to + * the jump. + */ bad_pc -=3D (env->hflags & MIPS_HFLAG_B16 ? 2 : 4); } =20 @@ -1022,14 +1033,14 @@ target_ulong exception_resume_pc (CPUMIPSState *env) } =20 #if !defined(CONFIG_USER_ONLY) -static void set_hflags_for_handler (CPUMIPSState *env) +static void set_hflags_for_handler(CPUMIPSState *env) { /* Exception handlers are entered in 32-bit mode. */ env->hflags &=3D ~(MIPS_HFLAG_M16); /* ...except that microMIPS lets you choose. */ if (env->insn_flags & ASE_MICROMIPS) { - env->hflags |=3D (!!(env->CP0_Config3 - & (1 << CP0C3_ISA_ON_EXC)) + env->hflags |=3D (!!(env->CP0_Config3 & + (1 << CP0C3_ISA_ON_EXC)) << MIPS_HFLAG_M16_SHIFT); } } @@ -1096,10 +1107,12 @@ void mips_cpu_do_interrupt(CPUState *cs) switch (cs->exception_index) { case EXCP_DSS: env->CP0_Debug |=3D 1 << CP0DB_DSS; - /* Debug single step cannot be raised inside a delay slot and - resume will always occur on the next instruction - (but we assume the pc has always been updated during - code translation). */ + /* + * Debug single step cannot be raised inside a delay slot and + * resume will always occur on the next instruction + * (but we assume the pc has always been updated during + * code translation). + */ env->CP0_DEPC =3D env->active_tc.PC | !!(env->hflags & MIPS_HFLAG_= M16); goto enter_debug_mode; case EXCP_DINT: @@ -1111,7 +1124,8 @@ void mips_cpu_do_interrupt(CPUState *cs) case EXCP_DBp: env->CP0_Debug |=3D 1 << CP0DB_DBp; /* Setup DExcCode - SDBBP instruction */ - env->CP0_Debug =3D (env->CP0_Debug & ~(0x1fULL << CP0DB_DEC)) | 9 = << CP0DB_DEC; + env->CP0_Debug =3D (env->CP0_Debug & ~(0x1fULL << CP0DB_DEC)) | + (9 << CP0DB_DEC); goto set_DEPC; case EXCP_DDBS: env->CP0_Debug |=3D 1 << CP0DB_DDBS; @@ -1132,8 +1146,9 @@ void mips_cpu_do_interrupt(CPUState *cs) env->hflags |=3D MIPS_HFLAG_DM | MIPS_HFLAG_CP0; env->hflags &=3D ~(MIPS_HFLAG_KSU); /* EJTAG probe trap enable is not implemented... */ - if (!(env->CP0_Status & (1 << CP0St_EXL))) + if (!(env->CP0_Status & (1 << CP0St_EXL))) { env->CP0_Cause &=3D ~(1U << CP0Ca_BD); + } env->active_tc.PC =3D env->exception_base + 0x480; set_hflags_for_handler(env); break; @@ -1159,8 +1174,9 @@ void mips_cpu_do_interrupt(CPUState *cs) } env->hflags |=3D MIPS_HFLAG_CP0; env->hflags &=3D ~(MIPS_HFLAG_KSU); - if (!(env->CP0_Status & (1 << CP0St_EXL))) + if (!(env->CP0_Status & (1 << CP0St_EXL))) { env->CP0_Cause &=3D ~(1U << CP0Ca_BD); + } env->active_tc.PC =3D env->exception_base; set_hflags_for_handler(env); break; @@ -1176,12 +1192,16 @@ void mips_cpu_do_interrupt(CPUState *cs) uint32_t pending =3D (env->CP0_Cause & CP0Ca_IP_mask) >> C= P0Ca_IP; =20 if (env->CP0_Config3 & (1 << CP0C3_VEIC)) { - /* For VEIC mode, the external interrupt controller fe= eds - * the vector through the CP0Cause IP lines. */ + /* + * For VEIC mode, the external interrupt controller fe= eds + * the vector through the CP0Cause IP lines. + */ vector =3D pending; } else { - /* Vectored Interrupts - * Mask with Status.IM7-IM0 to get enabled interrupts.= */ + /* + * Vectored Interrupts + * Mask with Status.IM7-IM0 to get enabled interrupts. + */ pending &=3D (env->CP0_Status >> CP0St_IM) & 0xff; /* Find the highest-priority interrupt. */ while (pending >>=3D 1) { @@ -1354,7 +1374,8 @@ void mips_cpu_do_interrupt(CPUState *cs) =20 env->active_tc.PC +=3D offset; set_hflags_for_handler(env); - env->CP0_Cause =3D (env->CP0_Cause & ~(0x1f << CP0Ca_EC)) | (cause= << CP0Ca_EC); + env->CP0_Cause =3D (env->CP0_Cause & ~(0x1f << CP0Ca_EC)) | + (cause << CP0Ca_EC); break; default: abort(); @@ -1390,7 +1411,7 @@ bool mips_cpu_exec_interrupt(CPUState *cs, int interr= upt_request) } =20 #if !defined(CONFIG_USER_ONLY) -void r4k_invalidate_tlb (CPUMIPSState *env, int idx, int use_extra) +void r4k_invalidate_tlb(CPUMIPSState *env, int idx, int use_extra) { CPUState *cs =3D env_cpu(env); r4k_tlb_t *tlb; @@ -1400,16 +1421,20 @@ void r4k_invalidate_tlb (CPUMIPSState *env, int idx= , int use_extra) target_ulong mask; =20 tlb =3D &env->tlb->mmu.r4k.tlb[idx]; - /* The qemu TLB is flushed when the ASID changes, so no need to - flush these entries again. */ + /* + * The qemu TLB is flushed when the ASID changes, so no need to + * flush these entries again. + */ if (tlb->G =3D=3D 0 && tlb->ASID !=3D ASID) { return; } =20 if (use_extra && env->tlb->tlb_in_use < MIPS_TLB_MAX) { - /* For tlbwr, we can shadow the discarded entry into - a new (fake) TLB entry, as long as the guest can not - tell that it's there. */ + /* + * For tlbwr, we can shadow the discarded entry into + * a new (fake) TLB entry, as long as the guest can not + * tell that it's there. + */ env->tlb->mmu.r4k.tlb[env->tlb->tlb_in_use] =3D *tlb; env->tlb->tlb_in_use++; return; --=20 2.7.4