From nobody Wed Nov 12 18:20:33 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1572023705; cv=none; d=zoho.com; s=zohoarc; b=JxBgktQjhySuMMOvrRu1dFWvIJ2w4plpUtgHRahgqd3kEXAuewUjsjQFhBxXMIafWXYxaqYv4KZ8YGAMXvTGsXsunjmtWL2xF6dUo4Drd21slvBu6Gm97+4XY49H8x70Cmfix/KClK4khOBfuPHAQJHxUYs7dc0cZZ3oVls0cTk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1572023705; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To; bh=fm9yUVfaGRg7W6enH/492h4//jdagpPztWkRuFlxaZY=; b=EeNg/Dn2Y15pAhG5h0CgtajyN3nxyDSUeqVfGMf6Gt6A0wf0yKBpWj/nps8hnL+m4BP3CXlf8b5dWgyWQGkD8V2pWeDHREnwzw4oB8L159z8PIlhEdWHuWfoJapSP97HoQyl4sOvowV1mhrN3LlQEA7ej33rExGQUDukAvaiczs= ARC-Authentication-Results: i=1; mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1572023705076546.1936582620945; Fri, 25 Oct 2019 10:15:05 -0700 (PDT) Received: from localhost ([::1]:34806 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iO3B1-0004VB-GG for importer@patchew.org; Fri, 25 Oct 2019 13:15:03 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:40569) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iO2ic-0004xK-4k for qemu-devel@nongnu.org; Fri, 25 Oct 2019 12:45:46 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iO2iX-0002FL-1Z for qemu-devel@nongnu.org; Fri, 25 Oct 2019 12:45:41 -0400 Received: from mx2.rt-rk.com ([89.216.37.149]:34452 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1iO2iW-0002Dv-LA for qemu-devel@nongnu.org; Fri, 25 Oct 2019 12:45:36 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id ECCB31A2286; Fri, 25 Oct 2019 18:44:29 +0200 (CEST) Received: from rtrkw774-lin.domain.local (rtrkw774-lin.domain.local [10.10.14.106]) by mail.rt-rk.com (Postfix) with ESMTPSA id A65681A21F7; Fri, 25 Oct 2019 18:44:29 +0200 (CEST) X-Virus-Scanned: amavisd-new at rt-rk.com From: Aleksandar Markovic To: qemu-devel@nongnu.org Subject: [PULL 11/20] target/mips: msa: Split helpers for HSUB_. Date: Fri, 25 Oct 2019 18:44:13 +0200 Message-Id: <1572021862-28273-12-git-send-email-aleksandar.markovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1572021862-28273-1-git-send-email-aleksandar.markovic@rt-rk.com> References: <1572021862-28273-1-git-send-email-aleksandar.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 89.216.37.149 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, amarkovic@wavecomp.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Aleksandar Markovic Achieves clearer code and slightly better performance. Signed-off-by: Aleksandar Markovic Reviewed-by: Aleksandar Rikalo Message-Id: <1571826227-10583-12-git-send-email-aleksandar.markovic@rt-rk.c= om> --- target/mips/helper.h | 10 ++++- target/mips/msa_helper.c | 108 +++++++++++++++++++++++++++++++++++++++++--= ---- target/mips/translate.c | 32 +++++++++++--- 3 files changed, 129 insertions(+), 21 deletions(-) diff --git a/target/mips/helper.h b/target/mips/helper.h index 7bb13d5..d7c4bbf 100644 --- a/target/mips/helper.h +++ b/target/mips/helper.h @@ -945,6 +945,14 @@ DEF_HELPER_4(msa_mod_s_h, void, env, i32, i32, i32) DEF_HELPER_4(msa_mod_s_w, void, env, i32, i32, i32) DEF_HELPER_4(msa_mod_s_d, void, env, i32, i32, i32) =20 +DEF_HELPER_4(msa_hsub_s_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_hsub_s_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_hsub_s_d, void, env, i32, i32, i32) + +DEF_HELPER_4(msa_hsub_u_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_hsub_u_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_hsub_u_d, void, env, i32, i32, i32) + DEF_HELPER_4(msa_ilvev_b, void, env, i32, i32, i32) DEF_HELPER_4(msa_ilvev_h, void, env, i32, i32, i32) DEF_HELPER_4(msa_ilvev_w, void, env, i32, i32, i32) @@ -1059,8 +1067,6 @@ DEF_HELPER_5(msa_dpsub_u_df, void, env, i32, i32, i32= , i32) DEF_HELPER_5(msa_sld_df, void, env, i32, i32, i32, i32) DEF_HELPER_5(msa_splat_df, void, env, i32, i32, i32, i32) DEF_HELPER_5(msa_vshf_df, void, env, i32, i32, i32, i32) -DEF_HELPER_5(msa_hsub_s_df, void, env, i32, i32, i32, i32) -DEF_HELPER_5(msa_hsub_u_df, void, env, i32, i32, i32, i32) =20 DEF_HELPER_5(msa_sldi_df, void, env, i32, i32, i32, i32) DEF_HELPER_5(msa_splati_df, void, env, i32, i32, i32, i32) diff --git a/target/mips/msa_helper.c b/target/mips/msa_helper.c index 2400632..ae9e8e0 100644 --- a/target/mips/msa_helper.c +++ b/target/mips/msa_helper.c @@ -2888,7 +2888,101 @@ void helper_msa_mod_u_d(CPUMIPSState *env, * +---------------+------------------------------------------------------= ----+ */ =20 -/* TODO: insert Int Subtract group helpers here */ +/* TODO: insert the rest of Int Subtract group helpers here */ + + +static inline int64_t msa_hsub_s_df(uint32_t df, int64_t arg1, int64_t arg= 2) +{ + return SIGNED_ODD(arg1, df) - SIGNED_EVEN(arg2, df); +} + +void helper_msa_hsub_s_h(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); + + pwd->h[0] =3D msa_hsub_s_df(DF_HALF, pws->h[0], pwt->h[0]); + pwd->h[1] =3D msa_hsub_s_df(DF_HALF, pws->h[1], pwt->h[1]); + pwd->h[2] =3D msa_hsub_s_df(DF_HALF, pws->h[2], pwt->h[2]); + pwd->h[3] =3D msa_hsub_s_df(DF_HALF, pws->h[3], pwt->h[3]); + pwd->h[4] =3D msa_hsub_s_df(DF_HALF, pws->h[4], pwt->h[4]); + pwd->h[5] =3D msa_hsub_s_df(DF_HALF, pws->h[5], pwt->h[5]); + pwd->h[6] =3D msa_hsub_s_df(DF_HALF, pws->h[6], pwt->h[6]); + pwd->h[7] =3D msa_hsub_s_df(DF_HALF, pws->h[7], pwt->h[7]); +} + +void helper_msa_hsub_s_w(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); + + pwd->w[0] =3D msa_hsub_s_df(DF_WORD, pws->w[0], pwt->w[0]); + pwd->w[1] =3D msa_hsub_s_df(DF_WORD, pws->w[1], pwt->w[1]); + pwd->w[2] =3D msa_hsub_s_df(DF_WORD, pws->w[2], pwt->w[2]); + pwd->w[3] =3D msa_hsub_s_df(DF_WORD, pws->w[3], pwt->w[3]); +} + +void helper_msa_hsub_s_d(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); + + pwd->d[0] =3D msa_hsub_s_df(DF_DOUBLE, pws->d[0], pwt->d[0]); + pwd->d[1] =3D msa_hsub_s_df(DF_DOUBLE, pws->d[1], pwt->d[1]); +} + + +static inline int64_t msa_hsub_u_df(uint32_t df, int64_t arg1, int64_t arg= 2) +{ + return UNSIGNED_ODD(arg1, df) - UNSIGNED_EVEN(arg2, df); +} + +void helper_msa_hsub_u_h(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); + + pwd->h[0] =3D msa_hsub_u_df(DF_HALF, pws->h[0], pwt->h[0]); + pwd->h[1] =3D msa_hsub_u_df(DF_HALF, pws->h[1], pwt->h[1]); + pwd->h[2] =3D msa_hsub_u_df(DF_HALF, pws->h[2], pwt->h[2]); + pwd->h[3] =3D msa_hsub_u_df(DF_HALF, pws->h[3], pwt->h[3]); + pwd->h[4] =3D msa_hsub_u_df(DF_HALF, pws->h[4], pwt->h[4]); + pwd->h[5] =3D msa_hsub_u_df(DF_HALF, pws->h[5], pwt->h[5]); + pwd->h[6] =3D msa_hsub_u_df(DF_HALF, pws->h[6], pwt->h[6]); + pwd->h[7] =3D msa_hsub_u_df(DF_HALF, pws->h[7], pwt->h[7]); +} + +void helper_msa_hsub_u_w(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); + + pwd->w[0] =3D msa_hsub_u_df(DF_WORD, pws->w[0], pwt->w[0]); + pwd->w[1] =3D msa_hsub_u_df(DF_WORD, pws->w[1], pwt->w[1]); + pwd->w[2] =3D msa_hsub_u_df(DF_WORD, pws->w[2], pwt->w[2]); + pwd->w[3] =3D msa_hsub_u_df(DF_WORD, pws->w[3], pwt->w[3]); +} + +void helper_msa_hsub_u_d(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); + + pwd->d[0] =3D msa_hsub_u_df(DF_DOUBLE, pws->d[0], pwt->d[0]); + pwd->d[1] =3D msa_hsub_u_df(DF_DOUBLE, pws->d[1], pwt->d[1]); +} =20 =20 /* @@ -4450,16 +4544,6 @@ static inline void msa_sld_df(uint32_t df, wr_t *pwd, } } =20 -static inline int64_t msa_hsub_s_df(uint32_t df, int64_t arg1, int64_t arg= 2) -{ - return SIGNED_ODD(arg1, df) - SIGNED_EVEN(arg2, df); -} - -static inline int64_t msa_hsub_u_df(uint32_t df, int64_t arg1, int64_t arg= 2) -{ - return UNSIGNED_ODD(arg1, df) - UNSIGNED_EVEN(arg2, df); -} - static inline int64_t msa_mul_q_df(uint32_t df, int64_t arg1, int64_t arg2) { int64_t q_min =3D DF_MIN_INT(df); @@ -4545,8 +4629,6 @@ MSA_BINOP_DF(asub_u) MSA_BINOP_DF(mulv) MSA_BINOP_DF(dotp_s) MSA_BINOP_DF(dotp_u) -MSA_BINOP_DF(hsub_s) -MSA_BINOP_DF(hsub_u) =20 MSA_BINOP_DF(mul_q) MSA_BINOP_DF(mulr_q) diff --git a/target/mips/translate.c b/target/mips/translate.c index a57e0da..4c68c5b 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -29107,6 +29107,32 @@ static void gen_msa_3r(CPUMIPSState *env, DisasCon= text *ctx) break; } break; + case OPC_HSUB_S_df: + switch (df) { + case DF_HALF: + gen_helper_msa_hsub_s_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_hsub_s_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_hsub_s_d(cpu_env, twd, tws, twt); + break; + } + break; + case OPC_HSUB_U_df: + switch (df) { + case DF_HALF: + gen_helper_msa_hsub_u_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_hsub_u_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_hsub_u_d(cpu_env, twd, tws, twt); + break; + } + break; case OPC_DOTP_S_df: gen_helper_msa_dotp_s_df(cpu_env, tdf, twd, tws, twt); break; @@ -29125,12 +29151,6 @@ static void gen_msa_3r(CPUMIPSState *env, DisasCon= text *ctx) case OPC_DPSUB_U_df: gen_helper_msa_dpsub_u_df(cpu_env, tdf, twd, tws, twt); break; - case OPC_HSUB_S_df: - gen_helper_msa_hsub_s_df(cpu_env, tdf, twd, tws, twt); - break; - case OPC_HSUB_U_df: - gen_helper_msa_hsub_u_df(cpu_env, tdf, twd, tws, twt); - break; } break; default: --=20 2.7.4