From nobody Wed Nov 12 18:12:14 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1572023475; cv=none; d=zoho.com; s=zohoarc; b=GCpAEepQGdab1hSd0oROQTfXdURK01uuS3g1VqCQ1AJmacdlFLcUu6qW+sAzc3ol/zhU6hp5NTm+ejn0ZqDt+Xdom2XZBSkTvZeGiSPV9RfEpZBQItbRem91vsietE5byngBNXCt6QFkzPKBahMCWDQtNvSB8Ghc6VLOOl3PHhI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1572023475; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To; bh=6HzUEwRXtkme3nZFppwz0z9YQztBwt23RAV/o9W9HHM=; b=YvW/FfBleuuuV5+6dl5d+05s3qOQkSlPeSuLEP9wsOaLv3QP5eOodxh5v+Lyb1UhSn0jos/qLCWBk/FRJ4Wo8qHVxoZ+/9S/DQH5jFju9rFZ7qnPOJfRTp67gYdNDFbo+dcVH9UoN8tSDckIdYIBM8ku7GBz1YY984h9XelbV+Y= ARC-Authentication-Results: i=1; mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1572023475536983.1861440157547; Fri, 25 Oct 2019 10:11:15 -0700 (PDT) Received: from localhost ([::1]:34780 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iO37I-0001ng-Ct for importer@patchew.org; Fri, 25 Oct 2019 13:11:13 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:40578) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iO2ic-0004yA-9S for qemu-devel@nongnu.org; Fri, 25 Oct 2019 12:45:47 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iO2iX-0002Fm-B3 for qemu-devel@nongnu.org; Fri, 25 Oct 2019 12:45:42 -0400 Received: from mx2.rt-rk.com ([89.216.37.149]:34455 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1iO2iW-0002E2-Pb for qemu-devel@nongnu.org; Fri, 25 Oct 2019 12:45:37 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id DC9C11A2287; Fri, 25 Oct 2019 18:44:29 +0200 (CEST) Received: from rtrkw774-lin.domain.local (rtrkw774-lin.domain.local [10.10.14.106]) by mail.rt-rk.com (Postfix) with ESMTPSA id 9BA901A228C; Fri, 25 Oct 2019 18:44:29 +0200 (CEST) X-Virus-Scanned: amavisd-new at rt-rk.com From: Aleksandar Markovic To: qemu-devel@nongnu.org Subject: [PULL 10/20] target/mips: msa: Split helpers for PCK. Date: Fri, 25 Oct 2019 18:44:12 +0200 Message-Id: <1572021862-28273-11-git-send-email-aleksandar.markovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1572021862-28273-1-git-send-email-aleksandar.markovic@rt-rk.com> References: <1572021862-28273-1-git-send-email-aleksandar.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 89.216.37.149 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, amarkovic@wavecomp.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Aleksandar Markovic Achieves clearer code and slightly better performance. Reviewed-by: Aleksandar Rikalo Signed-off-by: Aleksandar Markovic Message-Id: <1571826227-10583-11-git-send-email-aleksandar.markovic@rt-rk.c= om> --- target/mips/helper.h | 11 +- target/mips/msa_helper.c | 386 +++++++++++++++++++++++++------------------= ---- target/mips/translate.c | 38 ++++- 3 files changed, 249 insertions(+), 186 deletions(-) diff --git a/target/mips/helper.h b/target/mips/helper.h index f779404..7bb13d5 100644 --- a/target/mips/helper.h +++ b/target/mips/helper.h @@ -967,6 +967,15 @@ DEF_HELPER_4(msa_nor_v, void, env, i32, i32, i32) DEF_HELPER_4(msa_or_v, void, env, i32, i32, i32) DEF_HELPER_4(msa_xor_v, void, env, i32, i32, i32) =20 +DEF_HELPER_4(msa_pckev_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_pckev_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_pckev_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_pckev_d, void, env, i32, i32, i32) +DEF_HELPER_4(msa_pckod_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_pckod_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_pckod_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_pckod_d, void, env, i32, i32, i32) + DEF_HELPER_4(msa_sll_b, void, env, i32, i32, i32) DEF_HELPER_4(msa_sll_h, void, env, i32, i32, i32) DEF_HELPER_4(msa_sll_w, void, env, i32, i32, i32) @@ -1049,8 +1058,6 @@ DEF_HELPER_5(msa_dpsub_s_df, void, env, i32, i32, i32= , i32) DEF_HELPER_5(msa_dpsub_u_df, void, env, i32, i32, i32, i32) DEF_HELPER_5(msa_sld_df, void, env, i32, i32, i32, i32) DEF_HELPER_5(msa_splat_df, void, env, i32, i32, i32, i32) -DEF_HELPER_5(msa_pckev_df, void, env, i32, i32, i32, i32) -DEF_HELPER_5(msa_pckod_df, void, env, i32, i32, i32, i32) DEF_HELPER_5(msa_vshf_df, void, env, i32, i32, i32, i32) DEF_HELPER_5(msa_hsub_s_df, void, env, i32, i32, i32, i32) DEF_HELPER_5(msa_hsub_u_df, void, env, i32, i32, i32, i32) diff --git a/target/mips/msa_helper.c b/target/mips/msa_helper.c index 38ff1da..2400632 100644 --- a/target/mips/msa_helper.c +++ b/target/mips/msa_helper.c @@ -3430,7 +3430,214 @@ void helper_msa_move_v(CPUMIPSState *env, uint32_t = wd, uint32_t ws) * +---------------+------------------------------------------------------= ----+ */ =20 -/* TODO: insert Pack group helpers here */ + +void helper_msa_pckev_b(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); + +#if defined(HOST_WORDS_BIGENDIAN) + pwd->b[8] =3D pws->b[9]; + pwd->b[10] =3D pws->b[13]; + pwd->b[12] =3D pws->b[1]; + pwd->b[14] =3D pws->b[5]; + pwd->b[0] =3D pwt->b[9]; + pwd->b[2] =3D pwt->b[13]; + pwd->b[4] =3D pwt->b[1]; + pwd->b[6] =3D pwt->b[5]; + pwd->b[9] =3D pws->b[11]; + pwd->b[13] =3D pws->b[3]; + pwd->b[1] =3D pwt->b[11]; + pwd->b[5] =3D pwt->b[3]; + pwd->b[11] =3D pws->b[15]; + pwd->b[3] =3D pwt->b[15]; + pwd->b[15] =3D pws->b[7]; + pwd->b[7] =3D pwt->b[7]; +#else + pwd->b[15] =3D pws->b[14]; + pwd->b[13] =3D pws->b[10]; + pwd->b[11] =3D pws->b[6]; + pwd->b[9] =3D pws->b[2]; + pwd->b[7] =3D pwt->b[14]; + pwd->b[5] =3D pwt->b[10]; + pwd->b[3] =3D pwt->b[6]; + pwd->b[1] =3D pwt->b[2]; + pwd->b[14] =3D pws->b[12]; + pwd->b[10] =3D pws->b[4]; + pwd->b[6] =3D pwt->b[12]; + pwd->b[2] =3D pwt->b[4]; + pwd->b[12] =3D pws->b[8]; + pwd->b[4] =3D pwt->b[8]; + pwd->b[8] =3D pws->b[0]; + pwd->b[0] =3D pwt->b[0]; +#endif +} + +void helper_msa_pckev_h(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); + +#if defined(HOST_WORDS_BIGENDIAN) + pwd->h[4] =3D pws->h[5]; + pwd->h[6] =3D pws->h[1]; + pwd->h[0] =3D pwt->h[5]; + pwd->h[2] =3D pwt->h[1]; + pwd->h[5] =3D pws->h[7]; + pwd->h[1] =3D pwt->h[7]; + pwd->h[7] =3D pws->h[3]; + pwd->h[3] =3D pwt->h[3]; +#else + pwd->h[7] =3D pws->h[6]; + pwd->h[5] =3D pws->h[2]; + pwd->h[3] =3D pwt->h[6]; + pwd->h[1] =3D pwt->h[2]; + pwd->h[6] =3D pws->h[4]; + pwd->h[2] =3D pwt->h[4]; + pwd->h[4] =3D pws->h[0]; + pwd->h[0] =3D pwt->h[0]; +#endif +} + +void helper_msa_pckev_w(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); + +#if defined(HOST_WORDS_BIGENDIAN) + pwd->w[2] =3D pws->w[3]; + pwd->w[0] =3D pwt->w[3]; + pwd->w[3] =3D pws->w[1]; + pwd->w[1] =3D pwt->w[1]; +#else + pwd->w[3] =3D pws->w[2]; + pwd->w[1] =3D pwt->w[2]; + pwd->w[2] =3D pws->w[0]; + pwd->w[0] =3D pwt->w[0]; +#endif +} + +void helper_msa_pckev_d(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); + + pwd->d[1] =3D pws->d[0]; + pwd->d[0] =3D pwt->d[0]; +} + + +void helper_msa_pckod_b(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); + +#if defined(HOST_WORDS_BIGENDIAN) + pwd->b[7] =3D pwt->b[6]; + pwd->b[5] =3D pwt->b[2]; + pwd->b[3] =3D pwt->b[14]; + pwd->b[1] =3D pwt->b[10]; + pwd->b[15] =3D pws->b[6]; + pwd->b[13] =3D pws->b[2]; + pwd->b[11] =3D pws->b[14]; + pwd->b[9] =3D pws->b[10]; + pwd->b[6] =3D pwt->b[4]; + pwd->b[2] =3D pwt->b[12]; + pwd->b[14] =3D pws->b[4]; + pwd->b[10] =3D pws->b[12]; + pwd->b[4] =3D pwt->b[0]; + pwd->b[12] =3D pws->b[0]; + pwd->b[0] =3D pwt->b[8]; + pwd->b[8] =3D pws->b[8]; +#else + pwd->b[0] =3D pwt->b[1]; + pwd->b[2] =3D pwt->b[5]; + pwd->b[4] =3D pwt->b[9]; + pwd->b[6] =3D pwt->b[13]; + pwd->b[8] =3D pws->b[1]; + pwd->b[10] =3D pws->b[5]; + pwd->b[12] =3D pws->b[9]; + pwd->b[14] =3D pws->b[13]; + pwd->b[1] =3D pwt->b[3]; + pwd->b[5] =3D pwt->b[11]; + pwd->b[9] =3D pws->b[3]; + pwd->b[13] =3D pws->b[11]; + pwd->b[3] =3D pwt->b[7]; + pwd->b[11] =3D pws->b[7]; + pwd->b[7] =3D pwt->b[15]; + pwd->b[15] =3D pws->b[15]; +#endif + +} + +void helper_msa_pckod_h(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); + +#if defined(HOST_WORDS_BIGENDIAN) + pwd->h[3] =3D pwt->h[2]; + pwd->h[1] =3D pwt->h[6]; + pwd->h[7] =3D pws->h[2]; + pwd->h[5] =3D pws->h[6]; + pwd->h[2] =3D pwt->h[0]; + pwd->h[6] =3D pws->h[0]; + pwd->h[0] =3D pwt->h[4]; + pwd->h[4] =3D pws->h[4]; +#else + pwd->h[0] =3D pwt->h[1]; + pwd->h[2] =3D pwt->h[5]; + pwd->h[4] =3D pws->h[1]; + pwd->h[6] =3D pws->h[5]; + pwd->h[1] =3D pwt->h[3]; + pwd->h[5] =3D pws->h[3]; + pwd->h[3] =3D pwt->h[7]; + pwd->h[7] =3D pws->h[7]; +#endif +} + +void helper_msa_pckod_w(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); + +#if defined(HOST_WORDS_BIGENDIAN) + pwd->w[1] =3D pwt->w[0]; + pwd->w[3] =3D pws->w[0]; + pwd->w[0] =3D pwt->w[2]; + pwd->w[2] =3D pws->w[2]; +#else + pwd->w[0] =3D pwt->w[1]; + pwd->w[2] =3D pws->w[1]; + pwd->w[1] =3D pwt->w[3]; + pwd->w[3] =3D pws->w[3]; +#endif +} + +void helper_msa_pckod_d(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); + + pwd->d[0] =3D pwt->d[1]; + pwd->d[1] =3D pws->d[1]; +} =20 =20 /* @@ -4675,183 +4882,6 @@ MSA_FN_DF(vshf_df) #undef MSA_FN_DF =20 =20 -void helper_msa_pckev_df(CPUMIPSState *env, uint32_t df, uint32_t wd, - uint32_t ws, uint32_t wt) -{ - wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); - wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); - wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); - - switch (df) { - case DF_BYTE: -#if defined(HOST_WORDS_BIGENDIAN) - pwd->b[8] =3D pws->b[9]; - pwd->b[10] =3D pws->b[13]; - pwd->b[12] =3D pws->b[1]; - pwd->b[14] =3D pws->b[5]; - pwd->b[0] =3D pwt->b[9]; - pwd->b[2] =3D pwt->b[13]; - pwd->b[4] =3D pwt->b[1]; - pwd->b[6] =3D pwt->b[5]; - pwd->b[9] =3D pws->b[11]; - pwd->b[13] =3D pws->b[3]; - pwd->b[1] =3D pwt->b[11]; - pwd->b[5] =3D pwt->b[3]; - pwd->b[11] =3D pws->b[15]; - pwd->b[3] =3D pwt->b[15]; - pwd->b[15] =3D pws->b[7]; - pwd->b[7] =3D pwt->b[7]; -#else - pwd->b[15] =3D pws->b[14]; - pwd->b[13] =3D pws->b[10]; - pwd->b[11] =3D pws->b[6]; - pwd->b[9] =3D pws->b[2]; - pwd->b[7] =3D pwt->b[14]; - pwd->b[5] =3D pwt->b[10]; - pwd->b[3] =3D pwt->b[6]; - pwd->b[1] =3D pwt->b[2]; - pwd->b[14] =3D pws->b[12]; - pwd->b[10] =3D pws->b[4]; - pwd->b[6] =3D pwt->b[12]; - pwd->b[2] =3D pwt->b[4]; - pwd->b[12] =3D pws->b[8]; - pwd->b[4] =3D pwt->b[8]; - pwd->b[8] =3D pws->b[0]; - pwd->b[0] =3D pwt->b[0]; -#endif - break; - case DF_HALF: -#if defined(HOST_WORDS_BIGENDIAN) - pwd->h[4] =3D pws->h[5]; - pwd->h[6] =3D pws->h[1]; - pwd->h[0] =3D pwt->h[5]; - pwd->h[2] =3D pwt->h[1]; - pwd->h[5] =3D pws->h[7]; - pwd->h[1] =3D pwt->h[7]; - pwd->h[7] =3D pws->h[3]; - pwd->h[3] =3D pwt->h[3]; -#else - pwd->h[7] =3D pws->h[6]; - pwd->h[5] =3D pws->h[2]; - pwd->h[3] =3D pwt->h[6]; - pwd->h[1] =3D pwt->h[2]; - pwd->h[6] =3D pws->h[4]; - pwd->h[2] =3D pwt->h[4]; - pwd->h[4] =3D pws->h[0]; - pwd->h[0] =3D pwt->h[0]; -#endif - break; - case DF_WORD: -#if defined(HOST_WORDS_BIGENDIAN) - pwd->w[2] =3D pws->w[3]; - pwd->w[0] =3D pwt->w[3]; - pwd->w[3] =3D pws->w[1]; - pwd->w[1] =3D pwt->w[1]; -#else - pwd->w[3] =3D pws->w[2]; - pwd->w[1] =3D pwt->w[2]; - pwd->w[2] =3D pws->w[0]; - pwd->w[0] =3D pwt->w[0]; -#endif - break; - case DF_DOUBLE: - pwd->d[1] =3D pws->d[0]; - pwd->d[0] =3D pwt->d[0]; - break; - default: - assert(0); - } -} - -void helper_msa_pckod_df(CPUMIPSState *env, uint32_t df, uint32_t wd, - uint32_t ws, uint32_t wt) -{ - wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); - wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); - wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); - - switch (df) { - case DF_BYTE: -#if defined(HOST_WORDS_BIGENDIAN) - pwd->b[7] =3D pwt->b[6]; - pwd->b[5] =3D pwt->b[2]; - pwd->b[3] =3D pwt->b[14]; - pwd->b[1] =3D pwt->b[10]; - pwd->b[15] =3D pws->b[6]; - pwd->b[13] =3D pws->b[2]; - pwd->b[11] =3D pws->b[14]; - pwd->b[9] =3D pws->b[10]; - pwd->b[6] =3D pwt->b[4]; - pwd->b[2] =3D pwt->b[12]; - pwd->b[14] =3D pws->b[4]; - pwd->b[10] =3D pws->b[12]; - pwd->b[4] =3D pwt->b[0]; - pwd->b[12] =3D pws->b[0]; - pwd->b[0] =3D pwt->b[8]; - pwd->b[8] =3D pws->b[8]; -#else - pwd->b[0] =3D pwt->b[1]; - pwd->b[2] =3D pwt->b[5]; - pwd->b[4] =3D pwt->b[9]; - pwd->b[6] =3D pwt->b[13]; - pwd->b[8] =3D pws->b[1]; - pwd->b[10] =3D pws->b[5]; - pwd->b[12] =3D pws->b[9]; - pwd->b[14] =3D pws->b[13]; - pwd->b[1] =3D pwt->b[3]; - pwd->b[5] =3D pwt->b[11]; - pwd->b[9] =3D pws->b[3]; - pwd->b[13] =3D pws->b[11]; - pwd->b[3] =3D pwt->b[7]; - pwd->b[11] =3D pws->b[7]; - pwd->b[7] =3D pwt->b[15]; - pwd->b[15] =3D pws->b[15]; -#endif - break; - case DF_HALF: -#if defined(HOST_WORDS_BIGENDIAN) - pwd->h[3] =3D pwt->h[2]; - pwd->h[1] =3D pwt->h[6]; - pwd->h[7] =3D pws->h[2]; - pwd->h[5] =3D pws->h[6]; - pwd->h[2] =3D pwt->h[0]; - pwd->h[6] =3D pws->h[0]; - pwd->h[0] =3D pwt->h[4]; - pwd->h[4] =3D pws->h[4]; -#else - pwd->h[0] =3D pwt->h[1]; - pwd->h[2] =3D pwt->h[5]; - pwd->h[4] =3D pws->h[1]; - pwd->h[6] =3D pws->h[5]; - pwd->h[1] =3D pwt->h[3]; - pwd->h[5] =3D pws->h[3]; - pwd->h[3] =3D pwt->h[7]; - pwd->h[7] =3D pws->h[7]; -#endif - break; - case DF_WORD: -#if defined(HOST_WORDS_BIGENDIAN) - pwd->w[1] =3D pwt->w[0]; - pwd->w[3] =3D pws->w[0]; - pwd->w[0] =3D pwt->w[2]; - pwd->w[2] =3D pws->w[2]; -#else - pwd->w[0] =3D pwt->w[1]; - pwd->w[2] =3D pws->w[1]; - pwd->w[1] =3D pwt->w[3]; - pwd->w[3] =3D pws->w[3]; -#endif - break; - case DF_DOUBLE: - pwd->d[0] =3D pwt->d[1]; - pwd->d[1] =3D pws->d[1]; - break; - default: - assert(0); - } -} - - void helper_msa_sldi_df(CPUMIPSState *env, uint32_t df, uint32_t wd, uint32_t ws, uint32_t n) { diff --git a/target/mips/translate.c b/target/mips/translate.c index 7cdf68d..a57e0da 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -28914,6 +28914,38 @@ static void gen_msa_3r(CPUMIPSState *env, DisasCon= text *ctx) break; } break; + case OPC_PCKEV_df: + switch (df) { + case DF_BYTE: + gen_helper_msa_pckev_b(cpu_env, twd, tws, twt); + break; + case DF_HALF: + gen_helper_msa_pckev_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_pckev_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_pckev_d(cpu_env, twd, tws, twt); + break; + } + break; + case OPC_PCKOD_df: + switch (df) { + case DF_BYTE: + gen_helper_msa_pckod_b(cpu_env, twd, tws, twt); + break; + case DF_HALF: + gen_helper_msa_pckod_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_pckod_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_pckod_d(cpu_env, twd, tws, twt); + break; + } + break; case OPC_SLL_df: switch (df) { case DF_BYTE: @@ -29024,15 +29056,9 @@ static void gen_msa_3r(CPUMIPSState *env, DisasCon= text *ctx) case OPC_MSUBV_df: gen_helper_msa_msubv_df(cpu_env, tdf, twd, tws, twt); break; - case OPC_PCKEV_df: - gen_helper_msa_pckev_df(cpu_env, tdf, twd, tws, twt); - break; case OPC_SUBSUU_S_df: gen_helper_msa_subsuu_s_df(cpu_env, tdf, twd, tws, twt); break; - case OPC_PCKOD_df: - gen_helper_msa_pckod_df(cpu_env, tdf, twd, tws, twt); - break; case OPC_ASUB_S_df: gen_helper_msa_asub_s_df(cpu_env, tdf, twd, tws, twt); break; --=20 2.7.4