From nobody Thu May 2 18:31:14 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1571842782; cv=none; d=zoho.com; s=zohoarc; b=RDM+NJr6yO/VbjmdfRSrv6dZ/bBV74NH3dWS2zz5Ut1TPM+H3ti0eV1EFNAxIv7YmNZBVPTOqCeIphmhmenYA4EOAOxEyv3U52JlL+9/Tyhp4gFRSRf/SQ90aEk+Ccucpf0GnXT1HaL3PbUtZtNv8stjCPWA7OqknvEWaG+Rho4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1571842782; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=tT7Z2PtEY5U/6RiF0XGfwxd6yyuO3XxZsid8e/dyj/o=; b=XwQQ9jZz4VB0CI3U2K97aTxukH7ke+LtfaE7n0p+Pomf6qb9nJ2o+uQ1mgv+GdRwDTEqBjccz60tWkOe45gk/Cgflwrg1fjwHJrHncZ04MFSMhYZAYJqTcqF3vec5ojc6WhKvGWceq5cy14ycTFAtD6BSM/n7SZjtx/tceYGN/E= ARC-Authentication-Results: i=1; mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 157184278243497.83640496528506; Wed, 23 Oct 2019 07:59:42 -0700 (PDT) Received: from localhost ([::1]:38520 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iNI6t-0006Oh-4S for importer@patchew.org; Wed, 23 Oct 2019 10:59:39 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:32924) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iNHzc-0000fu-Rm for qemu-devel@nongnu.org; Wed, 23 Oct 2019 10:52:10 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iNHza-0003xm-VZ for qemu-devel@nongnu.org; Wed, 23 Oct 2019 10:52:08 -0400 Received: from mx0a-001b2d01.pphosted.com ([148.163.156.1]:43028) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1iNHza-0003wx-KR for qemu-devel@nongnu.org; Wed, 23 Oct 2019 10:52:06 -0400 Received: from pps.filterd (m0098399.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id x9NEiJFQ092089 for ; Wed, 23 Oct 2019 10:52:05 -0400 Received: from e06smtp03.uk.ibm.com (e06smtp03.uk.ibm.com [195.75.94.99]) by mx0a-001b2d01.pphosted.com with ESMTP id 2vtprge739-1 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=NOT) for ; Wed, 23 Oct 2019 10:52:05 -0400 Received: from localhost by e06smtp03.uk.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; (version=TLSv1/SSLv3 cipher=AES256-GCM-SHA384 bits=256/256) Wed, 23 Oct 2019 15:52:01 +0100 Received: from d06av24.portsmouth.uk.ibm.com (d06av24.portsmouth.uk.ibm.com [9.149.105.60]) by b06avi18626390.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id x9NEpRCj35455382 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Wed, 23 Oct 2019 14:51:27 GMT Received: from d06av24.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 05A3442042; Wed, 23 Oct 2019 14:52:00 +0000 (GMT) Received: from d06av24.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id B4C474204F; Wed, 23 Oct 2019 14:51:59 +0000 (GMT) Received: from bahia.lan (unknown [9.145.36.67]) by d06av24.portsmouth.uk.ibm.com (Postfix) with ESMTP; Wed, 23 Oct 2019 14:51:59 +0000 (GMT) Subject: [PATCH 1/6] ppc: Add intc_destroy() handlers to SpaprInterruptController/PnvChip From: Greg Kurz To: David Gibson Date: Wed, 23 Oct 2019 16:51:59 +0200 In-Reply-To: <157184231371.3053790.17713393349394736594.stgit@bahia.lan> References: <157184231371.3053790.17713393349394736594.stgit@bahia.lan> User-Agent: StGit/unknown-version MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 x-cbid: 19102314-0012-0000-0000-0000035C2C1B X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 19102314-0013-0000-0000-000021975B3F Message-Id: <157184231937.3053790.14496504009511167948.stgit@bahia.lan> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2019-10-23_03:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=2 phishscore=0 bulkscore=0 spamscore=0 clxscore=1034 lowpriorityscore=0 mlxscore=0 impostorscore=0 mlxlogscore=892 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1908290000 definitions=main-1910230148 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [generic] [fuzzy] X-Received-From: 148.163.156.1 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Paolo Bonzini , qemu-ppc@nongnu.org, =?utf-8?q?C=C3=A9dric?= Le Goater , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" SpaprInterruptControllerClass and PnvChipClass have an intc_create() method that calls the appropriate routine, ie. icp_create() or xive_tctx_create(), to establish the link between the VCPU and the presenter component of the interrupt controller during realize. There aren't any symmetrical call to be called when the VCPU gets unrealized though. It is assumed that object_unparent() is the only thing to do. This is questionable because the parenting logic around the CPU and presenter objects is really an implementation detail of the interrupt controller. It shouldn't be open-coded in the machine code. Fix this by adding an intc_destroy() method that undoes what was done in intc_create(). Signed-off-by: Greg Kurz --- hw/intc/spapr_xive.c | 7 +++++++ hw/intc/xics.c | 5 +++++ hw/intc/xics_spapr.c | 7 +++++++ hw/intc/xive.c | 5 +++++ hw/ppc/pnv.c | 15 +++++++++++++++ hw/ppc/pnv_core.c | 7 ++++--- hw/ppc/spapr_cpu_core.c | 7 +------ hw/ppc/spapr_irq.c | 14 ++++++++++++++ include/hw/ppc/pnv.h | 1 + include/hw/ppc/spapr_irq.h | 2 ++ include/hw/ppc/xics.h | 1 + include/hw/ppc/xive.h | 1 + 12 files changed, 63 insertions(+), 9 deletions(-) diff --git a/hw/intc/spapr_xive.c b/hw/intc/spapr_xive.c index d8e1291905c3..b09cc48bcb61 100644 --- a/hw/intc/spapr_xive.c +++ b/hw/intc/spapr_xive.c @@ -555,6 +555,12 @@ static void spapr_xive_cpu_intc_reset(SpaprInterruptCo= ntroller *intc, xive_tctx_set_os_cam(tctx, xive_nvt_cam_line(nvt_blk, nvt_idx)); } =20 +static void spapr_xive_cpu_intc_destroy(SpaprInterruptController *intc, + PowerPCCPU *cpu) +{ + xive_tctx_destroy(spapr_cpu_state(cpu)->tctx); +} + static void spapr_xive_set_irq(SpaprInterruptController *intc, int irq, in= t val) { SpaprXive *xive =3D SPAPR_XIVE(intc); @@ -692,6 +698,7 @@ static void spapr_xive_class_init(ObjectClass *klass, v= oid *data) sicc->deactivate =3D spapr_xive_deactivate; sicc->cpu_intc_create =3D spapr_xive_cpu_intc_create; sicc->cpu_intc_reset =3D spapr_xive_cpu_intc_reset; + sicc->cpu_intc_destroy =3D spapr_xive_cpu_intc_destroy; sicc->claim_irq =3D spapr_xive_claim_irq; sicc->free_irq =3D spapr_xive_free_irq; sicc->set_irq =3D spapr_xive_set_irq; diff --git a/hw/intc/xics.c b/hw/intc/xics.c index 6da05763f9db..935f325749cb 100644 --- a/hw/intc/xics.c +++ b/hw/intc/xics.c @@ -401,6 +401,11 @@ Object *icp_create(Object *cpu, const char *type, XICS= Fabric *xi, Error **errp) return obj; } =20 +void icp_destroy(ICPState *icp) +{ + object_unparent(OBJECT(icp)); +} + /* * ICS: Source layer */ diff --git a/hw/intc/xics_spapr.c b/hw/intc/xics_spapr.c index 7418fb9f370c..5977d1bdb73f 100644 --- a/hw/intc/xics_spapr.c +++ b/hw/intc/xics_spapr.c @@ -352,6 +352,12 @@ static void xics_spapr_cpu_intc_reset(SpaprInterruptCo= ntroller *intc, icp_reset(spapr_cpu_state(cpu)->icp); } =20 +static void xics_spapr_cpu_intc_destroy(SpaprInterruptController *intc, + PowerPCCPU *cpu) +{ + icp_destroy(spapr_cpu_state(cpu)->icp); +} + static int xics_spapr_claim_irq(SpaprInterruptController *intc, int irq, bool lsi, Error **errp) { @@ -440,6 +446,7 @@ static void ics_spapr_class_init(ObjectClass *klass, vo= id *data) sicc->deactivate =3D xics_spapr_deactivate; sicc->cpu_intc_create =3D xics_spapr_cpu_intc_create; sicc->cpu_intc_reset =3D xics_spapr_cpu_intc_reset; + sicc->cpu_intc_destroy =3D xics_spapr_cpu_intc_destroy; sicc->claim_irq =3D xics_spapr_claim_irq; sicc->free_irq =3D xics_spapr_free_irq; sicc->set_irq =3D xics_spapr_set_irq; diff --git a/hw/intc/xive.c b/hw/intc/xive.c index f066be5eb5e3..38257aa02083 100644 --- a/hw/intc/xive.c +++ b/hw/intc/xive.c @@ -696,6 +696,11 @@ error: return NULL; } =20 +void xive_tctx_destroy(XiveTCTX *tctx) +{ + object_unparent(OBJECT(tctx)); +} + /* * XIVE ESB helpers */ diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c index 4a51fb65a834..bd17c3536dd5 100644 --- a/hw/ppc/pnv.c +++ b/hw/ppc/pnv.c @@ -778,6 +778,7 @@ static void pnv_chip_power8_intc_create(PnvChip *chip, = PowerPCCPU *cpu, pnv_cpu->intc =3D obj; } =20 + static void pnv_chip_power8_intc_reset(PnvChip *chip, PowerPCCPU *cpu) { PnvCPUState *pnv_cpu =3D pnv_cpu_state(cpu); @@ -785,6 +786,11 @@ static void pnv_chip_power8_intc_reset(PnvChip *chip, = PowerPCCPU *cpu) icp_reset(ICP(pnv_cpu->intc)); } =20 +static void pnv_chip_power8_intc_destroy(PnvChip *chip, PowerPCCPU *cpu) +{ + icp_destroy(ICP(pnv_cpu_state(cpu)->intc)); +} + /* * 0:48 Reserved - Read as zeroes * 49:52 Node ID @@ -829,6 +835,11 @@ static void pnv_chip_power9_intc_reset(PnvChip *chip, = PowerPCCPU *cpu) xive_tctx_reset(XIVE_TCTX(pnv_cpu->intc)); } =20 +static void pnv_chip_power9_intc_destroy(PnvChip *chip, PowerPCCPU *cpu) +{ + xive_tctx_destroy(XIVE_TCTX(pnv_cpu_state(cpu)->intc)); +} + /* * Allowed core identifiers on a POWER8 Processor Chip : * @@ -999,6 +1010,7 @@ static void pnv_chip_power8e_class_init(ObjectClass *k= lass, void *data) k->core_pir =3D pnv_chip_core_pir_p8; k->intc_create =3D pnv_chip_power8_intc_create; k->intc_reset =3D pnv_chip_power8_intc_reset; + k->intc_destroy =3D pnv_chip_power8_intc_destroy; k->isa_create =3D pnv_chip_power8_isa_create; k->dt_populate =3D pnv_chip_power8_dt_populate; k->pic_print_info =3D pnv_chip_power8_pic_print_info; @@ -1019,6 +1031,7 @@ static void pnv_chip_power8_class_init(ObjectClass *k= lass, void *data) k->core_pir =3D pnv_chip_core_pir_p8; k->intc_create =3D pnv_chip_power8_intc_create; k->intc_reset =3D pnv_chip_power8_intc_reset; + k->intc_destroy =3D pnv_chip_power8_intc_destroy; k->isa_create =3D pnv_chip_power8_isa_create; k->dt_populate =3D pnv_chip_power8_dt_populate; k->pic_print_info =3D pnv_chip_power8_pic_print_info; @@ -1039,6 +1052,7 @@ static void pnv_chip_power8nvl_class_init(ObjectClass= *klass, void *data) k->core_pir =3D pnv_chip_core_pir_p8; k->intc_create =3D pnv_chip_power8_intc_create; k->intc_reset =3D pnv_chip_power8_intc_reset; + k->intc_destroy =3D pnv_chip_power8_intc_destroy; k->isa_create =3D pnv_chip_power8nvl_isa_create; k->dt_populate =3D pnv_chip_power8_dt_populate; k->pic_print_info =3D pnv_chip_power8_pic_print_info; @@ -1209,6 +1223,7 @@ static void pnv_chip_power9_class_init(ObjectClass *k= lass, void *data) k->core_pir =3D pnv_chip_core_pir_p9; k->intc_create =3D pnv_chip_power9_intc_create; k->intc_reset =3D pnv_chip_power9_intc_reset; + k->intc_destroy =3D pnv_chip_power9_intc_destroy; k->isa_create =3D pnv_chip_power9_isa_create; k->dt_populate =3D pnv_chip_power9_dt_populate; k->pic_print_info =3D pnv_chip_power9_pic_print_info; diff --git a/hw/ppc/pnv_core.c b/hw/ppc/pnv_core.c index 328ad07c8d06..a66c4b471407 100644 --- a/hw/ppc/pnv_core.c +++ b/hw/ppc/pnv_core.c @@ -270,11 +270,12 @@ err: error_propagate(errp, local_err); } =20 -static void pnv_core_cpu_unrealize(PowerPCCPU *cpu) +static void pnv_core_cpu_unrealize(PowerPCCPU *cpu, PnvChip *chip) { PnvCPUState *pnv_cpu =3D pnv_cpu_state(cpu); + PnvChipClass *pcc =3D PNV_CHIP_GET_CLASS(chip); =20 - object_unparent(OBJECT(pnv_cpu_state(cpu)->intc)); + pcc->intc_destroy(chip, cpu); cpu_remove_sync(CPU(cpu)); cpu->machine_data =3D NULL; g_free(pnv_cpu); @@ -290,7 +291,7 @@ static void pnv_core_unrealize(DeviceState *dev, Error = **errp) qemu_unregister_reset(pnv_core_reset, pc); =20 for (i =3D 0; i < cc->nr_threads; i++) { - pnv_core_cpu_unrealize(pc->threads[i]); + pnv_core_cpu_unrealize(pc->threads[i], pc->chip); } g_free(pc->threads); } diff --git a/hw/ppc/spapr_cpu_core.c b/hw/ppc/spapr_cpu_core.c index ef7b27a66d56..8339c4c0f86b 100644 --- a/hw/ppc/spapr_cpu_core.c +++ b/hw/ppc/spapr_cpu_core.c @@ -195,12 +195,7 @@ static void spapr_unrealize_vcpu(PowerPCCPU *cpu, Spap= rCpuCore *sc) if (!sc->pre_3_0_migration) { vmstate_unregister(NULL, &vmstate_spapr_cpu_state, cpu->machine_da= ta); } - if (spapr_cpu_state(cpu)->icp) { - object_unparent(OBJECT(spapr_cpu_state(cpu)->icp)); - } - if (spapr_cpu_state(cpu)->tctx) { - object_unparent(OBJECT(spapr_cpu_state(cpu)->tctx)); - } + spapr_irq_cpu_intc_destroy(SPAPR_MACHINE(qdev_get_machine()), cpu); cpu_remove_sync(CPU(cpu)); object_unparent(OBJECT(cpu)); } diff --git a/hw/ppc/spapr_irq.c b/hw/ppc/spapr_irq.c index b941608b69ba..168044be853a 100644 --- a/hw/ppc/spapr_irq.c +++ b/hw/ppc/spapr_irq.c @@ -234,6 +234,20 @@ void spapr_irq_cpu_intc_reset(SpaprMachineState *spapr= , PowerPCCPU *cpu) } } =20 +void spapr_irq_cpu_intc_destroy(SpaprMachineState *spapr, PowerPCCPU *cpu) +{ + SpaprInterruptController *intcs[] =3D ALL_INTCS(spapr); + int i; + + for (i =3D 0; i < ARRAY_SIZE(intcs); i++) { + SpaprInterruptController *intc =3D intcs[i]; + if (intc) { + SpaprInterruptControllerClass *sicc =3D SPAPR_INTC_GET_CLASS(i= ntc); + sicc->cpu_intc_destroy(intc, cpu); + } + } +} + static void spapr_set_irq(void *opaque, int irq, int level) { SpaprMachineState *spapr =3D SPAPR_MACHINE(opaque); diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h index 2a780e633f23..0b4c722e6b48 100644 --- a/include/hw/ppc/pnv.h +++ b/include/hw/ppc/pnv.h @@ -112,6 +112,7 @@ typedef struct PnvChipClass { uint32_t (*core_pir)(PnvChip *chip, uint32_t core_id); void (*intc_create)(PnvChip *chip, PowerPCCPU *cpu, Error **errp); void (*intc_reset)(PnvChip *chip, PowerPCCPU *cpu); + void (*intc_destroy)(PnvChip *chip, PowerPCCPU *cpu); ISABus *(*isa_create)(PnvChip *chip, Error **errp); void (*dt_populate)(PnvChip *chip, void *fdt); void (*pic_print_info)(PnvChip *chip, Monitor *mon); diff --git a/include/hw/ppc/spapr_irq.h b/include/hw/ppc/spapr_irq.h index 09232999b07e..ff814d13de37 100644 --- a/include/hw/ppc/spapr_irq.h +++ b/include/hw/ppc/spapr_irq.h @@ -53,6 +53,7 @@ typedef struct SpaprInterruptControllerClass { int (*cpu_intc_create)(SpaprInterruptController *intc, PowerPCCPU *cpu, Error **errp); void (*cpu_intc_reset)(SpaprInterruptController *intc, PowerPCCPU *cpu= ); + void (*cpu_intc_destroy)(SpaprInterruptController *intc, PowerPCCPU *c= pu); int (*claim_irq)(SpaprInterruptController *intc, int irq, bool lsi, Error **errp); void (*free_irq)(SpaprInterruptController *intc, int irq); @@ -70,6 +71,7 @@ void spapr_irq_update_active_intc(SpaprMachineState *spap= r); int spapr_irq_cpu_intc_create(SpaprMachineState *spapr, PowerPCCPU *cpu, Error **errp); void spapr_irq_cpu_intc_reset(SpaprMachineState *spapr, PowerPCCPU *cpu); +void spapr_irq_cpu_intc_destroy(SpaprMachineState *spapr, PowerPCCPU *cpu); void spapr_irq_print_info(SpaprMachineState *spapr, Monitor *mon); void spapr_irq_dt(SpaprMachineState *spapr, uint32_t nr_servers, void *fdt, uint32_t phandle); diff --git a/include/hw/ppc/xics.h b/include/hw/ppc/xics.h index 602173c12250..48a75aa4ab75 100644 --- a/include/hw/ppc/xics.h +++ b/include/hw/ppc/xics.h @@ -181,6 +181,7 @@ void icp_resend(ICPState *ss); =20 Object *icp_create(Object *cpu, const char *type, XICSFabric *xi, Error **errp); +void icp_destroy(ICPState *icp); =20 /* KVM */ void icp_get_kvm_state(ICPState *icp); diff --git a/include/hw/ppc/xive.h b/include/hw/ppc/xive.h index 99381639f50c..8fd439ec9bba 100644 --- a/include/hw/ppc/xive.h +++ b/include/hw/ppc/xive.h @@ -416,6 +416,7 @@ uint64_t xive_tctx_tm_read(XiveTCTX *tctx, hwaddr offse= t, unsigned size); void xive_tctx_pic_print_info(XiveTCTX *tctx, Monitor *mon); Object *xive_tctx_create(Object *cpu, XiveRouter *xrtr, Error **errp); void xive_tctx_reset(XiveTCTX *tctx); +void xive_tctx_destroy(XiveTCTX *tctx); =20 static inline uint32_t xive_nvt_cam_line(uint8_t nvt_blk, uint32_t nvt_idx) { From nobody Thu May 2 18:31:14 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1571842782; cv=none; d=zoho.com; s=zohoarc; b=ocBHb3ZYtrWZ/szxONdThfVOB77WzZrTOJWVeMCkjrx5vZTvP5FhumiFEtkaaWUVpap7Zzu8mNdSNCQPUS4RJFLkrWdXdsOGGDHDEv1rZP17Pp8xweiqSHwivsS4hfFKbsbRfGa3OJNlwGp/q80RWmgi7bHRzzphrlFVbI9hJBs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; 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Violators will be prosecuted; (version=TLSv1/SSLv3 cipher=AES256-GCM-SHA384 bits=256/256) Wed, 23 Oct 2019 15:52:06 +0100 Received: from d06av25.portsmouth.uk.ibm.com (d06av25.portsmouth.uk.ibm.com [9.149.105.61]) by b06cxnps4076.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id x9NEq5fF49348844 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Wed, 23 Oct 2019 14:52:05 GMT Received: from d06av25.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 8BE1F11C05C; Wed, 23 Oct 2019 14:52:05 +0000 (GMT) Received: from d06av25.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 5456011C04A; Wed, 23 Oct 2019 14:52:05 +0000 (GMT) Received: from bahia.lan (unknown [9.145.36.67]) by d06av25.portsmouth.uk.ibm.com (Postfix) with ESMTP; Wed, 23 Oct 2019 14:52:05 +0000 (GMT) Subject: [PATCH 2/6] xive, xics: Fix reference counting on CPU objects From: Greg Kurz To: David Gibson Date: Wed, 23 Oct 2019 16:52:05 +0200 In-Reply-To: <157184231371.3053790.17713393349394736594.stgit@bahia.lan> References: <157184231371.3053790.17713393349394736594.stgit@bahia.lan> User-Agent: StGit/unknown-version MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 x-cbid: 19102314-0008-0000-0000-00000326285C X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 19102314-0009-0000-0000-00004A455840 Message-Id: <157184232497.3053790.5571330781863409160.stgit@bahia.lan> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2019-10-23_03:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=0 phishscore=0 bulkscore=0 spamscore=0 clxscore=1034 lowpriorityscore=0 mlxscore=0 impostorscore=0 mlxlogscore=999 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1908290000 definitions=main-1910230148 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [generic] [fuzzy] X-Received-From: 148.163.158.5 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Paolo Bonzini , qemu-ppc@nongnu.org, =?utf-8?q?C=C3=A9dric?= Le Goater , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" When a VCPU gets connected to the XIVE interrupt controller, we add a const link targetting the CPU object to the TCTX object. Similar links are added to the ICP object when using the XICS interrupt controller. As explained in : * The caller must ensure that @target stays alive as long as * this property exists. In the case @target is a child of @obj, * this will be the case. Otherwise, the caller is responsible for * taking a reference. We're in the latter case for both XICS and XIVE. Add the missing calls to object_ref() and object_unref(). This doesn't fix any known issue because the life cycle of the TCTX or ICP happens to be shorter than the one of the CPU or XICS fabric, but better safe than sorry. Signed-off-by: Greg Kurz Reviewed-by: David Gibson --- hw/intc/xics.c | 8 +++++++- hw/intc/xive.c | 6 +++++- 2 files changed, 12 insertions(+), 2 deletions(-) diff --git a/hw/intc/xics.c b/hw/intc/xics.c index 935f325749cb..5f746079be46 100644 --- a/hw/intc/xics.c +++ b/hw/intc/xics.c @@ -388,8 +388,10 @@ Object *icp_create(Object *cpu, const char *type, XICS= Fabric *xi, Error **errp) obj =3D object_new(type); object_property_add_child(cpu, type, obj, &error_abort); object_unref(obj); + object_ref(OBJECT(xi)); object_property_add_const_link(obj, ICP_PROP_XICS, OBJECT(xi), &error_abort); + object_ref(cpu); object_property_add_const_link(obj, ICP_PROP_CPU, cpu, &error_abort); object_property_set_bool(obj, true, "realized", &local_err); if (local_err) { @@ -403,7 +405,11 @@ Object *icp_create(Object *cpu, const char *type, XICS= Fabric *xi, Error **errp) =20 void icp_destroy(ICPState *icp) { - object_unparent(OBJECT(icp)); + Object *obj =3D OBJECT(icp); + + object_unref(object_property_get_link(obj, ICP_PROP_CPU, &error_abort)= ); + object_unref(object_property_get_link(obj, ICP_PROP_XICS, &error_abort= )); + object_unparent(obj); } =20 /* diff --git a/hw/intc/xive.c b/hw/intc/xive.c index 38257aa02083..952a461d5329 100644 --- a/hw/intc/xive.c +++ b/hw/intc/xive.c @@ -682,6 +682,7 @@ Object *xive_tctx_create(Object *cpu, XiveRouter *xrtr,= Error **errp) obj =3D object_new(TYPE_XIVE_TCTX); object_property_add_child(cpu, TYPE_XIVE_TCTX, obj, &error_abort); object_unref(obj); + object_ref(cpu); object_property_add_const_link(obj, "cpu", cpu, &error_abort); object_property_set_bool(obj, true, "realized", &local_err); if (local_err) { @@ -698,7 +699,10 @@ error: =20 void xive_tctx_destroy(XiveTCTX *tctx) { - object_unparent(OBJECT(tctx)); + Object *obj =3D OBJECT(tctx); + + object_unref(object_property_get_link(obj, "cpu", &error_abort)); + object_unparent(obj); } =20 /* From nobody Thu May 2 18:31:14 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1571843173; cv=none; d=zoho.com; s=zohoarc; b=izttQjk+kYPHpXLmlMdQE6FvrEzL5P0Qhz+CmwVXJl7OAOIUwLbZ04jepJ9ZOmfHDwI/2KaL+ckBK2Eg7WzUzVf9Utj4INHC8pVXqXDKu38uUOy5cBGNXbn4FfDa2TDUTWb9WsS2Pe0jWDo78atlrVsfolIjRcUwCnlqKAgkzOM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1571843173; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=ye+58nSae9bjKAOh/N1u1ka6RIY/+Ff2oIjU/V0UlTQ=; b=RsIVq25repLm/MvOnF3RziVvLjnnNrKliEMgPVKFk9ZeiASZ2yPN2MufkI3azWEbezqOvYN2Lql6OhFT+ivaZn3/b0gWJPSpCZCrgKrux8nBqqBCP1Bm38dcJvqTLA+5AGJirTej0MIYQmbWk+TCWD0gWviK+xFQyKzjK/P1zqQ= ARC-Authentication-Results: i=1; mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1571843173387106.83498298936513; Wed, 23 Oct 2019 08:06:13 -0700 (PDT) Received: from localhost ([::1]:38978 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iNIDC-0002ZY-Ht for importer@patchew.org; Wed, 23 Oct 2019 11:06:10 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:33010) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iNHzm-0000oo-Pm for qemu-devel@nongnu.org; Wed, 23 Oct 2019 10:52:22 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iNHzl-000463-3u for qemu-devel@nongnu.org; Wed, 23 Oct 2019 10:52:18 -0400 Received: from mx0b-001b2d01.pphosted.com ([148.163.158.5]:53614 helo=mx0a-001b2d01.pphosted.com) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1iNHzk-00045Z-Vp for qemu-devel@nongnu.org; Wed, 23 Oct 2019 10:52:17 -0400 Received: from pps.filterd (m0098414.ppops.net [127.0.0.1]) by mx0b-001b2d01.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id x9NEj7dp128863 for ; Wed, 23 Oct 2019 10:52:16 -0400 Received: from e06smtp04.uk.ibm.com (e06smtp04.uk.ibm.com [195.75.94.100]) by mx0b-001b2d01.pphosted.com with ESMTP id 2vtqg6ccum-1 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=NOT) for ; Wed, 23 Oct 2019 10:52:16 -0400 Received: from localhost by e06smtp04.uk.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; (version=TLSv1/SSLv3 cipher=AES256-GCM-SHA384 bits=256/256) Wed, 23 Oct 2019 15:52:12 +0100 Received: from d06av26.portsmouth.uk.ibm.com (d06av26.portsmouth.uk.ibm.com [9.149.105.62]) by b06avi18626390.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id x9NEpcm829229436 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Wed, 23 Oct 2019 14:51:38 GMT Received: from d06av26.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 2744FAE053; Wed, 23 Oct 2019 14:52:11 +0000 (GMT) Received: from d06av26.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id E2B1BAE05A; Wed, 23 Oct 2019 14:52:10 +0000 (GMT) Received: from bahia.lan (unknown [9.145.36.67]) by d06av26.portsmouth.uk.ibm.com (Postfix) with ESMTP; Wed, 23 Oct 2019 14:52:10 +0000 (GMT) Subject: [PATCH 3/6] ppc: Reparent presenter objects to the interrupt controller object From: Greg Kurz To: David Gibson Date: Wed, 23 Oct 2019 16:52:10 +0200 In-Reply-To: <157184231371.3053790.17713393349394736594.stgit@bahia.lan> References: <157184231371.3053790.17713393349394736594.stgit@bahia.lan> User-Agent: StGit/unknown-version MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 x-cbid: 19102314-0016-0000-0000-000002BC2A79 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 19102314-0017-0000-0000-0000331D6B04 Message-Id: <157184233056.3053790.13073641279894392321.stgit@bahia.lan> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2019-10-23_03:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=0 phishscore=0 bulkscore=0 spamscore=0 clxscore=1034 lowpriorityscore=0 mlxscore=0 impostorscore=0 mlxlogscore=860 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1908290000 definitions=main-1910230148 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [generic] [fuzzy] X-Received-From: 148.163.158.5 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Paolo Bonzini , qemu-ppc@nongnu.org, =?utf-8?q?C=C3=A9dric?= Le Goater , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Each VCPU is associated to a presenter object within the interrupt controller, ie. TCTX for XIVE and ICP for XICS, but our current models put these objects below the VCPU, and we rely on CPU_FOREACH() to do anything that involves presenters. This recently bit us with the CAM line matching logic in XIVE because CPU_FOREACH() can race with CPU hotplug and we ended up considering a VCPU that wasn't associated to a TCTX object yet. Other users of CPU_FOREACH() are 'info pic' for both XICS and XIVE. It is again very easy to crash QEMU with concurrent VCPU hotplug/unplug and 'info pic'. Reparent the presenter objects to the corresponding interrupt controller object, ie. XIVE router or ICS, to make it clear they are not some extra data hanging from the CPU but internal XIVE or XICS entities. The CPU object now needs to explicitely take a reference on the presenter to ensure its pointer remains valid until unrealize time. This will allow to get rid of CPU_FOREACH() and ease further improvements to the XIVE model. This change doesn't impact section ids and is thus transparent to migration. Signed-off-by: Greg Kurz --- hw/intc/spapr_xive.c | 6 +++++- hw/intc/xics.c | 7 +++++-- hw/intc/xics_spapr.c | 8 ++++++-- hw/intc/xive.c | 4 +++- hw/ppc/pnv.c | 17 +++++++++++++---- include/hw/ppc/xics.h | 2 +- 6 files changed, 33 insertions(+), 11 deletions(-) diff --git a/hw/intc/spapr_xive.c b/hw/intc/spapr_xive.c index b09cc48bcb61..d74ee71e76b4 100644 --- a/hw/intc/spapr_xive.c +++ b/hw/intc/spapr_xive.c @@ -526,6 +526,7 @@ static int spapr_xive_cpu_intc_create(SpaprInterruptCon= troller *intc, return -1; } =20 + object_ref(obj); spapr_cpu->tctx =3D XIVE_TCTX(obj); return 0; } @@ -558,7 +559,10 @@ static void spapr_xive_cpu_intc_reset(SpaprInterruptCo= ntroller *intc, static void spapr_xive_cpu_intc_destroy(SpaprInterruptController *intc, PowerPCCPU *cpu) { - xive_tctx_destroy(spapr_cpu_state(cpu)->tctx); + XiveTCTX *tctx =3D spapr_cpu_state(cpu)->tctx; + + object_unref(OBJECT(tctx)); + xive_tctx_destroy(tctx); } =20 static void spapr_xive_set_irq(SpaprInterruptController *intc, int irq, in= t val) diff --git a/hw/intc/xics.c b/hw/intc/xics.c index 5f746079be46..d5e4db668a4b 100644 --- a/hw/intc/xics.c +++ b/hw/intc/xics.c @@ -380,13 +380,16 @@ static const TypeInfo icp_info =3D { .class_size =3D sizeof(ICPStateClass), }; =20 -Object *icp_create(Object *cpu, const char *type, XICSFabric *xi, Error **= errp) +Object *icp_create(Object *cpu, const char *type, ICSState *ics, XICSFabri= c *xi, + Error **errp) { Error *local_err =3D NULL; + g_autofree char *name =3D NULL; Object *obj; =20 obj =3D object_new(type); - object_property_add_child(cpu, type, obj, &error_abort); + name =3D g_strdup_printf("%s[%d]", type, CPU(cpu)->cpu_index); + object_property_add_child(OBJECT(ics), name, obj, &error_abort); object_unref(obj); object_ref(OBJECT(xi)); object_property_add_const_link(obj, ICP_PROP_XICS, OBJECT(xi), diff --git a/hw/intc/xics_spapr.c b/hw/intc/xics_spapr.c index 5977d1bdb73f..080ed73aad64 100644 --- a/hw/intc/xics_spapr.c +++ b/hw/intc/xics_spapr.c @@ -337,11 +337,12 @@ static int xics_spapr_cpu_intc_create(SpaprInterruptC= ontroller *intc, Object *obj; SpaprCpuState *spapr_cpu =3D spapr_cpu_state(cpu); =20 - obj =3D icp_create(OBJECT(cpu), TYPE_ICP, ics->xics, errp); + obj =3D icp_create(OBJECT(cpu), TYPE_ICP, ics, ics->xics, errp); if (!obj) { return -1; } =20 + object_ref(obj); spapr_cpu->icp =3D ICP(obj); return 0; } @@ -355,7 +356,10 @@ static void xics_spapr_cpu_intc_reset(SpaprInterruptCo= ntroller *intc, static void xics_spapr_cpu_intc_destroy(SpaprInterruptController *intc, PowerPCCPU *cpu) { - icp_destroy(spapr_cpu_state(cpu)->icp); + ICPState *icp =3D spapr_cpu_state(cpu)->icp; + + object_unref(OBJECT(icp)); + icp_destroy(icp); } =20 static int xics_spapr_claim_irq(SpaprInterruptController *intc, int irq, diff --git a/hw/intc/xive.c b/hw/intc/xive.c index 952a461d5329..8d2da4a11163 100644 --- a/hw/intc/xive.c +++ b/hw/intc/xive.c @@ -677,10 +677,12 @@ static const TypeInfo xive_tctx_info =3D { Object *xive_tctx_create(Object *cpu, XiveRouter *xrtr, Error **errp) { Error *local_err =3D NULL; + g_autofree char *name =3D NULL; Object *obj; =20 obj =3D object_new(TYPE_XIVE_TCTX); - object_property_add_child(cpu, TYPE_XIVE_TCTX, obj, &error_abort); + name =3D g_strdup_printf(TYPE_XIVE_TCTX "[%d]", CPU(cpu)->cpu_index); + object_property_add_child(OBJECT(xrtr), name, obj, &error_abort); object_unref(obj); object_ref(cpu); object_property_add_const_link(obj, "cpu", cpu, &error_abort); diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c index bd17c3536dd5..cbeabf98bff6 100644 --- a/hw/ppc/pnv.c +++ b/hw/ppc/pnv.c @@ -767,14 +767,16 @@ static void pnv_chip_power8_intc_create(PnvChip *chip= , PowerPCCPU *cpu, Error *local_err =3D NULL; Object *obj; PnvCPUState *pnv_cpu =3D pnv_cpu_state(cpu); + Pnv8Chip *chip8 =3D PNV8_CHIP(chip); =20 - obj =3D icp_create(OBJECT(cpu), TYPE_PNV_ICP, XICS_FABRIC(qdev_get_mac= hine()), - &local_err); + obj =3D icp_create(OBJECT(cpu), TYPE_PNV_ICP, &chip8->psi.ics, + XICS_FABRIC(qdev_get_machine()), &local_err); if (local_err) { error_propagate(errp, local_err); return; } =20 + object_ref(obj); pnv_cpu->intc =3D obj; } =20 @@ -788,7 +790,10 @@ static void pnv_chip_power8_intc_reset(PnvChip *chip, = PowerPCCPU *cpu) =20 static void pnv_chip_power8_intc_destroy(PnvChip *chip, PowerPCCPU *cpu) { - icp_destroy(ICP(pnv_cpu_state(cpu)->intc)); + Object *intc =3D pnv_cpu_state(cpu)->intc; + + object_unref(intc); + icp_destroy(ICP(intc)); } =20 /* @@ -825,6 +830,7 @@ static void pnv_chip_power9_intc_create(PnvChip *chip, = PowerPCCPU *cpu, return; } =20 + object_ref(obj); pnv_cpu->intc =3D obj; } =20 @@ -837,7 +843,10 @@ static void pnv_chip_power9_intc_reset(PnvChip *chip, = PowerPCCPU *cpu) =20 static void pnv_chip_power9_intc_destroy(PnvChip *chip, PowerPCCPU *cpu) { - xive_tctx_destroy(XIVE_TCTX(pnv_cpu_state(cpu)->intc)); + Object *intc =3D pnv_cpu_state(cpu)->intc; + + object_unref(intc); + xive_tctx_destroy(XIVE_TCTX(intc)); } =20 /* diff --git a/include/hw/ppc/xics.h b/include/hw/ppc/xics.h index 48a75aa4ab75..f4827e748fd8 100644 --- a/include/hw/ppc/xics.h +++ b/include/hw/ppc/xics.h @@ -179,7 +179,7 @@ void ics_pic_print_info(ICSState *ics, Monitor *mon); void ics_resend(ICSState *ics); void icp_resend(ICPState *ss); =20 -Object *icp_create(Object *cpu, const char *type, XICSFabric *xi, +Object *icp_create(Object *cpu, const char *type, ICSState *ics, XICSFabri= c *xi, Error **errp); void icp_destroy(ICPState *icp); =20 From nobody Thu May 2 18:31:14 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1571843267; cv=none; d=zoho.com; s=zohoarc; b=NYOBhxEdKRQmVU2gj8JfzIxBgZX1k6jHLfqT63f+5tN/LBh9XdRxXAGoL5wt+UEuTgCluFO8q8z0WbyPN6JvsFNuvLPBB8O0guvPUNdpNyIDGv3ntK11NEylsq+go4xkXvWqk9Svc60oNi74vyGUs6Owiuuome2b7PjQxBY3miI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1571843267; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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Violators will be prosecuted; (version=TLSv1/SSLv3 cipher=AES256-GCM-SHA384 bits=256/256) Wed, 23 Oct 2019 15:52:17 +0100 Received: from b06wcsmtp001.portsmouth.uk.ibm.com (b06wcsmtp001.portsmouth.uk.ibm.com [9.149.105.160]) by b06cxnps4074.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id x9NEqGln41746582 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Wed, 23 Oct 2019 14:52:16 GMT Received: from b06wcsmtp001.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id BA656A4060; Wed, 23 Oct 2019 14:52:16 +0000 (GMT) Received: from b06wcsmtp001.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 81BA9A4054; Wed, 23 Oct 2019 14:52:16 +0000 (GMT) Received: from bahia.lan (unknown [9.145.36.67]) by b06wcsmtp001.portsmouth.uk.ibm.com (Postfix) with ESMTP; Wed, 23 Oct 2019 14:52:16 +0000 (GMT) Subject: [PATCH 4/6] qom: Add object_child_foreach_type() helper function From: Greg Kurz To: David Gibson Date: Wed, 23 Oct 2019 16:52:16 +0200 In-Reply-To: <157184231371.3053790.17713393349394736594.stgit@bahia.lan> References: <157184231371.3053790.17713393349394736594.stgit@bahia.lan> User-Agent: StGit/unknown-version MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 x-cbid: 19102314-4275-0000-0000-000003763436 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 19102314-4276-0000-0000-000038895BDE Message-Id: <157184233616.3053790.246919545000657597.stgit@bahia.lan> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2019-10-23_03:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=0 phishscore=0 bulkscore=0 spamscore=0 clxscore=1034 lowpriorityscore=0 mlxscore=0 impostorscore=0 mlxlogscore=999 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1908290000 definitions=main-1910230148 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [generic] [fuzzy] X-Received-From: 148.163.158.5 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Paolo Bonzini , qemu-ppc@nongnu.org, =?utf-8?q?C=C3=A9dric?= Le Goater , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Calling a function for children of a certain type is a recurring pattern in the QEMU code base. In order to avoid the need to setup the same boiler plate again and again, introduce a variant of object_child_foreach() that only considers children of the given type. Signed-off-by: Greg Kurz Reviewed-by: David Gibson --- include/qom/object.h | 35 +++++++++++++++++++++++++++++++++++ qom/object.c | 30 +++++++++++++++++++++++------- 2 files changed, 58 insertions(+), 7 deletions(-) diff --git a/include/qom/object.h b/include/qom/object.h index 128d00c77fd6..e9e3c2eae8ed 100644 --- a/include/qom/object.h +++ b/include/qom/object.h @@ -1728,6 +1728,41 @@ int object_child_foreach(Object *obj, int (*fn)(Obje= ct *child, void *opaque), int object_child_foreach_recursive(Object *obj, int (*fn)(Object *child, void *opaque), void *opaque); + +/** + * object_child_foreach_type: + * @obj: the object whose children will be navigated + * @typename: the type of child objects to consider + * @fn: the iterator function to be called + * @opaque: an opaque value that will be passed to the iterator + * + * This is similar to object_child_foreach, but it only calls @fn for + * child objects of the give @typename. + * + * Returns: The last value returned by @fn, or 0 if there is no child of + * the given @typename. + */ +int object_child_foreach_type(Object *obj, const char *typename, + int (*fn)(Object *child, void *opaque), + void *opaque); + +/** + * object_child_foreach_recursive_type: + * @obj: the object whose children will be navigated + * @typename: the type of child objects to consider + * @fn: the iterator function to be called + * @opaque: an opaque value that will be passed to the iterator + * + * This is similar to object_child_foreach_recursive, but it only calls + * @fn for child objects of the give @typename. + * + * Returns: The last value returned by @fn, or 0 if there is no child of + * the given @typename. + */ +int object_child_foreach_recursive_type(Object *obj, const char *typename, + int (*fn)(Object *child, void *opa= que), + void *opaque); + /** * container_get: * @root: root of the #path, e.g., object_get_root() diff --git a/qom/object.c b/qom/object.c index 6fa9c619fac4..a2dec1261ff7 100644 --- a/qom/object.c +++ b/qom/object.c @@ -986,7 +986,7 @@ void object_class_foreach(void (*fn)(ObjectClass *klass= , void *opaque), enumerating_types =3D false; } =20 -static int do_object_child_foreach(Object *obj, +static int do_object_child_foreach(Object *obj, const char *typename, int (*fn)(Object *child, void *opaque), void *opaque, bool recurse) { @@ -999,12 +999,14 @@ static int do_object_child_foreach(Object *obj, if (object_property_is_child(prop)) { Object *child =3D prop->opaque; =20 - ret =3D fn(child, opaque); - if (ret !=3D 0) { - break; + if (!typename || object_dynamic_cast(child, typename)) { + ret =3D fn(child, opaque); + if (ret !=3D 0) { + break; + } } if (recurse) { - do_object_child_foreach(child, fn, opaque, true); + do_object_child_foreach(child, typename, fn, opaque, true); } } } @@ -1014,14 +1016,28 @@ static int do_object_child_foreach(Object *obj, int object_child_foreach(Object *obj, int (*fn)(Object *child, void *opaqu= e), void *opaque) { - return do_object_child_foreach(obj, fn, opaque, false); + return do_object_child_foreach(obj, NULL, fn, opaque, false); } =20 int object_child_foreach_recursive(Object *obj, int (*fn)(Object *child, void *opaque), void *opaque) { - return do_object_child_foreach(obj, fn, opaque, true); + return do_object_child_foreach(obj, NULL, fn, opaque, true); +} + +int object_child_foreach_type(Object *obj, const char *typename, + int (*fn)(Object *child, void *opaque), + void *opaque) +{ + return do_object_child_foreach(obj, typename, fn, opaque, false); +} + +int object_child_foreach_recursive_type(Object *obj, const char *typename, + int (*fn)(Object *child, void *opa= que), + void *opaque) +{ + return do_object_child_foreach(obj, typename, fn, opaque, true); } =20 static void object_class_get_list_tramp(ObjectClass *klass, void *opaque) From nobody Thu May 2 18:31:14 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1571842916; cv=none; d=zoho.com; s=zohoarc; b=XyyQLllUWWlDZHrpfettDxJD3Unfl3yFNiycPoNdqNPI62jmspDrO9gRMgPafgzmTLB0jLKWlpKd7vAqzP5lE9yYL2pXvEtQm1C7Aq801WI/uBGgNtjftAlU0ieXnKooJtUzu1qeigSXt2s2xbRDStY6YnLI+86SBdPOOtGDVH8= ARC-Message-Signature: i=1; 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Violators will be prosecuted; (version=TLSv1/SSLv3 cipher=AES256-GCM-SHA384 bits=256/256) Wed, 23 Oct 2019 15:52:23 +0100 Received: from d06av21.portsmouth.uk.ibm.com (d06av21.portsmouth.uk.ibm.com [9.149.105.232]) by b06cxnps3075.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id x9NEqMBW62521360 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Wed, 23 Oct 2019 14:52:22 GMT Received: from d06av21.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 4D0A25204F; Wed, 23 Oct 2019 14:52:22 +0000 (GMT) Received: from bahia.lan (unknown [9.145.36.67]) by d06av21.portsmouth.uk.ibm.com (Postfix) with ESMTP id 1583C5204E; Wed, 23 Oct 2019 14:52:22 +0000 (GMT) Subject: [PATCH 5/6] spapr: Don't use CPU_FOREACH() in 'info pic' From: Greg Kurz To: David Gibson Date: Wed, 23 Oct 2019 16:52:21 +0200 In-Reply-To: <157184231371.3053790.17713393349394736594.stgit@bahia.lan> References: <157184231371.3053790.17713393349394736594.stgit@bahia.lan> User-Agent: StGit/unknown-version MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 x-cbid: 19102314-0020-0000-0000-0000037D2E47 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 19102314-0021-0000-0000-000021D37080 Message-Id: <157184234176.3053790.8577967462603127139.stgit@bahia.lan> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2019-10-23_03:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=2 phishscore=0 bulkscore=0 spamscore=0 clxscore=1034 lowpriorityscore=0 mlxscore=0 impostorscore=0 mlxlogscore=400 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1908290000 definitions=main-1910230148 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [generic] [fuzzy] X-Received-From: 148.163.156.1 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Paolo Bonzini , qemu-ppc@nongnu.org, =?utf-8?q?C=C3=A9dric?= Le Goater , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Now that presenter objects are parented to the interrupt controller, stop relying on CPU_FOREACH() which can race with CPU hotplug and crash QEMU. Signed-off-by: Greg Kurz --- hw/intc/spapr_xive.c | 8 +------- hw/intc/xics.c | 12 ++++++++++++ hw/intc/xics_spapr.c | 8 +------- hw/intc/xive.c | 12 ++++++++++++ include/hw/ppc/xics.h | 1 + include/hw/ppc/xive.h | 2 ++ 6 files changed, 29 insertions(+), 14 deletions(-) diff --git a/hw/intc/spapr_xive.c b/hw/intc/spapr_xive.c index d74ee71e76b4..05763a58cf5d 100644 --- a/hw/intc/spapr_xive.c +++ b/hw/intc/spapr_xive.c @@ -579,14 +579,8 @@ static void spapr_xive_set_irq(SpaprInterruptControlle= r *intc, int irq, int val) static void spapr_xive_print_info(SpaprInterruptController *intc, Monitor = *mon) { SpaprXive *xive =3D SPAPR_XIVE(intc); - CPUState *cs; - - CPU_FOREACH(cs) { - PowerPCCPU *cpu =3D POWERPC_CPU(cs); - - xive_tctx_pic_print_info(spapr_cpu_state(cpu)->tctx, mon); - } =20 + xive_presenter_print_info(XIVE_ROUTER(intc), mon); spapr_xive_pic_print_info(xive, mon); } =20 diff --git a/hw/intc/xics.c b/hw/intc/xics.c index d5e4db668a4b..6e820c4851f3 100644 --- a/hw/intc/xics.c +++ b/hw/intc/xics.c @@ -88,6 +88,18 @@ void ics_pic_print_info(ICSState *ics, Monitor *mon) } } =20 +static int do_ics_pic_print_icp_infos(Object *child, void *opaque) +{ + icp_pic_print_info(ICP(child), opaque); + return 0; +} + +void ics_pic_print_icp_infos(ICSState *ics, const char *type, Monitor *mon) +{ + object_child_foreach_type(OBJECT(ics), type, do_ics_pic_print_icp_info= s, + mon); +} + /* * ICP: Presentation layer */ diff --git a/hw/intc/xics_spapr.c b/hw/intc/xics_spapr.c index 080ed73aad64..7624d693c8da 100644 --- a/hw/intc/xics_spapr.c +++ b/hw/intc/xics_spapr.c @@ -400,14 +400,8 @@ static void xics_spapr_set_irq(SpaprInterruptControlle= r *intc, int irq, int val) static void xics_spapr_print_info(SpaprInterruptController *intc, Monitor = *mon) { ICSState *ics =3D ICS_SPAPR(intc); - CPUState *cs; - - CPU_FOREACH(cs) { - PowerPCCPU *cpu =3D POWERPC_CPU(cs); - - icp_pic_print_info(spapr_cpu_state(cpu)->icp, mon); - } =20 + ics_pic_print_icp_infos(ics, TYPE_ICP, mon); ics_pic_print_info(ics, mon); } =20 diff --git a/hw/intc/xive.c b/hw/intc/xive.c index 8d2da4a11163..40ce43152456 100644 --- a/hw/intc/xive.c +++ b/hw/intc/xive.c @@ -547,6 +547,18 @@ void xive_tctx_pic_print_info(XiveTCTX *tctx, Monitor = *mon) } } =20 +static int do_xive_presenter_print_info(Object *child, void *opaque) +{ + xive_tctx_pic_print_info(XIVE_TCTX(child), opaque); + return 0; +} + +void xive_presenter_print_info(XiveRouter *xrtr, Monitor *mon) +{ + object_child_foreach_type(OBJECT(xrtr), TYPE_XIVE_TCTX, + do_xive_presenter_print_info, mon); +} + void xive_tctx_reset(XiveTCTX *tctx) { memset(tctx->regs, 0, sizeof(tctx->regs)); diff --git a/include/hw/ppc/xics.h b/include/hw/ppc/xics.h index f4827e748fd8..4de1f421c997 100644 --- a/include/hw/ppc/xics.h +++ b/include/hw/ppc/xics.h @@ -175,6 +175,7 @@ static inline bool ics_irq_free(ICSState *ics, uint32_t= srcno) void ics_set_irq_type(ICSState *ics, int srcno, bool lsi); void icp_pic_print_info(ICPState *icp, Monitor *mon); void ics_pic_print_info(ICSState *ics, Monitor *mon); +void ics_pic_print_icp_infos(ICSState *ics, const char *type, Monitor *mon= ); =20 void ics_resend(ICSState *ics); void icp_resend(ICPState *ss); diff --git a/include/hw/ppc/xive.h b/include/hw/ppc/xive.h index 8fd439ec9bba..14690428a0aa 100644 --- a/include/hw/ppc/xive.h +++ b/include/hw/ppc/xive.h @@ -367,6 +367,8 @@ int xive_router_write_nvt(XiveRouter *xrtr, uint8_t nvt= _blk, uint32_t nvt_idx, XiveTCTX *xive_router_get_tctx(XiveRouter *xrtr, CPUState *cs); void xive_router_notify(XiveNotifier *xn, uint32_t lisn); =20 +void xive_presenter_print_info(XiveRouter *xrtr, Monitor *mon); + /* * XIVE END ESBs */ From nobody Thu May 2 18:31:14 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1571843508; cv=none; d=zoho.com; s=zohoarc; b=YXc8AyJq08Ri1CM1lc5ee4iK19L0DOD+bGLZCHPvHmwRib1z/iLxlWBssw3xaNeI6W7B5dP3A0r3VPt6WNoJEi4rMwvkjcH8yqSRYCdudKJQhVWw7ns1PVdESaROjF4DCzn2ZMPfl4HrfnW8rCtm6QuLCbcibyURglUtrzf13ew= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1571843508; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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Violators will be prosecuted; (version=TLSv1/SSLv3 cipher=AES256-GCM-SHA384 bits=256/256) Wed, 23 Oct 2019 15:52:28 +0100 Received: from d06av22.portsmouth.uk.ibm.com (d06av22.portsmouth.uk.ibm.com [9.149.105.58]) by b06cxnps3075.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id x9NEqRtq58523898 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Wed, 23 Oct 2019 14:52:28 GMT Received: from d06av22.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id D2DB74C058; Wed, 23 Oct 2019 14:52:27 +0000 (GMT) Received: from d06av22.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id A422D4C04A; Wed, 23 Oct 2019 14:52:27 +0000 (GMT) Received: from bahia.lan (unknown [9.145.36.67]) by d06av22.portsmouth.uk.ibm.com (Postfix) with ESMTP; Wed, 23 Oct 2019 14:52:27 +0000 (GMT) Subject: [PATCH 6/6] xive: Don't use CPU_FOREACH() to perform CAM line matching From: Greg Kurz To: David Gibson Date: Wed, 23 Oct 2019 16:52:27 +0200 In-Reply-To: <157184231371.3053790.17713393349394736594.stgit@bahia.lan> References: <157184231371.3053790.17713393349394736594.stgit@bahia.lan> User-Agent: StGit/unknown-version MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 x-cbid: 19102314-4275-0000-0000-00000376343F X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 19102314-4276-0000-0000-000038895BE9 Message-Id: <157184234731.3053790.18369348907304339634.stgit@bahia.lan> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2019-10-23_03:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=0 phishscore=0 bulkscore=0 spamscore=0 clxscore=1034 lowpriorityscore=0 mlxscore=0 impostorscore=0 mlxlogscore=999 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1908290000 definitions=main-1910230148 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [generic] [fuzzy] X-Received-From: 148.163.156.1 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Paolo Bonzini , qemu-ppc@nongnu.org, =?utf-8?q?C=C3=A9dric?= Le Goater , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Now that the TCTX objects are children of the XIVE router, stop using CPU_FOREACH() when looking for a matching VCPU target. Signed-off-by: Greg Kurz --- hw/intc/xive.c | 100 +++++++++++++++++++++++++++++++++++-----------------= ---- 1 file changed, 62 insertions(+), 38 deletions(-) diff --git a/hw/intc/xive.c b/hw/intc/xive.c index 40ce43152456..ec5e7d0ee39a 100644 --- a/hw/intc/xive.c +++ b/hw/intc/xive.c @@ -1403,55 +1403,79 @@ typedef struct XiveTCTXMatch { uint8_t ring; } XiveTCTXMatch; =20 -static bool xive_presenter_match(XiveRouter *xrtr, uint8_t format, - uint8_t nvt_blk, uint32_t nvt_idx, - bool cam_ignore, uint8_t priority, - uint32_t logic_serv, XiveTCTXMatch *match) +typedef struct XivePresenterMatch { + uint8_t format; + uint8_t nvt_blk; + uint32_t nvt_idx; + bool cam_ignore; + uint8_t priority; + uint32_t logic_serv; + XiveTCTXMatch *match; + int count; +} XivePresenterMatch; + +static int do_xive_presenter_match(Object *child, void *opaque) { - CPUState *cs; + XiveTCTX *tctx =3D XIVE_TCTX(child); + XivePresenterMatch *xpm =3D opaque; + int ring; =20 /* * TODO (PowerNV): handle chip_id overwrite of block field for * hardwired CAM compares */ =20 - CPU_FOREACH(cs) { - XiveTCTX *tctx =3D xive_router_get_tctx(xrtr, cs); - int ring; + /* + * HW checks that the CPU is enabled in the Physical Thread + * Enable Register (PTER). + */ =20 - /* - * Skip partially initialized vCPUs. This can happen when - * vCPUs are hotplugged. - */ - if (!tctx) { - continue; + /* + * Check the thread context CAM lines and record matches. We + * will handle CPU exception delivery later + */ + ring =3D xive_presenter_tctx_match(tctx, xpm->format, xpm->nvt_blk, + xpm->nvt_idx, xpm->cam_ignore, + xpm->logic_serv); + + /* + * Save the context and follow on to catch duplicates, that we + * don't support yet. + */ + if (ring !=3D -1) { + if (xpm->match->tctx) { + qemu_log_mask(LOG_GUEST_ERROR, "XIVE: already found a thread " + "context NVT %x/%x\n", xpm->nvt_blk, xpm->nvt_id= x); + return -1; } =20 - /* - * HW checks that the CPU is enabled in the Physical Thread - * Enable Register (PTER). - */ + xpm->match->ring =3D ring; + xpm->match->tctx =3D tctx; + xpm->count++; + } =20 - /* - * Check the thread context CAM lines and record matches. We - * will handle CPU exception delivery later - */ - ring =3D xive_presenter_tctx_match(tctx, format, nvt_blk, nvt_idx, - cam_ignore, logic_serv); - /* - * Save the context and follow on to catch duplicates, that we - * don't support yet. - */ - if (ring !=3D -1) { - if (match->tctx) { - qemu_log_mask(LOG_GUEST_ERROR, "XIVE: already found a thre= ad " - "context NVT %x/%x\n", nvt_blk, nvt_idx); - return false; - } - - match->ring =3D ring; - match->tctx =3D tctx; - } + return 0; +} + +static bool xive_presenter_match(XiveRouter *xrtr, uint8_t format, + uint8_t nvt_blk, uint32_t nvt_idx, + bool cam_ignore, uint8_t priority, + uint32_t logic_serv, XiveTCTXMatch *match) +{ + XivePresenterMatch xpm =3D { + .format =3D format, + .nvt_blk =3D nvt_blk, + .nvt_idx =3D nvt_idx, + .cam_ignore =3D cam_ignore, + .priority =3D priority, + .logic_serv =3D logic_serv, + .match =3D match, + .count =3D 0, + }; + + if (object_child_foreach_type(OBJECT(xrtr), TYPE_XIVE_TCTX, + do_xive_presenter_match, &xpm) < 0) { + return false; } =20 if (!match->tctx) {