From nobody Tue Feb 10 07:42:36 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1570991661; cv=none; d=zoho.com; s=zohoarc; b=SnmHIqu+s6vyLtu+gOo9FgF3hvVpkVG9UnCmC0mXe3mkQpe3nEOCC5Ad6W16AJSMNJ0S6ViNB93JO/iTd59LJ01hlT7sOAt61dBHqyeM7wxJzw25lZyn2fnR0OHEKeF5aL4mkNS9yZ+y5CPr5TtkEOi4WVRx8byIKm/Xkcg3zw4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1570991661; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To; bh=lmOGaAkBP24Nh3qeT1wjqo+M8T/XTwGpKXNcrTneNS0=; b=Xq6C6zBGDcGJrhoNRGNfApYw5YTTI51Qt0hzVpDTQRDqNdcP5C2yogdrljn7rxgRrDTfMuhfkxzSMTuKvIMOIZ3zevg+7c/XfbFIovJ3yXVzCYPWSw621nwalM13rrNkDWZJeyts/X0fBWgTaawZdTtnZIB0sGnBq+JdmVuIp6U= ARC-Authentication-Results: i=1; mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1570991661796521.9254537616611; Sun, 13 Oct 2019 11:34:21 -0700 (PDT) Received: from localhost ([::1]:41460 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iJih8-0003Zk-GL for importer@patchew.org; Sun, 13 Oct 2019 14:34:18 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:54915) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iJiae-0006nW-8U for qemu-devel@nongnu.org; Sun, 13 Oct 2019 14:27:39 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iJiab-0003nE-74 for qemu-devel@nongnu.org; Sun, 13 Oct 2019 14:27:36 -0400 Received: from mx2.rt-rk.com ([89.216.37.149]:42402 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1iJiaa-0003kt-NJ for qemu-devel@nongnu.org; Sun, 13 Oct 2019 14:27:33 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id E573A1A0F16; Sun, 13 Oct 2019 20:26:25 +0200 (CEST) Received: from rtrkw774-lin.domain.local (rtrkw774-lin.domain.local [10.10.14.106]) by mail.rt-rk.com (Postfix) with ESMTPSA id 6C0F11A1E57; Sun, 13 Oct 2019 20:26:25 +0200 (CEST) X-Virus-Scanned: amavisd-new at rt-rk.com From: Aleksandar Markovic To: qemu-devel@nongnu.org Subject: [PATCH v4 7/8] target/mips: msa: Split helpers for ADD<_A|S_A|S_S|S_U|V>. Date: Sun, 13 Oct 2019 20:26:17 +0200 Message-Id: <1570991178-5511-8-git-send-email-aleksandar.markovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1570991178-5511-1-git-send-email-aleksandar.markovic@rt-rk.com> References: <1570991178-5511-1-git-send-email-aleksandar.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 89.216.37.149 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: aleksandar.rikalo@rt-rk.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Aleksandar Markovic Achieves clearer code and slightly better performance. Signed-off-by: Aleksandar Markovic --- target/mips/helper.h | 30 +++- target/mips/msa_helper.c | 426 +++++++++++++++++++++++++++++++++++++++++--= ---- target/mips/translate.c | 95 +++++++++-- 3 files changed, 482 insertions(+), 69 deletions(-) diff --git a/target/mips/helper.h b/target/mips/helper.h index f3df187..ce01e97 100644 --- a/target/mips/helper.h +++ b/target/mips/helper.h @@ -822,6 +822,31 @@ DEF_HELPER_4(msa_bset_h, void, env, i32, i32, i32) DEF_HELPER_4(msa_bset_w, void, env, i32, i32, i32) DEF_HELPER_4(msa_bset_d, void, env, i32, i32, i32) =20 +DEF_HELPER_4(msa_add_a_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_add_a_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_add_a_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_add_a_d, void, env, i32, i32, i32) + +DEF_HELPER_4(msa_adds_a_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_adds_a_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_adds_a_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_adds_a_d, void, env, i32, i32, i32) + +DEF_HELPER_4(msa_adds_s_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_adds_s_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_adds_s_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_adds_s_d, void, env, i32, i32, i32) + +DEF_HELPER_4(msa_adds_u_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_adds_u_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_adds_u_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_adds_u_d, void, env, i32, i32, i32) + +DEF_HELPER_4(msa_addv_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_addv_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_addv_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_addv_d, void, env, i32, i32, i32) + DEF_HELPER_4(msa_ave_s_b, void, env, i32, i32, i32) DEF_HELPER_4(msa_ave_s_h, void, env, i32, i32, i32) DEF_HELPER_4(msa_ave_s_w, void, env, i32, i32, i32) @@ -976,12 +1001,7 @@ DEF_HELPER_5(msa_sra_df, void, env, i32, i32, i32, i3= 2) DEF_HELPER_5(msa_srl_df, void, env, i32, i32, i32, i32) DEF_HELPER_5(msa_binsl_df, void, env, i32, i32, i32, i32) DEF_HELPER_5(msa_binsr_df, void, env, i32, i32, i32, i32) -DEF_HELPER_5(msa_addv_df, void, env, i32, i32, i32, i32) DEF_HELPER_5(msa_subv_df, void, env, i32, i32, i32, i32) -DEF_HELPER_5(msa_add_a_df, void, env, i32, i32, i32, i32) -DEF_HELPER_5(msa_adds_a_df, void, env, i32, i32, i32, i32) -DEF_HELPER_5(msa_adds_s_df, void, env, i32, i32, i32, i32) -DEF_HELPER_5(msa_adds_u_df, void, env, i32, i32, i32, i32) DEF_HELPER_5(msa_subs_s_df, void, env, i32, i32, i32, i32) DEF_HELPER_5(msa_subs_u_df, void, env, i32, i32, i32, i32) DEF_HELPER_5(msa_subsus_u_df, void, env, i32, i32, i32, i32) diff --git a/target/mips/msa_helper.c b/target/mips/msa_helper.c index 499fcde..c31f46c 100644 --- a/target/mips/msa_helper.c +++ b/target/mips/msa_helper.c @@ -805,7 +805,383 @@ void helper_msa_bset_d(CPUMIPSState *env, uint32_t wd= , uint32_t ws, uint32_t wt) * +---------------+------------------------------------------------------= ----+ */ =20 -/* TODO: insert Int Add group helpers here */ + +static inline int64_t msa_add_a_df(uint32_t df, int64_t arg1, int64_t arg2) +{ + uint64_t abs_arg1 =3D arg1 >=3D 0 ? arg1 : -arg1; + uint64_t abs_arg2 =3D arg2 >=3D 0 ? arg2 : -arg2; + return abs_arg1 + abs_arg2; +} + +void helper_msa_add_a_b(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); + + pwd->b[0] =3D msa_add_a_df(DF_BYTE, pws->b[0], pwt->b[0]); + pwd->b[1] =3D msa_add_a_df(DF_BYTE, pws->b[1], pwt->b[1]); + pwd->b[2] =3D msa_add_a_df(DF_BYTE, pws->b[2], pwt->b[2]); + pwd->b[3] =3D msa_add_a_df(DF_BYTE, pws->b[3], pwt->b[3]); + pwd->b[4] =3D msa_add_a_df(DF_BYTE, pws->b[4], pwt->b[4]); + pwd->b[5] =3D msa_add_a_df(DF_BYTE, pws->b[5], pwt->b[5]); + pwd->b[6] =3D msa_add_a_df(DF_BYTE, pws->b[6], pwt->b[6]); + pwd->b[7] =3D msa_add_a_df(DF_BYTE, pws->b[7], pwt->b[7]); + pwd->b[8] =3D msa_add_a_df(DF_BYTE, pws->b[8], pwt->b[8]); + pwd->b[9] =3D msa_add_a_df(DF_BYTE, pws->b[9], pwt->b[9]); + pwd->b[10] =3D msa_add_a_df(DF_BYTE, pws->b[10], pwt->b[10]); + pwd->b[11] =3D msa_add_a_df(DF_BYTE, pws->b[11], pwt->b[11]); + pwd->b[12] =3D msa_add_a_df(DF_BYTE, pws->b[12], pwt->b[12]); + pwd->b[13] =3D msa_add_a_df(DF_BYTE, pws->b[13], pwt->b[13]); + pwd->b[14] =3D msa_add_a_df(DF_BYTE, pws->b[14], pwt->b[14]); + pwd->b[15] =3D msa_add_a_df(DF_BYTE, pws->b[15], pwt->b[15]); +} + +void helper_msa_add_a_h(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); + + pwd->h[0] =3D msa_add_a_df(DF_HALF, pws->h[0], pwt->h[0]); + pwd->h[1] =3D msa_add_a_df(DF_HALF, pws->h[1], pwt->h[1]); + pwd->h[2] =3D msa_add_a_df(DF_HALF, pws->h[2], pwt->h[2]); + pwd->h[3] =3D msa_add_a_df(DF_HALF, pws->h[3], pwt->h[3]); + pwd->h[4] =3D msa_add_a_df(DF_HALF, pws->h[4], pwt->h[4]); + pwd->h[5] =3D msa_add_a_df(DF_HALF, pws->h[5], pwt->h[5]); + pwd->h[6] =3D msa_add_a_df(DF_HALF, pws->h[6], pwt->h[6]); + pwd->h[7] =3D msa_add_a_df(DF_HALF, pws->h[7], pwt->h[7]); +} + +void helper_msa_add_a_w(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); + + pwd->w[0] =3D msa_add_a_df(DF_WORD, pws->w[0], pwt->w[0]); + pwd->w[1] =3D msa_add_a_df(DF_WORD, pws->w[1], pwt->w[1]); + pwd->w[2] =3D msa_add_a_df(DF_WORD, pws->w[2], pwt->w[2]); + pwd->w[3] =3D msa_add_a_df(DF_WORD, pws->w[3], pwt->w[3]); +} + +void helper_msa_add_a_d(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); + + pwd->d[0] =3D msa_add_a_df(DF_DOUBLE, pws->d[0], pwt->d[0]); + pwd->d[1] =3D msa_add_a_df(DF_DOUBLE, pws->d[1], pwt->d[1]); +} + + +static inline int64_t msa_adds_a_df(uint32_t df, int64_t arg1, int64_t arg= 2) +{ + uint64_t max_int =3D (uint64_t)DF_MAX_INT(df); + uint64_t abs_arg1 =3D arg1 >=3D 0 ? arg1 : -arg1; + uint64_t abs_arg2 =3D arg2 >=3D 0 ? arg2 : -arg2; + if (abs_arg1 > max_int || abs_arg2 > max_int) { + return (int64_t)max_int; + } else { + return (abs_arg1 < max_int - abs_arg2) ? abs_arg1 + abs_arg2 : max= _int; + } +} + +void helper_msa_adds_a_b(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); + + pwd->b[0] =3D msa_adds_a_df(DF_BYTE, pws->b[0], pwt->b[0]); + pwd->b[1] =3D msa_adds_a_df(DF_BYTE, pws->b[1], pwt->b[1]); + pwd->b[2] =3D msa_adds_a_df(DF_BYTE, pws->b[2], pwt->b[2]); + pwd->b[3] =3D msa_adds_a_df(DF_BYTE, pws->b[3], pwt->b[3]); + pwd->b[4] =3D msa_adds_a_df(DF_BYTE, pws->b[4], pwt->b[4]); + pwd->b[5] =3D msa_adds_a_df(DF_BYTE, pws->b[5], pwt->b[5]); + pwd->b[6] =3D msa_adds_a_df(DF_BYTE, pws->b[6], pwt->b[6]); + pwd->b[7] =3D msa_adds_a_df(DF_BYTE, pws->b[7], pwt->b[7]); + pwd->b[8] =3D msa_adds_a_df(DF_BYTE, pws->b[8], pwt->b[8]); + pwd->b[9] =3D msa_adds_a_df(DF_BYTE, pws->b[9], pwt->b[9]); + pwd->b[10] =3D msa_adds_a_df(DF_BYTE, pws->b[10], pwt->b[10]); + pwd->b[11] =3D msa_adds_a_df(DF_BYTE, pws->b[11], pwt->b[11]); + pwd->b[12] =3D msa_adds_a_df(DF_BYTE, pws->b[12], pwt->b[12]); + pwd->b[13] =3D msa_adds_a_df(DF_BYTE, pws->b[13], pwt->b[13]); + pwd->b[14] =3D msa_adds_a_df(DF_BYTE, pws->b[14], pwt->b[14]); + pwd->b[15] =3D msa_adds_a_df(DF_BYTE, pws->b[15], pwt->b[15]); +} + +void helper_msa_adds_a_h(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); + + pwd->h[0] =3D msa_adds_a_df(DF_HALF, pws->h[0], pwt->h[0]); + pwd->h[1] =3D msa_adds_a_df(DF_HALF, pws->h[1], pwt->h[1]); + pwd->h[2] =3D msa_adds_a_df(DF_HALF, pws->h[2], pwt->h[2]); + pwd->h[3] =3D msa_adds_a_df(DF_HALF, pws->h[3], pwt->h[3]); + pwd->h[4] =3D msa_adds_a_df(DF_HALF, pws->h[4], pwt->h[4]); + pwd->h[5] =3D msa_adds_a_df(DF_HALF, pws->h[5], pwt->h[5]); + pwd->h[6] =3D msa_adds_a_df(DF_HALF, pws->h[6], pwt->h[6]); + pwd->h[7] =3D msa_adds_a_df(DF_HALF, pws->h[7], pwt->h[7]); +} + +void helper_msa_adds_a_w(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); + + pwd->w[0] =3D msa_adds_a_df(DF_WORD, pws->w[0], pwt->w[0]); + pwd->w[1] =3D msa_adds_a_df(DF_WORD, pws->w[1], pwt->w[1]); + pwd->w[2] =3D msa_adds_a_df(DF_WORD, pws->w[2], pwt->w[2]); + pwd->w[3] =3D msa_adds_a_df(DF_WORD, pws->w[3], pwt->w[3]); +} + +void helper_msa_adds_a_d(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); + + pwd->d[0] =3D msa_adds_a_df(DF_DOUBLE, pws->d[0], pwt->d[0]); + pwd->d[1] =3D msa_adds_a_df(DF_DOUBLE, pws->d[1], pwt->d[1]); +} + + +static inline int64_t msa_adds_s_df(uint32_t df, int64_t arg1, int64_t arg= 2) +{ + int64_t max_int =3D DF_MAX_INT(df); + int64_t min_int =3D DF_MIN_INT(df); + if (arg1 < 0) { + return (min_int - arg1 < arg2) ? arg1 + arg2 : min_int; + } else { + return (arg2 < max_int - arg1) ? arg1 + arg2 : max_int; + } +} + +void helper_msa_adds_s_b(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); + + pwd->b[0] =3D msa_adds_s_df(DF_BYTE, pws->b[0], pwt->b[0]); + pwd->b[1] =3D msa_adds_s_df(DF_BYTE, pws->b[1], pwt->b[1]); + pwd->b[2] =3D msa_adds_s_df(DF_BYTE, pws->b[2], pwt->b[2]); + pwd->b[3] =3D msa_adds_s_df(DF_BYTE, pws->b[3], pwt->b[3]); + pwd->b[4] =3D msa_adds_s_df(DF_BYTE, pws->b[4], pwt->b[4]); + pwd->b[5] =3D msa_adds_s_df(DF_BYTE, pws->b[5], pwt->b[5]); + pwd->b[6] =3D msa_adds_s_df(DF_BYTE, pws->b[6], pwt->b[6]); + pwd->b[7] =3D msa_adds_s_df(DF_BYTE, pws->b[7], pwt->b[7]); + pwd->b[8] =3D msa_adds_s_df(DF_BYTE, pws->b[8], pwt->b[8]); + pwd->b[9] =3D msa_adds_s_df(DF_BYTE, pws->b[9], pwt->b[9]); + pwd->b[10] =3D msa_adds_s_df(DF_BYTE, pws->b[10], pwt->b[10]); + pwd->b[11] =3D msa_adds_s_df(DF_BYTE, pws->b[11], pwt->b[11]); + pwd->b[12] =3D msa_adds_s_df(DF_BYTE, pws->b[12], pwt->b[12]); + pwd->b[13] =3D msa_adds_s_df(DF_BYTE, pws->b[13], pwt->b[13]); + pwd->b[14] =3D msa_adds_s_df(DF_BYTE, pws->b[14], pwt->b[14]); + pwd->b[15] =3D msa_adds_s_df(DF_BYTE, pws->b[15], pwt->b[15]); +} + +void helper_msa_adds_s_h(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); + + pwd->h[0] =3D msa_adds_s_df(DF_HALF, pws->h[0], pwt->h[0]); + pwd->h[1] =3D msa_adds_s_df(DF_HALF, pws->h[1], pwt->h[1]); + pwd->h[2] =3D msa_adds_s_df(DF_HALF, pws->h[2], pwt->h[2]); + pwd->h[3] =3D msa_adds_s_df(DF_HALF, pws->h[3], pwt->h[3]); + pwd->h[4] =3D msa_adds_s_df(DF_HALF, pws->h[4], pwt->h[4]); + pwd->h[5] =3D msa_adds_s_df(DF_HALF, pws->h[5], pwt->h[5]); + pwd->h[6] =3D msa_adds_s_df(DF_HALF, pws->h[6], pwt->h[6]); + pwd->h[7] =3D msa_adds_s_df(DF_HALF, pws->h[7], pwt->h[7]); +} + +void helper_msa_adds_s_w(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); + + pwd->w[0] =3D msa_adds_s_df(DF_WORD, pws->w[0], pwt->w[0]); + pwd->w[1] =3D msa_adds_s_df(DF_WORD, pws->w[1], pwt->w[1]); + pwd->w[2] =3D msa_adds_s_df(DF_WORD, pws->w[2], pwt->w[2]); + pwd->w[3] =3D msa_adds_s_df(DF_WORD, pws->w[3], pwt->w[3]); +} + +void helper_msa_adds_s_d(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); + + pwd->d[0] =3D msa_adds_s_df(DF_DOUBLE, pws->d[0], pwt->d[0]); + pwd->d[1] =3D msa_adds_s_df(DF_DOUBLE, pws->d[1], pwt->d[1]); +} + + +static inline uint64_t msa_adds_u_df(uint32_t df, uint64_t arg1, uint64_t = arg2) +{ + uint64_t max_uint =3D DF_MAX_UINT(df); + uint64_t u_arg1 =3D UNSIGNED(arg1, df); + uint64_t u_arg2 =3D UNSIGNED(arg2, df); + return (u_arg1 < max_uint - u_arg2) ? u_arg1 + u_arg2 : max_uint; +} + +void helper_msa_adds_u_b(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); + + pwd->b[0] =3D msa_adds_u_df(DF_BYTE, pws->b[0], pwt->b[0]); + pwd->b[1] =3D msa_adds_u_df(DF_BYTE, pws->b[1], pwt->b[1]); + pwd->b[2] =3D msa_adds_u_df(DF_BYTE, pws->b[2], pwt->b[2]); + pwd->b[3] =3D msa_adds_u_df(DF_BYTE, pws->b[3], pwt->b[3]); + pwd->b[4] =3D msa_adds_u_df(DF_BYTE, pws->b[4], pwt->b[4]); + pwd->b[5] =3D msa_adds_u_df(DF_BYTE, pws->b[5], pwt->b[5]); + pwd->b[6] =3D msa_adds_u_df(DF_BYTE, pws->b[6], pwt->b[6]); + pwd->b[7] =3D msa_adds_u_df(DF_BYTE, pws->b[7], pwt->b[7]); + pwd->b[8] =3D msa_adds_u_df(DF_BYTE, pws->b[8], pwt->b[8]); + pwd->b[9] =3D msa_adds_u_df(DF_BYTE, pws->b[9], pwt->b[9]); + pwd->b[10] =3D msa_adds_u_df(DF_BYTE, pws->b[10], pwt->b[10]); + pwd->b[11] =3D msa_adds_u_df(DF_BYTE, pws->b[11], pwt->b[11]); + pwd->b[12] =3D msa_adds_u_df(DF_BYTE, pws->b[12], pwt->b[12]); + pwd->b[13] =3D msa_adds_u_df(DF_BYTE, pws->b[13], pwt->b[13]); + pwd->b[14] =3D msa_adds_u_df(DF_BYTE, pws->b[14], pwt->b[14]); + pwd->b[15] =3D msa_adds_u_df(DF_BYTE, pws->b[15], pwt->b[15]); +} + +void helper_msa_adds_u_h(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); + + pwd->h[0] =3D msa_adds_u_df(DF_HALF, pws->h[0], pwt->h[0]); + pwd->h[1] =3D msa_adds_u_df(DF_HALF, pws->h[1], pwt->h[1]); + pwd->h[2] =3D msa_adds_u_df(DF_HALF, pws->h[2], pwt->h[2]); + pwd->h[3] =3D msa_adds_u_df(DF_HALF, pws->h[3], pwt->h[3]); + pwd->h[4] =3D msa_adds_u_df(DF_HALF, pws->h[4], pwt->h[4]); + pwd->h[5] =3D msa_adds_u_df(DF_HALF, pws->h[5], pwt->h[5]); + pwd->h[6] =3D msa_adds_u_df(DF_HALF, pws->h[6], pwt->h[6]); + pwd->h[7] =3D msa_adds_u_df(DF_HALF, pws->h[7], pwt->h[7]); +} + +void helper_msa_adds_u_w(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); + + pwd->w[0] =3D msa_adds_u_df(DF_WORD, pws->w[0], pwt->w[0]); + pwd->w[1] =3D msa_adds_u_df(DF_WORD, pws->w[1], pwt->w[1]); + pwd->w[2] =3D msa_adds_u_df(DF_WORD, pws->w[2], pwt->w[2]); + pwd->w[3] =3D msa_adds_u_df(DF_WORD, pws->w[3], pwt->w[3]); +} + +void helper_msa_adds_u_d(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); + + pwd->d[0] =3D msa_adds_u_df(DF_DOUBLE, pws->d[0], pwt->d[0]); + pwd->d[1] =3D msa_adds_u_df(DF_DOUBLE, pws->d[1], pwt->d[1]); +} + + +static inline int64_t msa_addv_df(uint32_t df, int64_t arg1, int64_t arg2) +{ + return arg1 + arg2; +} + +void helper_msa_addv_b(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); + + pwd->b[0] =3D msa_addv_df(DF_BYTE, pws->b[0], pwt->b[0]); + pwd->b[1] =3D msa_addv_df(DF_BYTE, pws->b[1], pwt->b[1]); + pwd->b[2] =3D msa_addv_df(DF_BYTE, pws->b[2], pwt->b[2]); + pwd->b[3] =3D msa_addv_df(DF_BYTE, pws->b[3], pwt->b[3]); + pwd->b[4] =3D msa_addv_df(DF_BYTE, pws->b[4], pwt->b[4]); + pwd->b[5] =3D msa_addv_df(DF_BYTE, pws->b[5], pwt->b[5]); + pwd->b[6] =3D msa_addv_df(DF_BYTE, pws->b[6], pwt->b[6]); + pwd->b[7] =3D msa_addv_df(DF_BYTE, pws->b[7], pwt->b[7]); + pwd->b[8] =3D msa_addv_df(DF_BYTE, pws->b[8], pwt->b[8]); + pwd->b[9] =3D msa_addv_df(DF_BYTE, pws->b[9], pwt->b[9]); + pwd->b[10] =3D msa_addv_df(DF_BYTE, pws->b[10], pwt->b[10]); + pwd->b[11] =3D msa_addv_df(DF_BYTE, pws->b[11], pwt->b[11]); + pwd->b[12] =3D msa_addv_df(DF_BYTE, pws->b[12], pwt->b[12]); + pwd->b[13] =3D msa_addv_df(DF_BYTE, pws->b[13], pwt->b[13]); + pwd->b[14] =3D msa_addv_df(DF_BYTE, pws->b[14], pwt->b[14]); + pwd->b[15] =3D msa_addv_df(DF_BYTE, pws->b[15], pwt->b[15]); +} + +void helper_msa_addv_h(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); + + pwd->h[0] =3D msa_addv_df(DF_HALF, pws->h[0], pwt->h[0]); + pwd->h[1] =3D msa_addv_df(DF_HALF, pws->h[1], pwt->h[1]); + pwd->h[2] =3D msa_addv_df(DF_HALF, pws->h[2], pwt->h[2]); + pwd->h[3] =3D msa_addv_df(DF_HALF, pws->h[3], pwt->h[3]); + pwd->h[4] =3D msa_addv_df(DF_HALF, pws->h[4], pwt->h[4]); + pwd->h[5] =3D msa_addv_df(DF_HALF, pws->h[5], pwt->h[5]); + pwd->h[6] =3D msa_addv_df(DF_HALF, pws->h[6], pwt->h[6]); + pwd->h[7] =3D msa_addv_df(DF_HALF, pws->h[7], pwt->h[7]); +} + +void helper_msa_addv_w(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); + + pwd->w[0] =3D msa_addv_df(DF_WORD, pws->w[0], pwt->w[0]); + pwd->w[1] =3D msa_addv_df(DF_WORD, pws->w[1], pwt->w[1]); + pwd->w[2] =3D msa_addv_df(DF_WORD, pws->w[2], pwt->w[2]); + pwd->w[3] =3D msa_addv_df(DF_WORD, pws->w[3], pwt->w[3]); +} + +void helper_msa_addv_d(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); + + pwd->d[0] =3D msa_addv_df(DF_DOUBLE, pws->d[0], pwt->d[0]); + pwd->d[1] =3D msa_addv_df(DF_DOUBLE, pws->d[1], pwt->d[1]); +} =20 =20 /* @@ -3050,11 +3426,6 @@ void helper_msa_shf_df(CPUMIPSState *env, uint32_t d= f, uint32_t wd, msa_move_v(pwd, pwx); } =20 -static inline int64_t msa_addv_df(uint32_t df, int64_t arg1, int64_t arg2) -{ - return arg1 + arg2; -} - static inline int64_t msa_subv_df(uint32_t df, int64_t arg1, int64_t arg2) { return arg1 - arg2; @@ -3283,44 +3654,6 @@ MSA_TEROP_IMMU_DF(binsli, binsl) MSA_TEROP_IMMU_DF(binsri, binsr) #undef MSA_TEROP_IMMU_DF =20 -static inline int64_t msa_add_a_df(uint32_t df, int64_t arg1, int64_t arg2) -{ - uint64_t abs_arg1 =3D arg1 >=3D 0 ? arg1 : -arg1; - uint64_t abs_arg2 =3D arg2 >=3D 0 ? arg2 : -arg2; - return abs_arg1 + abs_arg2; -} - -static inline int64_t msa_adds_a_df(uint32_t df, int64_t arg1, int64_t arg= 2) -{ - uint64_t max_int =3D (uint64_t)DF_MAX_INT(df); - uint64_t abs_arg1 =3D arg1 >=3D 0 ? arg1 : -arg1; - uint64_t abs_arg2 =3D arg2 >=3D 0 ? arg2 : -arg2; - if (abs_arg1 > max_int || abs_arg2 > max_int) { - return (int64_t)max_int; - } else { - return (abs_arg1 < max_int - abs_arg2) ? abs_arg1 + abs_arg2 : max= _int; - } -} - -static inline int64_t msa_adds_s_df(uint32_t df, int64_t arg1, int64_t arg= 2) -{ - int64_t max_int =3D DF_MAX_INT(df); - int64_t min_int =3D DF_MIN_INT(df); - if (arg1 < 0) { - return (min_int - arg1 < arg2) ? arg1 + arg2 : min_int; - } else { - return (arg2 < max_int - arg1) ? arg1 + arg2 : max_int; - } -} - -static inline uint64_t msa_adds_u_df(uint32_t df, uint64_t arg1, uint64_t = arg2) -{ - uint64_t max_uint =3D DF_MAX_UINT(df); - uint64_t u_arg1 =3D UNSIGNED(arg1, df); - uint64_t u_arg2 =3D UNSIGNED(arg2, df); - return (u_arg1 < max_uint - u_arg2) ? u_arg1 + u_arg2 : max_uint; -} - static inline int64_t msa_subs_s_df(uint32_t df, int64_t arg1, int64_t arg= 2) { int64_t max_int =3D DF_MAX_INT(df); @@ -3580,12 +3913,7 @@ void helper_msa_ ## func ## _df(CPUMIPSState *env, u= int32_t df, \ MSA_BINOP_DF(sll) MSA_BINOP_DF(sra) MSA_BINOP_DF(srl) -MSA_BINOP_DF(addv) MSA_BINOP_DF(subv) -MSA_BINOP_DF(add_a) -MSA_BINOP_DF(adds_a) -MSA_BINOP_DF(adds_s) -MSA_BINOP_DF(adds_u) MSA_BINOP_DF(subs_s) MSA_BINOP_DF(subs_u) MSA_BINOP_DF(subsus_u) diff --git a/target/mips/translate.c b/target/mips/translate.c index ea8b8f4..14f9891 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -28466,6 +28466,86 @@ static void gen_msa_3r(CPUMIPSState *env, DisasCon= text *ctx) break; } break; + case OPC_ADD_A_df: + switch (df) { + case DF_BYTE: + gen_helper_msa_add_a_b(cpu_env, twd, tws, twt); + break; + case DF_HALF: + gen_helper_msa_add_a_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_add_a_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_add_a_d(cpu_env, twd, tws, twt); + break; + } + break; + case OPC_ADDS_A_df: + switch (df) { + case DF_BYTE: + gen_helper_msa_adds_a_b(cpu_env, twd, tws, twt); + break; + case DF_HALF: + gen_helper_msa_adds_a_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_adds_a_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_adds_a_d(cpu_env, twd, tws, twt); + break; + } + break; + case OPC_ADDS_S_df: + switch (df) { + case DF_BYTE: + gen_helper_msa_adds_s_b(cpu_env, twd, tws, twt); + break; + case DF_HALF: + gen_helper_msa_adds_s_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_adds_s_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_adds_s_d(cpu_env, twd, tws, twt); + break; + } + break; + case OPC_ADDS_U_df: + switch (df) { + case DF_BYTE: + gen_helper_msa_adds_u_b(cpu_env, twd, tws, twt); + break; + case DF_HALF: + gen_helper_msa_adds_u_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_adds_u_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_adds_u_d(cpu_env, twd, tws, twt); + break; + } + break; + case OPC_ADDV_df: + switch (df) { + case DF_BYTE: + gen_helper_msa_addv_b(cpu_env, twd, tws, twt); + break; + case DF_HALF: + gen_helper_msa_addv_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_addv_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_addv_d(cpu_env, twd, tws, twt); + break; + } + break; case OPC_AVE_S_df: switch (df) { case DF_BYTE: @@ -28837,12 +28917,6 @@ static void gen_msa_3r(CPUMIPSState *env, DisasCon= text *ctx) case OPC_SLL_df: gen_helper_msa_sll_df(cpu_env, tdf, twd, tws, twt); break; - case OPC_ADDV_df: - gen_helper_msa_addv_df(cpu_env, tdf, twd, tws, twt); - break; - case OPC_ADD_A_df: - gen_helper_msa_add_a_df(cpu_env, tdf, twd, tws, twt); - break; case OPC_SUBS_S_df: gen_helper_msa_subs_s_df(cpu_env, tdf, twd, tws, twt); break; @@ -28861,9 +28935,6 @@ static void gen_msa_3r(CPUMIPSState *env, DisasCont= ext *ctx) case OPC_SUBV_df: gen_helper_msa_subv_df(cpu_env, tdf, twd, tws, twt); break; - case OPC_ADDS_A_df: - gen_helper_msa_adds_a_df(cpu_env, tdf, twd, tws, twt); - break; case OPC_SUBS_U_df: gen_helper_msa_subs_u_df(cpu_env, tdf, twd, tws, twt); break; @@ -28879,9 +28950,6 @@ static void gen_msa_3r(CPUMIPSState *env, DisasCont= ext *ctx) case OPC_SRL_df: gen_helper_msa_srl_df(cpu_env, tdf, twd, tws, twt); break; - case OPC_ADDS_S_df: - gen_helper_msa_adds_s_df(cpu_env, tdf, twd, tws, twt); - break; case OPC_SUBSUS_U_df: gen_helper_msa_subsus_u_df(cpu_env, tdf, twd, tws, twt); break; @@ -28894,9 +28962,6 @@ static void gen_msa_3r(CPUMIPSState *env, DisasCont= ext *ctx) case OPC_SRLR_df: gen_helper_msa_srlr_df(cpu_env, tdf, twd, tws, twt); break; - case OPC_ADDS_U_df: - gen_helper_msa_adds_u_df(cpu_env, tdf, twd, tws, twt); - break; case OPC_SUBSUU_S_df: gen_helper_msa_subsuu_s_df(cpu_env, tdf, twd, tws, twt); break; --=20 2.7.4