From nobody Tue Feb 10 11:34:24 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1570991643; cv=none; d=zoho.com; s=zohoarc; b=OPiD+CiOR38p3G9/t43P+foC67KbTYAcHFhfPpG3f3Eyq5fh8/LnQmu7pzjBKqe005P7aReYTtTrOVZJZgBoHkVRiKfiDzi6vERJxyj8/8YDeZjTqcVSvDg5IrG3wh8/FPR5AasViOe+nHcT6sDrEoNp4p7AMj6toghhtk0TzPQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1570991643; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To; bh=BmFVApihcE6rpnhqwKlbU4WJ4ERkfrHTlR3RdA5qPHM=; b=JNok3I0n4KPhmVjaUCCf91SMUiB0N2JzNSRH/ZEtS0jbGDpwHxBlKf1oaMoQNvvXpwEDXHIEolEF2Z2hzZ145SBmeiHVdI0DDbSIfAB2NpUAOTOnT3nL/SJR5KmLy+27UxoFBh333JtAIeeGf0kTPgdWnOwnMjv8valMSnbhX5E= ARC-Authentication-Results: i=1; mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1570991643421776.5627375359777; Sun, 13 Oct 2019 11:34:03 -0700 (PDT) Received: from localhost ([::1]:41458 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iJigr-0003Vw-OQ for importer@patchew.org; Sun, 13 Oct 2019 14:34:01 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:54881) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iJiac-0006mz-N8 for qemu-devel@nongnu.org; Sun, 13 Oct 2019 14:27:37 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iJiaZ-0003kn-Q6 for qemu-devel@nongnu.org; Sun, 13 Oct 2019 14:27:34 -0400 Received: from mx2.rt-rk.com ([89.216.37.149]:40799 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1iJiaZ-0002WI-9r for qemu-devel@nongnu.org; Sun, 13 Oct 2019 14:27:31 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id A48431A1E9F; Sun, 13 Oct 2019 20:26:25 +0200 (CEST) Received: from rtrkw774-lin.domain.local (rtrkw774-lin.domain.local [10.10.14.106]) by mail.rt-rk.com (Postfix) with ESMTPSA id 3DCE21A1E2D; Sun, 13 Oct 2019 20:26:25 +0200 (CEST) X-Virus-Scanned: amavisd-new at rt-rk.com From: Aleksandar Markovic To: qemu-devel@nongnu.org Subject: [PATCH v4 5/8] target/mips: msa: Split helpers for _. Date: Sun, 13 Oct 2019 20:26:15 +0200 Message-Id: <1570991178-5511-6-git-send-email-aleksandar.markovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1570991178-5511-1-git-send-email-aleksandar.markovic@rt-rk.com> References: <1570991178-5511-1-git-send-email-aleksandar.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 89.216.37.149 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: aleksandar.rikalo@rt-rk.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Aleksandar Markovic Achieves clearer code and slightly better performance. Signed-off-by: Aleksandar Markovic --- target/mips/helper.h | 20 ++- target/mips/msa_helper.c | 320 ++++++++++++++++++++++++++++++++++++++++++-= ---- target/mips/translate.c | 76 +++++++++-- 3 files changed, 372 insertions(+), 44 deletions(-) diff --git a/target/mips/helper.h b/target/mips/helper.h index cef4de6..6419bb8 100644 --- a/target/mips/helper.h +++ b/target/mips/helper.h @@ -881,10 +881,26 @@ DEF_HELPER_4(msa_max_a_b, void, env, i32, i32, i32) DEF_HELPER_4(msa_max_a_h, void, env, i32, i32, i32) DEF_HELPER_4(msa_max_a_w, void, env, i32, i32, i32) DEF_HELPER_4(msa_max_a_d, void, env, i32, i32, i32) +DEF_HELPER_4(msa_max_s_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_max_s_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_max_s_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_max_s_d, void, env, i32, i32, i32) +DEF_HELPER_4(msa_max_u_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_max_u_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_max_u_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_max_u_d, void, env, i32, i32, i32) DEF_HELPER_4(msa_min_a_b, void, env, i32, i32, i32) DEF_HELPER_4(msa_min_a_h, void, env, i32, i32, i32) DEF_HELPER_4(msa_min_a_w, void, env, i32, i32, i32) DEF_HELPER_4(msa_min_a_d, void, env, i32, i32, i32) +DEF_HELPER_4(msa_min_s_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_min_s_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_min_s_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_min_s_d, void, env, i32, i32, i32) +DEF_HELPER_4(msa_min_u_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_min_u_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_min_u_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_min_u_d, void, env, i32, i32, i32) =20 DEF_HELPER_4(msa_mod_u_b, void, env, i32, i32, i32) DEF_HELPER_4(msa_mod_u_h, void, env, i32, i32, i32) @@ -945,10 +961,6 @@ DEF_HELPER_5(msa_binsl_df, void, env, i32, i32, i32, i= 32) DEF_HELPER_5(msa_binsr_df, void, env, i32, i32, i32, i32) DEF_HELPER_5(msa_addv_df, void, env, i32, i32, i32, i32) DEF_HELPER_5(msa_subv_df, void, env, i32, i32, i32, i32) -DEF_HELPER_5(msa_max_s_df, void, env, i32, i32, i32, i32) -DEF_HELPER_5(msa_max_u_df, void, env, i32, i32, i32, i32) -DEF_HELPER_5(msa_min_s_df, void, env, i32, i32, i32, i32) -DEF_HELPER_5(msa_min_u_df, void, env, i32, i32, i32, i32) DEF_HELPER_5(msa_add_a_df, void, env, i32, i32, i32, i32) DEF_HELPER_5(msa_adds_a_df, void, env, i32, i32, i32, i32) DEF_HELPER_5(msa_adds_s_df, void, env, i32, i32, i32, i32) diff --git a/target/mips/msa_helper.c b/target/mips/msa_helper.c index 3eb0ab1..65df15d 100644 --- a/target/mips/msa_helper.c +++ b/target/mips/msa_helper.c @@ -1810,6 +1810,152 @@ void helper_msa_max_a_d(CPUMIPSState *env, } =20 =20 +static inline int64_t msa_max_s_df(uint32_t df, int64_t arg1, int64_t arg2) +{ + return arg1 > arg2 ? arg1 : arg2; +} + +void helper_msa_max_s_b(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); + + pwd->b[0] =3D msa_max_s_df(DF_BYTE, pws->b[0], pwt->b[0]); + pwd->b[1] =3D msa_max_s_df(DF_BYTE, pws->b[1], pwt->b[1]); + pwd->b[2] =3D msa_max_s_df(DF_BYTE, pws->b[2], pwt->b[2]); + pwd->b[3] =3D msa_max_s_df(DF_BYTE, pws->b[3], pwt->b[3]); + pwd->b[4] =3D msa_max_s_df(DF_BYTE, pws->b[4], pwt->b[4]); + pwd->b[5] =3D msa_max_s_df(DF_BYTE, pws->b[5], pwt->b[5]); + pwd->b[6] =3D msa_max_s_df(DF_BYTE, pws->b[6], pwt->b[6]); + pwd->b[7] =3D msa_max_s_df(DF_BYTE, pws->b[7], pwt->b[7]); + pwd->b[8] =3D msa_max_s_df(DF_BYTE, pws->b[8], pwt->b[8]); + pwd->b[9] =3D msa_max_s_df(DF_BYTE, pws->b[9], pwt->b[9]); + pwd->b[10] =3D msa_max_s_df(DF_BYTE, pws->b[10], pwt->b[10]); + pwd->b[11] =3D msa_max_s_df(DF_BYTE, pws->b[11], pwt->b[11]); + pwd->b[12] =3D msa_max_s_df(DF_BYTE, pws->b[12], pwt->b[12]); + pwd->b[13] =3D msa_max_s_df(DF_BYTE, pws->b[13], pwt->b[13]); + pwd->b[14] =3D msa_max_s_df(DF_BYTE, pws->b[14], pwt->b[14]); + pwd->b[15] =3D msa_max_s_df(DF_BYTE, pws->b[15], pwt->b[15]); +} + +void helper_msa_max_s_h(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); + + pwd->h[0] =3D msa_max_s_df(DF_HALF, pws->h[0], pwt->h[0]); + pwd->h[1] =3D msa_max_s_df(DF_HALF, pws->h[1], pwt->h[1]); + pwd->h[2] =3D msa_max_s_df(DF_HALF, pws->h[2], pwt->h[2]); + pwd->h[3] =3D msa_max_s_df(DF_HALF, pws->h[3], pwt->h[3]); + pwd->h[4] =3D msa_max_s_df(DF_HALF, pws->h[4], pwt->h[4]); + pwd->h[5] =3D msa_max_s_df(DF_HALF, pws->h[5], pwt->h[5]); + pwd->h[6] =3D msa_max_s_df(DF_HALF, pws->h[6], pwt->h[6]); + pwd->h[7] =3D msa_max_s_df(DF_HALF, pws->h[7], pwt->h[7]); +} + +void helper_msa_max_s_w(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); + + pwd->w[0] =3D msa_max_s_df(DF_WORD, pws->w[0], pwt->w[0]); + pwd->w[1] =3D msa_max_s_df(DF_WORD, pws->w[1], pwt->w[1]); + pwd->w[2] =3D msa_max_s_df(DF_WORD, pws->w[2], pwt->w[2]); + pwd->w[3] =3D msa_max_s_df(DF_WORD, pws->w[3], pwt->w[3]); +} + +void helper_msa_max_s_d(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); + + pwd->d[0] =3D msa_max_s_df(DF_DOUBLE, pws->d[0], pwt->d[0]); + pwd->d[1] =3D msa_max_s_df(DF_DOUBLE, pws->d[1], pwt->d[1]); +} + + +static inline int64_t msa_max_u_df(uint32_t df, int64_t arg1, int64_t arg2) +{ + uint64_t u_arg1 =3D UNSIGNED(arg1, df); + uint64_t u_arg2 =3D UNSIGNED(arg2, df); + return u_arg1 > u_arg2 ? arg1 : arg2; +} + +void helper_msa_max_u_b(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); + + pwd->b[0] =3D msa_max_u_df(DF_BYTE, pws->b[0], pwt->b[0]); + pwd->b[1] =3D msa_max_u_df(DF_BYTE, pws->b[1], pwt->b[1]); + pwd->b[2] =3D msa_max_u_df(DF_BYTE, pws->b[2], pwt->b[2]); + pwd->b[3] =3D msa_max_u_df(DF_BYTE, pws->b[3], pwt->b[3]); + pwd->b[4] =3D msa_max_u_df(DF_BYTE, pws->b[4], pwt->b[4]); + pwd->b[5] =3D msa_max_u_df(DF_BYTE, pws->b[5], pwt->b[5]); + pwd->b[6] =3D msa_max_u_df(DF_BYTE, pws->b[6], pwt->b[6]); + pwd->b[7] =3D msa_max_u_df(DF_BYTE, pws->b[7], pwt->b[7]); + pwd->b[8] =3D msa_max_u_df(DF_BYTE, pws->b[8], pwt->b[8]); + pwd->b[9] =3D msa_max_u_df(DF_BYTE, pws->b[9], pwt->b[9]); + pwd->b[10] =3D msa_max_u_df(DF_BYTE, pws->b[10], pwt->b[10]); + pwd->b[11] =3D msa_max_u_df(DF_BYTE, pws->b[11], pwt->b[11]); + pwd->b[12] =3D msa_max_u_df(DF_BYTE, pws->b[12], pwt->b[12]); + pwd->b[13] =3D msa_max_u_df(DF_BYTE, pws->b[13], pwt->b[13]); + pwd->b[14] =3D msa_max_u_df(DF_BYTE, pws->b[14], pwt->b[14]); + pwd->b[15] =3D msa_max_u_df(DF_BYTE, pws->b[15], pwt->b[15]); +} + +void helper_msa_max_u_h(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); + + pwd->h[0] =3D msa_max_u_df(DF_HALF, pws->h[0], pwt->h[0]); + pwd->h[1] =3D msa_max_u_df(DF_HALF, pws->h[1], pwt->h[1]); + pwd->h[2] =3D msa_max_u_df(DF_HALF, pws->h[2], pwt->h[2]); + pwd->h[3] =3D msa_max_u_df(DF_HALF, pws->h[3], pwt->h[3]); + pwd->h[4] =3D msa_max_u_df(DF_HALF, pws->h[4], pwt->h[4]); + pwd->h[5] =3D msa_max_u_df(DF_HALF, pws->h[5], pwt->h[5]); + pwd->h[6] =3D msa_max_u_df(DF_HALF, pws->h[6], pwt->h[6]); + pwd->h[7] =3D msa_max_u_df(DF_HALF, pws->h[7], pwt->h[7]); +} + +void helper_msa_max_u_w(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); + + pwd->w[0] =3D msa_max_u_df(DF_WORD, pws->w[0], pwt->w[0]); + pwd->w[1] =3D msa_max_u_df(DF_WORD, pws->w[1], pwt->w[1]); + pwd->w[2] =3D msa_max_u_df(DF_WORD, pws->w[2], pwt->w[2]); + pwd->w[3] =3D msa_max_u_df(DF_WORD, pws->w[3], pwt->w[3]); +} + +void helper_msa_max_u_d(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); + + pwd->d[0] =3D msa_max_u_df(DF_DOUBLE, pws->d[0], pwt->d[0]); + pwd->d[1] =3D msa_max_u_df(DF_DOUBLE, pws->d[1], pwt->d[1]); +} + + static inline int64_t msa_min_a_df(uint32_t df, int64_t arg1, int64_t arg2) { uint64_t abs_arg1 =3D arg1 >=3D 0 ? arg1 : -arg1; @@ -1884,6 +2030,152 @@ void helper_msa_min_a_d(CPUMIPSState *env, } =20 =20 +static inline int64_t msa_min_s_df(uint32_t df, int64_t arg1, int64_t arg2) +{ + return arg1 < arg2 ? arg1 : arg2; +} + +void helper_msa_min_s_b(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); + + pwd->b[0] =3D msa_min_s_df(DF_BYTE, pws->b[0], pwt->b[0]); + pwd->b[1] =3D msa_min_s_df(DF_BYTE, pws->b[1], pwt->b[1]); + pwd->b[2] =3D msa_min_s_df(DF_BYTE, pws->b[2], pwt->b[2]); + pwd->b[3] =3D msa_min_s_df(DF_BYTE, pws->b[3], pwt->b[3]); + pwd->b[4] =3D msa_min_s_df(DF_BYTE, pws->b[4], pwt->b[4]); + pwd->b[5] =3D msa_min_s_df(DF_BYTE, pws->b[5], pwt->b[5]); + pwd->b[6] =3D msa_min_s_df(DF_BYTE, pws->b[6], pwt->b[6]); + pwd->b[7] =3D msa_min_s_df(DF_BYTE, pws->b[7], pwt->b[7]); + pwd->b[8] =3D msa_min_s_df(DF_BYTE, pws->b[8], pwt->b[8]); + pwd->b[9] =3D msa_min_s_df(DF_BYTE, pws->b[9], pwt->b[9]); + pwd->b[10] =3D msa_min_s_df(DF_BYTE, pws->b[10], pwt->b[10]); + pwd->b[11] =3D msa_min_s_df(DF_BYTE, pws->b[11], pwt->b[11]); + pwd->b[12] =3D msa_min_s_df(DF_BYTE, pws->b[12], pwt->b[12]); + pwd->b[13] =3D msa_min_s_df(DF_BYTE, pws->b[13], pwt->b[13]); + pwd->b[14] =3D msa_min_s_df(DF_BYTE, pws->b[14], pwt->b[14]); + pwd->b[15] =3D msa_min_s_df(DF_BYTE, pws->b[15], pwt->b[15]); +} + +void helper_msa_min_s_h(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); + + pwd->h[0] =3D msa_min_s_df(DF_HALF, pws->h[0], pwt->h[0]); + pwd->h[1] =3D msa_min_s_df(DF_HALF, pws->h[1], pwt->h[1]); + pwd->h[2] =3D msa_min_s_df(DF_HALF, pws->h[2], pwt->h[2]); + pwd->h[3] =3D msa_min_s_df(DF_HALF, pws->h[3], pwt->h[3]); + pwd->h[4] =3D msa_min_s_df(DF_HALF, pws->h[4], pwt->h[4]); + pwd->h[5] =3D msa_min_s_df(DF_HALF, pws->h[5], pwt->h[5]); + pwd->h[6] =3D msa_min_s_df(DF_HALF, pws->h[6], pwt->h[6]); + pwd->h[7] =3D msa_min_s_df(DF_HALF, pws->h[7], pwt->h[7]); +} + +void helper_msa_min_s_w(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); + + pwd->w[0] =3D msa_min_s_df(DF_WORD, pws->w[0], pwt->w[0]); + pwd->w[1] =3D msa_min_s_df(DF_WORD, pws->w[1], pwt->w[1]); + pwd->w[2] =3D msa_min_s_df(DF_WORD, pws->w[2], pwt->w[2]); + pwd->w[3] =3D msa_min_s_df(DF_WORD, pws->w[3], pwt->w[3]); +} + +void helper_msa_min_s_d(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); + + pwd->d[0] =3D msa_min_s_df(DF_DOUBLE, pws->d[0], pwt->d[0]); + pwd->d[1] =3D msa_min_s_df(DF_DOUBLE, pws->d[1], pwt->d[1]); +} + + +static inline int64_t msa_min_u_df(uint32_t df, int64_t arg1, int64_t arg2) +{ + uint64_t u_arg1 =3D UNSIGNED(arg1, df); + uint64_t u_arg2 =3D UNSIGNED(arg2, df); + return u_arg1 < u_arg2 ? arg1 : arg2; +} + +void helper_msa_min_u_b(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); + + pwd->b[0] =3D msa_min_u_df(DF_BYTE, pws->b[0], pwt->b[0]); + pwd->b[1] =3D msa_min_u_df(DF_BYTE, pws->b[1], pwt->b[1]); + pwd->b[2] =3D msa_min_u_df(DF_BYTE, pws->b[2], pwt->b[2]); + pwd->b[3] =3D msa_min_u_df(DF_BYTE, pws->b[3], pwt->b[3]); + pwd->b[4] =3D msa_min_u_df(DF_BYTE, pws->b[4], pwt->b[4]); + pwd->b[5] =3D msa_min_u_df(DF_BYTE, pws->b[5], pwt->b[5]); + pwd->b[6] =3D msa_min_u_df(DF_BYTE, pws->b[6], pwt->b[6]); + pwd->b[7] =3D msa_min_u_df(DF_BYTE, pws->b[7], pwt->b[7]); + pwd->b[8] =3D msa_min_u_df(DF_BYTE, pws->b[8], pwt->b[8]); + pwd->b[9] =3D msa_min_u_df(DF_BYTE, pws->b[9], pwt->b[9]); + pwd->b[10] =3D msa_min_u_df(DF_BYTE, pws->b[10], pwt->b[10]); + pwd->b[11] =3D msa_min_u_df(DF_BYTE, pws->b[11], pwt->b[11]); + pwd->b[12] =3D msa_min_u_df(DF_BYTE, pws->b[12], pwt->b[12]); + pwd->b[13] =3D msa_min_u_df(DF_BYTE, pws->b[13], pwt->b[13]); + pwd->b[14] =3D msa_min_u_df(DF_BYTE, pws->b[14], pwt->b[14]); + pwd->b[15] =3D msa_min_u_df(DF_BYTE, pws->b[15], pwt->b[15]); +} + +void helper_msa_min_u_h(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); + + pwd->h[0] =3D msa_min_u_df(DF_HALF, pws->h[0], pwt->h[0]); + pwd->h[1] =3D msa_min_u_df(DF_HALF, pws->h[1], pwt->h[1]); + pwd->h[2] =3D msa_min_u_df(DF_HALF, pws->h[2], pwt->h[2]); + pwd->h[3] =3D msa_min_u_df(DF_HALF, pws->h[3], pwt->h[3]); + pwd->h[4] =3D msa_min_u_df(DF_HALF, pws->h[4], pwt->h[4]); + pwd->h[5] =3D msa_min_u_df(DF_HALF, pws->h[5], pwt->h[5]); + pwd->h[6] =3D msa_min_u_df(DF_HALF, pws->h[6], pwt->h[6]); + pwd->h[7] =3D msa_min_u_df(DF_HALF, pws->h[7], pwt->h[7]); +} + +void helper_msa_min_u_w(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); + + pwd->w[0] =3D msa_min_u_df(DF_WORD, pws->w[0], pwt->w[0]); + pwd->w[1] =3D msa_min_u_df(DF_WORD, pws->w[1], pwt->w[1]); + pwd->w[2] =3D msa_min_u_df(DF_WORD, pws->w[2], pwt->w[2]); + pwd->w[3] =3D msa_min_u_df(DF_WORD, pws->w[3], pwt->w[3]); +} + +void helper_msa_min_u_d(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); + + pwd->d[0] =3D msa_min_u_df(DF_DOUBLE, pws->d[0], pwt->d[0]); + pwd->d[1] =3D msa_min_u_df(DF_DOUBLE, pws->d[1], pwt->d[1]); +} + + /* * Int Modulo * ---------- @@ -2354,30 +2646,6 @@ static inline int64_t msa_subv_df(uint32_t df, int64= _t arg1, int64_t arg2) return arg1 - arg2; } =20 -static inline int64_t msa_max_s_df(uint32_t df, int64_t arg1, int64_t arg2) -{ - return arg1 > arg2 ? arg1 : arg2; -} - -static inline int64_t msa_max_u_df(uint32_t df, int64_t arg1, int64_t arg2) -{ - uint64_t u_arg1 =3D UNSIGNED(arg1, df); - uint64_t u_arg2 =3D UNSIGNED(arg2, df); - return u_arg1 > u_arg2 ? arg1 : arg2; -} - -static inline int64_t msa_min_s_df(uint32_t df, int64_t arg1, int64_t arg2) -{ - return arg1 < arg2 ? arg1 : arg2; -} - -static inline int64_t msa_min_u_df(uint32_t df, int64_t arg1, int64_t arg2) -{ - uint64_t u_arg1 =3D UNSIGNED(arg1, df); - uint64_t u_arg2 =3D UNSIGNED(arg2, df); - return u_arg1 < u_arg2 ? arg1 : arg2; -} - #define MSA_BINOP_IMM_DF(helper, func) \ void helper_msa_ ## helper ## _df(CPUMIPSState *env, uint32_t df, \ uint32_t wd, uint32_t ws, int32_t u5) \ @@ -2900,10 +3168,6 @@ MSA_BINOP_DF(sra) MSA_BINOP_DF(srl) MSA_BINOP_DF(addv) MSA_BINOP_DF(subv) -MSA_BINOP_DF(max_s) -MSA_BINOP_DF(max_u) -MSA_BINOP_DF(min_s) -MSA_BINOP_DF(min_u) MSA_BINOP_DF(add_a) MSA_BINOP_DF(adds_a) MSA_BINOP_DF(adds_s) diff --git a/target/mips/translate.c b/target/mips/translate.c index 8e26548..7a35c26 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -28658,6 +28658,38 @@ static void gen_msa_3r(CPUMIPSState *env, DisasCon= text *ctx) break; } break; + case OPC_MAX_S_df: + switch (df) { + case DF_BYTE: + gen_helper_msa_max_s_b(cpu_env, twd, tws, twt); + break; + case DF_HALF: + gen_helper_msa_max_s_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_max_s_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_max_s_d(cpu_env, twd, tws, twt); + break; + } + break; + case OPC_MAX_U_df: + switch (df) { + case DF_BYTE: + gen_helper_msa_max_u_b(cpu_env, twd, tws, twt); + break; + case DF_HALF: + gen_helper_msa_max_u_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_max_u_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_max_u_d(cpu_env, twd, tws, twt); + break; + } + break; case OPC_MIN_A_df: switch (df) { case DF_BYTE: @@ -28674,6 +28706,38 @@ static void gen_msa_3r(CPUMIPSState *env, DisasCon= text *ctx) break; } break; + case OPC_MIN_S_df: + switch (df) { + case DF_BYTE: + gen_helper_msa_min_s_b(cpu_env, twd, tws, twt); + break; + case DF_HALF: + gen_helper_msa_min_s_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_min_s_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_min_s_d(cpu_env, twd, tws, twt); + break; + } + break; + case OPC_MIN_U_df: + switch (df) { + case DF_BYTE: + gen_helper_msa_min_u_b(cpu_env, twd, tws, twt); + break; + case DF_HALF: + gen_helper_msa_min_u_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_min_u_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_min_u_d(cpu_env, twd, tws, twt); + break; + } + break; case OPC_MOD_S_df: switch (df) { case DF_BYTE: @@ -28751,9 +28815,6 @@ static void gen_msa_3r(CPUMIPSState *env, DisasCont= ext *ctx) case OPC_SRL_df: gen_helper_msa_srl_df(cpu_env, tdf, twd, tws, twt); break; - case OPC_MAX_S_df: - gen_helper_msa_max_s_df(cpu_env, tdf, twd, tws, twt); - break; case OPC_ADDS_S_df: gen_helper_msa_adds_s_df(cpu_env, tdf, twd, tws, twt); break; @@ -28769,9 +28830,6 @@ static void gen_msa_3r(CPUMIPSState *env, DisasCont= ext *ctx) case OPC_SRLR_df: gen_helper_msa_srlr_df(cpu_env, tdf, twd, tws, twt); break; - case OPC_MAX_U_df: - gen_helper_msa_max_u_df(cpu_env, tdf, twd, tws, twt); - break; case OPC_ADDS_U_df: gen_helper_msa_adds_u_df(cpu_env, tdf, twd, tws, twt); break; @@ -28781,18 +28839,12 @@ static void gen_msa_3r(CPUMIPSState *env, DisasCo= ntext *ctx) case OPC_PCKOD_df: gen_helper_msa_pckod_df(cpu_env, tdf, twd, tws, twt); break; - case OPC_MIN_S_df: - gen_helper_msa_min_s_df(cpu_env, tdf, twd, tws, twt); - break; case OPC_ASUB_S_df: gen_helper_msa_asub_s_df(cpu_env, tdf, twd, tws, twt); break; case OPC_ILVL_df: gen_helper_msa_ilvl_df(cpu_env, tdf, twd, tws, twt); break; - case OPC_MIN_U_df: - gen_helper_msa_min_u_df(cpu_env, tdf, twd, tws, twt); - break; case OPC_ASUB_U_df: gen_helper_msa_asub_u_df(cpu_env, tdf, twd, tws, twt); break; --=20 2.7.4