From nobody Sun May 5 20:08:25 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1570902224; cv=none; d=zoho.com; s=zohoarc; b=Z/8XzYUL7lQiqVblx/tvMev/VAT8MLiAwd4eLfBuyt1UEJVKqpMuFJtw7+5Xa1RpfzIPSuXlXXLJUdFEzN7+ZnTaFmnLADd8owCkAAEABg+xEZLCowxAh+NTtjHoVmEJO1ZOCXyiM/rTSzzSnXJyIP/avDkfeQWG09XkMUXBdj4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1570902224; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To; bh=iHygzIm80x4oAdkqM6iLfzE5xUI8PzS4gaSksLmKBHw=; b=WuqZbWl3Nk1S6EnV2FcSm0sWkf8lDQRQXeJKyD92tWUs0LROzVeSWwXsdZkMMiSUTdoJgVmSwwj4KJlzYfCGSDJ5Ydw6MMie0P9xnJR4SxYjaKUv/U/WsHu6vayMTcWVepG9GSyvVRbIxGi+sk8RuJG4aug7QJpvADxiV722/lE= ARC-Authentication-Results: i=1; mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 15709022243876.4157615381282085; Sat, 12 Oct 2019 10:43:44 -0700 (PDT) Received: from localhost ([::1]:35152 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iJLQd-0006aB-3f for importer@patchew.org; Sat, 12 Oct 2019 13:43:43 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:38575) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iJLM5-0001Nd-2J for qemu-devel@nongnu.org; Sat, 12 Oct 2019 13:39:04 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iJLM2-00026k-KK for qemu-devel@nongnu.org; Sat, 12 Oct 2019 13:39:00 -0400 Received: from mx2.rt-rk.com ([89.216.37.149]:36002 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1iJLM2-0001nt-7w for qemu-devel@nongnu.org; Sat, 12 Oct 2019 13:38:58 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id 014651A1DD1; Sat, 12 Oct 2019 19:37:53 +0200 (CEST) Received: from rtrkw774-lin.domain.local (rtrkw774-lin.domain.local [10.10.14.106]) by mail.rt-rk.com (Postfix) with ESMTPSA id CF3FA1A1CE2; Sat, 12 Oct 2019 19:37:52 +0200 (CEST) X-Virus-Scanned: amavisd-new at rt-rk.com From: Aleksandar Markovic To: qemu-devel@nongnu.org Subject: [PATCH v3 1/6] target/mips: Clean up helper.c Date: Sat, 12 Oct 2019 19:37:41 +0200 Message-Id: <1570901866-9548-2-git-send-email-aleksandar.markovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1570901866-9548-1-git-send-email-aleksandar.markovic@rt-rk.com> References: <1570901866-9548-1-git-send-email-aleksandar.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 89.216.37.149 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: aleksandar.rikalo@rt-rk.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Aleksandar Markovic Mostly fix errors and warnings reported by 'checkpatch.pl -f'. Signed-off-by: Aleksandar Markovic --- target/mips/helper.c | 128 +++++++++++++++++++++++++++++++----------------= ---- 1 file changed, 78 insertions(+), 50 deletions(-) diff --git a/target/mips/helper.c b/target/mips/helper.c index a2b6459..2411a2c 100644 --- a/target/mips/helper.c +++ b/target/mips/helper.c @@ -39,8 +39,8 @@ enum { #if !defined(CONFIG_USER_ONLY) =20 /* no MMU emulation */ -int no_mmu_map_address (CPUMIPSState *env, hwaddr *physical, int *prot, - target_ulong address, int rw, int access_type) +int no_mmu_map_address(CPUMIPSState *env, hwaddr *physical, int *prot, + target_ulong address, int rw, int access_type) { *physical =3D address; *prot =3D PAGE_READ | PAGE_WRITE | PAGE_EXEC; @@ -48,26 +48,28 @@ int no_mmu_map_address (CPUMIPSState *env, hwaddr *phys= ical, int *prot, } =20 /* fixed mapping MMU emulation */ -int fixed_mmu_map_address (CPUMIPSState *env, hwaddr *physical, int *prot, - target_ulong address, int rw, int access_type) +int fixed_mmu_map_address(CPUMIPSState *env, hwaddr *physical, int *prot, + target_ulong address, int rw, int access_type) { if (address <=3D (int32_t)0x7FFFFFFFUL) { - if (!(env->CP0_Status & (1 << CP0St_ERL))) + if (!(env->CP0_Status & (1 << CP0St_ERL))) { *physical =3D address + 0x40000000UL; - else + } else { *physical =3D address; - } else if (address <=3D (int32_t)0xBFFFFFFFUL) + } + } else if (address <=3D (int32_t)0xBFFFFFFFUL) { *physical =3D address & 0x1FFFFFFF; - else + } else { *physical =3D address; + } =20 *prot =3D PAGE_READ | PAGE_WRITE | PAGE_EXEC; return TLBRET_MATCH; } =20 /* MIPS32/MIPS64 R4000-style MMU emulation */ -int r4k_map_address (CPUMIPSState *env, hwaddr *physical, int *prot, - target_ulong address, int rw, int access_type) +int r4k_map_address(CPUMIPSState *env, hwaddr *physical, int *prot, + target_ulong address, int rw, int access_type) { uint16_t ASID =3D env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask; int i; @@ -99,8 +101,9 @@ int r4k_map_address (CPUMIPSState *env, hwaddr *physical= , int *prot, if (rw !=3D MMU_DATA_STORE || (n ? tlb->D1 : tlb->D0)) { *physical =3D tlb->PFN[n] | (address & (mask >> 1)); *prot =3D PAGE_READ; - if (n ? tlb->D1 : tlb->D0) + if (n ? tlb->D1 : tlb->D0) { *prot |=3D PAGE_WRITE; + } if (!(n ? tlb->XI1 : tlb->XI0)) { *prot |=3D PAGE_EXEC; } @@ -130,8 +133,11 @@ static int is_seg_am_mapped(unsigned int am, bool eu, = int mmu_idx) int32_t adetlb_mask; =20 switch (mmu_idx) { - case 3 /* ERL */: - /* If EU is set, always unmapped */ + case 3: + /* + * ERL + * If EU is set, always unmapped + */ if (eu) { return 0; } @@ -204,7 +210,7 @@ static int get_segctl_physical_address(CPUMIPSState *en= v, hwaddr *physical, pa & ~(hwaddr)segmask); } =20 -static int get_physical_address (CPUMIPSState *env, hwaddr *physical, +static int get_physical_address(CPUMIPSState *env, hwaddr *physical, int *prot, target_ulong real_address, int rw, int access_type, int mmu_idx) { @@ -252,14 +258,15 @@ static int get_physical_address (CPUMIPSState *env, h= waddr *physical, } else { segctl =3D env->CP0_SegCtl2 >> 16; } - ret =3D get_segctl_physical_address(env, physical, prot, real_addr= ess, rw, - access_type, mmu_idx, segctl, - 0x3FFFFFFF); + ret =3D get_segctl_physical_address(env, physical, prot, + real_address, rw, access_type, + mmu_idx, segctl, 0x3FFFFFFF); #if defined(TARGET_MIPS64) } else if (address < 0x4000000000000000ULL) { /* xuseg */ if (UX && address <=3D (0x3FFFFFFFFFFFFFFFULL & env->SEGMask)) { - ret =3D env->tlb->map_address(env, physical, prot, real_addres= s, rw, access_type); + ret =3D env->tlb->map_address(env, physical, prot, + real_address, rw, access_type); } else { ret =3D TLBRET_BADADDR; } @@ -267,7 +274,8 @@ static int get_physical_address (CPUMIPSState *env, hwa= ddr *physical, /* xsseg */ if ((supervisor_mode || kernel_mode) && SX && address <=3D (0x7FFFFFFFFFFFFFFFULL & env->SEGMask)) { - ret =3D env->tlb->map_address(env, physical, prot, real_addres= s, rw, access_type); + ret =3D env->tlb->map_address(env, physical, prot, + real_address, rw, access_type); } else { ret =3D TLBRET_BADADDR; } @@ -307,7 +315,8 @@ static int get_physical_address (CPUMIPSState *env, hwa= ddr *physical, /* xkseg */ if (kernel_mode && KX && address <=3D (0xFFFFFFFF7FFFFFFFULL & env->SEGMask)) { - ret =3D env->tlb->map_address(env, physical, prot, real_addres= s, rw, access_type); + ret =3D env->tlb->map_address(env, physical, prot, + real_address, rw, access_type); } else { ret =3D TLBRET_BADADDR; } @@ -328,8 +337,10 @@ static int get_physical_address (CPUMIPSState *env, hw= addr *physical, access_type, mmu_idx, env->CP0_SegCtl0 >> 16, 0x1FFFFF= FF); } else { - /* kseg3 */ - /* XXX: debug segment is not emulated */ + /* + * kseg3 + * XXX: debug segment is not emulated + */ ret =3D get_segctl_physical_address(env, physical, prot, real_addr= ess, rw, access_type, mmu_idx, env->CP0_SegCtl0, 0x1FFFFFFF); @@ -515,9 +526,9 @@ static void raise_mmu_exception(CPUMIPSState *env, targ= et_ulong address, #if defined(TARGET_MIPS64) env->CP0_EntryHi &=3D env->SEGMask; env->CP0_XContext =3D - /* PTEBase */ (env->CP0_XContext & ((~0ULL) << (env->SEGBITS - 7= ))) | - /* R */ (extract64(address, 62, 2) << (env->SEGBITS - 9)) | - /* BadVPN2 */ (extract64(address, 13, env->SEGBITS - 13) << 4); + (env->CP0_XContext & ((~0ULL) << (env->SEGBITS - 7))) | /* PTEBase= */ + (extract64(address, 62, 2) << (env->SEGBITS - 9)) | /* R = */ + (extract64(address, 13, env->SEGBITS - 13) << 4); /* BadVPN2= */ #endif cs->exception_index =3D exception; env->error_code =3D error_code; @@ -945,7 +956,8 @@ bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, int= size, } =20 #ifndef CONFIG_USER_ONLY -hwaddr cpu_mips_translate_address(CPUMIPSState *env, target_ulong address,= int rw) +hwaddr cpu_mips_translate_address(CPUMIPSState *env, target_ulong address, + int rw) { hwaddr physical; int prot; @@ -1005,7 +1017,7 @@ static const char * const excp_names[EXCP_LAST + 1] = =3D { }; #endif =20 -target_ulong exception_resume_pc (CPUMIPSState *env) +target_ulong exception_resume_pc(CPUMIPSState *env) { target_ulong bad_pc; target_ulong isa_mode; @@ -1013,8 +1025,10 @@ target_ulong exception_resume_pc (CPUMIPSState *env) isa_mode =3D !!(env->hflags & MIPS_HFLAG_M16); bad_pc =3D env->active_tc.PC | isa_mode; if (env->hflags & MIPS_HFLAG_BMASK) { - /* If the exception was raised from a delay slot, come back to - the jump. */ + /* + * If the exception was raised from a delay slot, come back to + * the jump. + */ bad_pc -=3D (env->hflags & MIPS_HFLAG_B16 ? 2 : 4); } =20 @@ -1022,14 +1036,14 @@ target_ulong exception_resume_pc (CPUMIPSState *env) } =20 #if !defined(CONFIG_USER_ONLY) -static void set_hflags_for_handler (CPUMIPSState *env) +static void set_hflags_for_handler(CPUMIPSState *env) { /* Exception handlers are entered in 32-bit mode. */ env->hflags &=3D ~(MIPS_HFLAG_M16); /* ...except that microMIPS lets you choose. */ if (env->insn_flags & ASE_MICROMIPS) { - env->hflags |=3D (!!(env->CP0_Config3 - & (1 << CP0C3_ISA_ON_EXC)) + env->hflags |=3D (!!(env->CP0_Config3 & + (1 << CP0C3_ISA_ON_EXC)) << MIPS_HFLAG_M16_SHIFT); } } @@ -1096,10 +1110,12 @@ void mips_cpu_do_interrupt(CPUState *cs) switch (cs->exception_index) { case EXCP_DSS: env->CP0_Debug |=3D 1 << CP0DB_DSS; - /* Debug single step cannot be raised inside a delay slot and - resume will always occur on the next instruction - (but we assume the pc has always been updated during - code translation). */ + /* + * Debug single step cannot be raised inside a delay slot and + * resume will always occur on the next instruction + * (but we assume the pc has always been updated during + * code translation). + */ env->CP0_DEPC =3D env->active_tc.PC | !!(env->hflags & MIPS_HFLAG_= M16); goto enter_debug_mode; case EXCP_DINT: @@ -1111,7 +1127,8 @@ void mips_cpu_do_interrupt(CPUState *cs) case EXCP_DBp: env->CP0_Debug |=3D 1 << CP0DB_DBp; /* Setup DExcCode - SDBBP instruction */ - env->CP0_Debug =3D (env->CP0_Debug & ~(0x1fULL << CP0DB_DEC)) | 9 = << CP0DB_DEC; + env->CP0_Debug =3D (env->CP0_Debug & ~(0x1fULL << CP0DB_DEC)) | + (9 << CP0DB_DEC); goto set_DEPC; case EXCP_DDBS: env->CP0_Debug |=3D 1 << CP0DB_DDBS; @@ -1132,8 +1149,9 @@ void mips_cpu_do_interrupt(CPUState *cs) env->hflags |=3D MIPS_HFLAG_DM | MIPS_HFLAG_CP0; env->hflags &=3D ~(MIPS_HFLAG_KSU); /* EJTAG probe trap enable is not implemented... */ - if (!(env->CP0_Status & (1 << CP0St_EXL))) + if (!(env->CP0_Status & (1 << CP0St_EXL))) { env->CP0_Cause &=3D ~(1U << CP0Ca_BD); + } env->active_tc.PC =3D env->exception_base + 0x480; set_hflags_for_handler(env); break; @@ -1159,8 +1177,9 @@ void mips_cpu_do_interrupt(CPUState *cs) } env->hflags |=3D MIPS_HFLAG_CP0; env->hflags &=3D ~(MIPS_HFLAG_KSU); - if (!(env->CP0_Status & (1 << CP0St_EXL))) + if (!(env->CP0_Status & (1 << CP0St_EXL))) { env->CP0_Cause &=3D ~(1U << CP0Ca_BD); + } env->active_tc.PC =3D env->exception_base; set_hflags_for_handler(env); break; @@ -1176,12 +1195,16 @@ void mips_cpu_do_interrupt(CPUState *cs) uint32_t pending =3D (env->CP0_Cause & CP0Ca_IP_mask) >> C= P0Ca_IP; =20 if (env->CP0_Config3 & (1 << CP0C3_VEIC)) { - /* For VEIC mode, the external interrupt controller fe= eds - * the vector through the CP0Cause IP lines. */ + /* + * For VEIC mode, the external interrupt controller fe= eds + * the vector through the CP0Cause IP lines. + */ vector =3D pending; } else { - /* Vectored Interrupts - * Mask with Status.IM7-IM0 to get enabled interrupts.= */ + /* + * Vectored Interrupts + * Mask with Status.IM7-IM0 to get enabled interrupts. + */ pending &=3D (env->CP0_Status >> CP0St_IM) & 0xff; /* Find the highest-priority interrupt. */ while (pending >>=3D 1) { @@ -1354,7 +1377,8 @@ void mips_cpu_do_interrupt(CPUState *cs) =20 env->active_tc.PC +=3D offset; set_hflags_for_handler(env); - env->CP0_Cause =3D (env->CP0_Cause & ~(0x1f << CP0Ca_EC)) | (cause= << CP0Ca_EC); + env->CP0_Cause =3D (env->CP0_Cause & ~(0x1f << CP0Ca_EC)) | + (cause << CP0Ca_EC); break; default: abort(); @@ -1390,7 +1414,7 @@ bool mips_cpu_exec_interrupt(CPUState *cs, int interr= upt_request) } =20 #if !defined(CONFIG_USER_ONLY) -void r4k_invalidate_tlb (CPUMIPSState *env, int idx, int use_extra) +void r4k_invalidate_tlb(CPUMIPSState *env, int idx, int use_extra) { CPUState *cs =3D env_cpu(env); r4k_tlb_t *tlb; @@ -1400,16 +1424,20 @@ void r4k_invalidate_tlb (CPUMIPSState *env, int idx= , int use_extra) target_ulong mask; =20 tlb =3D &env->tlb->mmu.r4k.tlb[idx]; - /* The qemu TLB is flushed when the ASID changes, so no need to - flush these entries again. */ + /* + * The qemu TLB is flushed when the ASID changes, so no need to + * flush these entries again. + */ if (tlb->G =3D=3D 0 && tlb->ASID !=3D ASID) { return; } =20 if (use_extra && env->tlb->tlb_in_use < MIPS_TLB_MAX) { - /* For tlbwr, we can shadow the discarded entry into - a new (fake) TLB entry, as long as the guest can not - tell that it's there. */ + /* + * For tlbwr, we can shadow the discarded entry into + * a new (fake) TLB entry, as long as the guest can not + * tell that it's there. + */ env->tlb->mmu.r4k.tlb[env->tlb->tlb_in_use] =3D *tlb; env->tlb->tlb_in_use++; return; --=20 2.7.4 From nobody Sun May 5 20:08:25 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1570902247; cv=none; d=zoho.com; s=zohoarc; b=f2tN8iBO5EuCcHnG+yXyuYbXLaiKFpfZVJaj4ATjeBKEdPbCY8Rx2X+17nOk9vKAEmjPRYPN+tg4fxNxkSThLMsyr5UL3scp56b0GmhEqhUFE3jVu4FLjR4T7pcsqwewWKJKgKJC1Bc3x8dqHGDCqnq/hiy9/HS4HoNCilHpo50= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1570902247; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To; bh=7vCl6SKxpfX58wRntVx42qI/3QFh8z0ukeNrXNKNczw=; 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Sat, 12 Oct 2019 13:39:08 -0400 Received: from mx2.rt-rk.com ([89.216.37.149]:36143 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1iJLM3-00026g-Ej for qemu-devel@nongnu.org; Sat, 12 Oct 2019 13:39:00 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id 412381A1E28; Sat, 12 Oct 2019 19:37:53 +0200 (CEST) Received: from rtrkw774-lin.domain.local (rtrkw774-lin.domain.local [10.10.14.106]) by mail.rt-rk.com (Postfix) with ESMTPSA id DC9AD1A1CE4; Sat, 12 Oct 2019 19:37:52 +0200 (CEST) X-Virus-Scanned: amavisd-new at rt-rk.com From: Aleksandar Markovic To: qemu-devel@nongnu.org Subject: [PATCH v3 2/6] target/mips: Clean up op_helper.c Date: Sat, 12 Oct 2019 19:37:42 +0200 Message-Id: <1570901866-9548-3-git-send-email-aleksandar.markovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1570901866-9548-1-git-send-email-aleksandar.markovic@rt-rk.com> References: <1570901866-9548-1-git-send-email-aleksandar.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 89.216.37.149 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: aleksandar.rikalo@rt-rk.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Aleksandar Markovic Mostly fix errors and warnings reported by 'checkpatch.pl -f'. Signed-off-by: Aleksandar Markovic --- target/mips/op_helper.c | 1010 +++++++++++++++++++++++++++++++------------= ---- 1 file changed, 663 insertions(+), 347 deletions(-) diff --git a/target/mips/op_helper.c b/target/mips/op_helper.c index 4de6465..18fcee4 100644 --- a/target/mips/op_helper.c +++ b/target/mips/op_helper.c @@ -64,8 +64,7 @@ static inline type do_##name(CPUMIPSState *env, target_ul= ong addr, \ static inline type do_##name(CPUMIPSState *env, target_ulong addr, \ int mem_idx, uintptr_t retaddr) \ { \ - switch (mem_idx) \ - { \ + switch (mem_idx) { \ case 0: return (type) cpu_##insn##_kernel_ra(env, addr, retaddr); \ case 1: return (type) cpu_##insn##_super_ra(env, addr, retaddr); \ default: \ @@ -92,12 +91,17 @@ static inline void do_##name(CPUMIPSState *env, target_= ulong addr, \ static inline void do_##name(CPUMIPSState *env, target_ulong addr, \ type val, int mem_idx, uintptr_t retaddr) \ { \ - switch (mem_idx) \ - { \ - case 0: cpu_##insn##_kernel_ra(env, addr, val, retaddr); break; \ - case 1: cpu_##insn##_super_ra(env, addr, val, retaddr); break; \ + switch (mem_idx) { \ + case 0: \ + cpu_##insn##_kernel_ra(env, addr, val, retaddr); \ + break; \ + case 1: \ + cpu_##insn##_super_ra(env, addr, val, retaddr); \ + break; \ default: \ - case 2: cpu_##insn##_user_ra(env, addr, val, retaddr); break; \ + case 2: \ + cpu_##insn##_user_ra(env, addr, val, retaddr); \ + break; \ case 3: \ cpu_##insn##_error_ra(env, addr, val, retaddr); \ break; \ @@ -114,7 +118,8 @@ HELPER_ST(sd, stq, uint64_t) /* 64 bits arithmetic for 32 bits hosts */ static inline uint64_t get_HILO(CPUMIPSState *env) { - return ((uint64_t)(env->active_tc.HI[0]) << 32) | (uint32_t)env->activ= e_tc.LO[0]; + return ((uint64_t)(env->active_tc.HI[0]) << 32) | + (uint32_t)env->active_tc.LO[0]; } =20 static inline target_ulong set_HIT0_LO(CPUMIPSState *env, uint64_t HILO) @@ -435,9 +440,10 @@ void helper_swr(CPUMIPSState *env, target_ulong arg1, = target_ulong arg2, } =20 #if defined(TARGET_MIPS64) -/* "half" load and stores. We must do the memory access inline, - or fault handling won't work. */ - +/* + * "half" load and stores. We must do the memory access inline, + * or fault handling won't work. + */ #ifdef TARGET_WORDS_BIGENDIAN #define GET_LMASK64(v) ((v) & 7) #else @@ -535,7 +541,7 @@ void helper_lwm(CPUMIPSState *env, target_ulong addr, t= arget_ulong reglist, target_ulong base_reglist =3D reglist & 0xf; target_ulong do_r31 =3D reglist & 0x10; =20 - if (base_reglist > 0 && base_reglist <=3D ARRAY_SIZE (multiple_regs)) { + if (base_reglist > 0 && base_reglist <=3D ARRAY_SIZE(multiple_regs)) { target_ulong i; =20 for (i =3D 0; i < base_reglist; i++) { @@ -557,7 +563,7 @@ void helper_swm(CPUMIPSState *env, target_ulong addr, t= arget_ulong reglist, target_ulong base_reglist =3D reglist & 0xf; target_ulong do_r31 =3D reglist & 0x10; =20 - if (base_reglist > 0 && base_reglist <=3D ARRAY_SIZE (multiple_regs)) { + if (base_reglist > 0 && base_reglist <=3D ARRAY_SIZE(multiple_regs)) { target_ulong i; =20 for (i =3D 0; i < base_reglist; i++) { @@ -579,7 +585,7 @@ void helper_ldm(CPUMIPSState *env, target_ulong addr, t= arget_ulong reglist, target_ulong base_reglist =3D reglist & 0xf; target_ulong do_r31 =3D reglist & 0x10; =20 - if (base_reglist > 0 && base_reglist <=3D ARRAY_SIZE (multiple_regs)) { + if (base_reglist > 0 && base_reglist <=3D ARRAY_SIZE(multiple_regs)) { target_ulong i; =20 for (i =3D 0; i < base_reglist; i++) { @@ -600,7 +606,7 @@ void helper_sdm(CPUMIPSState *env, target_ulong addr, t= arget_ulong reglist, target_ulong base_reglist =3D reglist & 0xf; target_ulong do_r31 =3D reglist & 0x10; =20 - if (base_reglist > 0 && base_reglist <=3D ARRAY_SIZE (multiple_regs)) { + if (base_reglist > 0 && base_reglist <=3D ARRAY_SIZE(multiple_regs)) { target_ulong i; =20 for (i =3D 0; i < base_reglist; i++) { @@ -623,8 +629,10 @@ static bool mips_vpe_is_wfi(MIPSCPU *c) CPUState *cpu =3D CPU(c); CPUMIPSState *env =3D &c->env; =20 - /* If the VPE is halted but otherwise active, it means it's waiting for - an interrupt. */ + /* + * If the VPE is halted but otherwise active, it means it's waiting for + * an interrupt.\ + */ return cpu->halted && mips_vpe_active(env); } =20 @@ -638,9 +646,11 @@ static bool mips_vp_is_wfi(MIPSCPU *c) =20 static inline void mips_vpe_wake(MIPSCPU *c) { - /* Don't set ->halted =3D 0 directly, let it be done via cpu_has_work - because there might be other conditions that state that c should - be sleeping. */ + /* + * Don't set ->halted =3D 0 directly, let it be done via cpu_has_work + * because there might be other conditions that state that c should + * be sleeping. + */ qemu_mutex_lock_iothread(); cpu_interrupt(CPU(c), CPU_INTERRUPT_WAKE); qemu_mutex_unlock_iothread(); @@ -650,8 +660,10 @@ static inline void mips_vpe_sleep(MIPSCPU *cpu) { CPUState *cs =3D CPU(cpu); =20 - /* The VPE was shut off, really go to bed. - Reset any old _WAKE requests. */ + /* + * The VPE was shut off, really go to bed. + * Reset any old _WAKE requests. + */ cs->halted =3D 1; cpu_reset_interrupt(cs, CPU_INTERRUPT_WAKE); } @@ -684,9 +696,12 @@ static inline void mips_tc_sleep(MIPSCPU *cpu, int tc) * This function will transform @tc into a local index within the * returned #CPUMIPSState. */ -/* FIXME: This code assumes that all VPEs have the same number of TCs, - which depends on runtime setup. Can probably be fixed by - walking the list of CPUMIPSStates. */ + +/* + * FIXME: This code assumes that all VPEs have the same number of TCs, + * which depends on runtime setup. Can probably be fixed by + * walking the list of CPUMIPSStates. + */ static CPUMIPSState *mips_cpu_map_tc(CPUMIPSState *env, int *tc) { MIPSCPU *cpu; @@ -712,17 +727,21 @@ static CPUMIPSState *mips_cpu_map_tc(CPUMIPSState *en= v, int *tc) return &cpu->env; } =20 -/* The per VPE CP0_Status register shares some fields with the per TC - CP0_TCStatus registers. These fields are wired to the same registers, - so changes to either of them should be reflected on both registers. - - Also, EntryHi shares the bottom 8 bit ASID with TCStauts. - - These helper call synchronizes the regs for a given cpu. */ +/* + * The per VPE CP0_Status register shares some fields with the per TC + * CP0_TCStatus registers. These fields are wired to the same registers, + * so changes to either of them should be reflected on both registers. + * + * Also, EntryHi shares the bottom 8 bit ASID with TCStauts. + * + * These helper call synchronizes the regs for a given cpu. + */ =20 -/* Called for updates to CP0_Status. Defined in "cpu.h" for gdbstub.c. */ -/* static inline void sync_c0_status(CPUMIPSState *env, CPUMIPSState *cpu, - int tc); */ +/* + * Called for updates to CP0_Status. Defined in "cpu.h" for gdbstub.c. + * static inline void sync_c0_status(CPUMIPSState *env, CPUMIPSState *cpu, + * int tc); + */ =20 /* Called for updates to CP0_TCStatus. */ static void sync_c0_tcstatus(CPUMIPSState *cpu, int tc, @@ -805,10 +824,11 @@ target_ulong helper_mftc0_tcstatus(CPUMIPSState *env) int other_tc =3D env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); CPUMIPSState *other =3D mips_cpu_map_tc(env, &other_tc); =20 - if (other_tc =3D=3D other->current_tc) + if (other_tc =3D=3D other->current_tc) { return other->active_tc.CP0_TCStatus; - else + } else { return other->tcs[other_tc].CP0_TCStatus; + } } =20 target_ulong helper_mfc0_tcbind(CPUMIPSState *env) @@ -821,10 +841,11 @@ target_ulong helper_mftc0_tcbind(CPUMIPSState *env) int other_tc =3D env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); CPUMIPSState *other =3D mips_cpu_map_tc(env, &other_tc); =20 - if (other_tc =3D=3D other->current_tc) + if (other_tc =3D=3D other->current_tc) { return other->active_tc.CP0_TCBind; - else + } else { return other->tcs[other_tc].CP0_TCBind; + } } =20 target_ulong helper_mfc0_tcrestart(CPUMIPSState *env) @@ -837,10 +858,11 @@ target_ulong helper_mftc0_tcrestart(CPUMIPSState *env) int other_tc =3D env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); CPUMIPSState *other =3D mips_cpu_map_tc(env, &other_tc); =20 - if (other_tc =3D=3D other->current_tc) + if (other_tc =3D=3D other->current_tc) { return other->active_tc.PC; - else + } else { return other->tcs[other_tc].PC; + } } =20 target_ulong helper_mfc0_tchalt(CPUMIPSState *env) @@ -853,10 +875,11 @@ target_ulong helper_mftc0_tchalt(CPUMIPSState *env) int other_tc =3D env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); CPUMIPSState *other =3D mips_cpu_map_tc(env, &other_tc); =20 - if (other_tc =3D=3D other->current_tc) + if (other_tc =3D=3D other->current_tc) { return other->active_tc.CP0_TCHalt; - else + } else { return other->tcs[other_tc].CP0_TCHalt; + } } =20 target_ulong helper_mfc0_tccontext(CPUMIPSState *env) @@ -869,10 +892,11 @@ target_ulong helper_mftc0_tccontext(CPUMIPSState *env) int other_tc =3D env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); CPUMIPSState *other =3D mips_cpu_map_tc(env, &other_tc); =20 - if (other_tc =3D=3D other->current_tc) + if (other_tc =3D=3D other->current_tc) { return other->active_tc.CP0_TCContext; - else + } else { return other->tcs[other_tc].CP0_TCContext; + } } =20 target_ulong helper_mfc0_tcschedule(CPUMIPSState *env) @@ -885,10 +909,11 @@ target_ulong helper_mftc0_tcschedule(CPUMIPSState *en= v) int other_tc =3D env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); CPUMIPSState *other =3D mips_cpu_map_tc(env, &other_tc); =20 - if (other_tc =3D=3D other->current_tc) + if (other_tc =3D=3D other->current_tc) { return other->active_tc.CP0_TCSchedule; - else + } else { return other->tcs[other_tc].CP0_TCSchedule; + } } =20 target_ulong helper_mfc0_tcschefback(CPUMIPSState *env) @@ -901,10 +926,11 @@ target_ulong helper_mftc0_tcschefback(CPUMIPSState *e= nv) int other_tc =3D env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); CPUMIPSState *other =3D mips_cpu_map_tc(env, &other_tc); =20 - if (other_tc =3D=3D other->current_tc) + if (other_tc =3D=3D other->current_tc) { return other->active_tc.CP0_TCScheFBack; - else + } else { return other->tcs[other_tc].CP0_TCScheFBack; + } } =20 target_ulong helper_mfc0_count(CPUMIPSState *env) @@ -987,8 +1013,9 @@ target_ulong helper_mfc0_watchhi(CPUMIPSState *env, ui= nt32_t sel) target_ulong helper_mfc0_debug(CPUMIPSState *env) { target_ulong t0 =3D env->CP0_Debug; - if (env->hflags & MIPS_HFLAG_DM) + if (env->hflags & MIPS_HFLAG_DM) { t0 |=3D 1 << CP0DB_DM; + } =20 return t0; } @@ -999,10 +1026,11 @@ target_ulong helper_mftc0_debug(CPUMIPSState *env) int32_t tcstatus; CPUMIPSState *other =3D mips_cpu_map_tc(env, &other_tc); =20 - if (other_tc =3D=3D other->current_tc) + if (other_tc =3D=3D other->current_tc) { tcstatus =3D other->active_tc.CP0_Debug_tcstatus; - else + } else { tcstatus =3D other->tcs[other_tc].CP0_Debug_tcstatus; + } =20 /* XXX: Might be wrong, check with EJTAG spec. */ return (other->CP0_Debug & ~((1 << CP0DB_SSt) | (1 << CP0DB_Halt))) | @@ -1076,14 +1104,16 @@ void helper_mtc0_mvpcontrol(CPUMIPSState *env, targ= et_ulong arg1) uint32_t mask =3D 0; uint32_t newval; =20 - if (env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP)) + if (env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP)) { mask |=3D (1 << CP0MVPCo_CPA) | (1 << CP0MVPCo_VPC) | (1 << CP0MVPCo_EVP); - if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC)) + } + if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC)) { mask |=3D (1 << CP0MVPCo_STLB); + } newval =3D (env->mvp->CP0_MVPControl & ~mask) | (arg1 & mask); =20 - // TODO: Enable/disable shared TLB, enable/disable VPEs. + /* TODO: Enable/disable shared TLB, enable/disable VPEs. */ =20 env->mvp->CP0_MVPControl =3D newval; } @@ -1097,10 +1127,12 @@ void helper_mtc0_vpecontrol(CPUMIPSState *env, targ= et_ulong arg1) (1 << CP0VPECo_TE) | (0xff << CP0VPECo_TargTC); newval =3D (env->CP0_VPEControl & ~mask) | (arg1 & mask); =20 - /* Yield scheduler intercept not implemented. */ - /* Gating storage scheduler intercept not implemented. */ + /* + * Yield scheduler intercept not implemented. + * Gating storage scheduler intercept not implemented. + */ =20 - // TODO: Enable/disable TCs. + /* TODO: Enable/disable TCs. */ =20 env->CP0_VPEControl =3D newval; } @@ -1143,13 +1175,14 @@ void helper_mtc0_vpeconf0(CPUMIPSState *env, target= _ulong arg1) uint32_t newval; =20 if (env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP)) { - if (env->CP0_VPEConf0 & (1 << CP0VPEC0_VPA)) + if (env->CP0_VPEConf0 & (1 << CP0VPEC0_VPA)) { mask |=3D (0xff << CP0VPEC0_XTC); + } mask |=3D (1 << CP0VPEC0_MVP) | (1 << CP0VPEC0_VPA); } newval =3D (env->CP0_VPEConf0 & ~mask) | (arg1 & mask); =20 - // TODO: TC exclusive handling due to ERL/EXL. + /* TODO: TC exclusive handling due to ERL/EXL. */ =20 env->CP0_VPEConf0 =3D newval; } @@ -1181,7 +1214,7 @@ void helper_mtc0_vpeconf1(CPUMIPSState *env, target_u= long arg1) /* UDI not implemented. */ /* CP2 not implemented. */ =20 - // TODO: Handle FPU (CP1) binding. + /* TODO: Handle FPU (CP1) binding. */ =20 env->CP0_VPEConf1 =3D newval; } @@ -1233,10 +1266,11 @@ void helper_mttc0_tcstatus(CPUMIPSState *env, targe= t_ulong arg1) int other_tc =3D env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); CPUMIPSState *other =3D mips_cpu_map_tc(env, &other_tc); =20 - if (other_tc =3D=3D other->current_tc) + if (other_tc =3D=3D other->current_tc) { other->active_tc.CP0_TCStatus =3D arg1; - else + } else { other->tcs[other_tc].CP0_TCStatus =3D arg1; + } sync_c0_tcstatus(other, other_tc, arg1); } =20 @@ -1245,8 +1279,9 @@ void helper_mtc0_tcbind(CPUMIPSState *env, target_ulo= ng arg1) uint32_t mask =3D (1 << CP0TCBd_TBE); uint32_t newval; =20 - if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC)) + if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC)) { mask |=3D (1 << CP0TCBd_CurVPE); + } newval =3D (env->active_tc.CP0_TCBind & ~mask) | (arg1 & mask); env->active_tc.CP0_TCBind =3D newval; } @@ -1258,8 +1293,9 @@ void helper_mttc0_tcbind(CPUMIPSState *env, target_ul= ong arg1) uint32_t newval; CPUMIPSState *other =3D mips_cpu_map_tc(env, &other_tc); =20 - if (other->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC)) + if (other->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC)) { mask |=3D (1 << CP0TCBd_CurVPE); + } if (other_tc =3D=3D other->current_tc) { newval =3D (other->active_tc.CP0_TCBind & ~mask) | (arg1 & mask); other->active_tc.CP0_TCBind =3D newval; @@ -1304,7 +1340,7 @@ void helper_mtc0_tchalt(CPUMIPSState *env, target_ulo= ng arg1) =20 env->active_tc.CP0_TCHalt =3D arg1 & 0x1; =20 - // TODO: Halt TC / Restart (if allocated+active) TC. + /* TODO: Halt TC / Restart (if allocated+active) TC. */ if (env->active_tc.CP0_TCHalt & 1) { mips_tc_sleep(cpu, env->current_tc); } else { @@ -1318,12 +1354,13 @@ void helper_mttc0_tchalt(CPUMIPSState *env, target_= ulong arg1) CPUMIPSState *other =3D mips_cpu_map_tc(env, &other_tc); MIPSCPU *other_cpu =3D env_archcpu(other); =20 - // TODO: Halt TC / Restart (if allocated+active) TC. + /* TODO: Halt TC / Restart (if allocated+active) TC. */ =20 - if (other_tc =3D=3D other->current_tc) + if (other_tc =3D=3D other->current_tc) { other->active_tc.CP0_TCHalt =3D arg1; - else + } else { other->tcs[other_tc].CP0_TCHalt =3D arg1; + } =20 if (arg1 & 1) { mips_tc_sleep(other_cpu, other_tc); @@ -1342,10 +1379,11 @@ void helper_mttc0_tccontext(CPUMIPSState *env, targ= et_ulong arg1) int other_tc =3D env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); CPUMIPSState *other =3D mips_cpu_map_tc(env, &other_tc); =20 - if (other_tc =3D=3D other->current_tc) + if (other_tc =3D=3D other->current_tc) { other->active_tc.CP0_TCContext =3D arg1; - else + } else { other->tcs[other_tc].CP0_TCContext =3D arg1; + } } =20 void helper_mtc0_tcschedule(CPUMIPSState *env, target_ulong arg1) @@ -1358,10 +1396,11 @@ void helper_mttc0_tcschedule(CPUMIPSState *env, tar= get_ulong arg1) int other_tc =3D env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); CPUMIPSState *other =3D mips_cpu_map_tc(env, &other_tc); =20 - if (other_tc =3D=3D other->current_tc) + if (other_tc =3D=3D other->current_tc) { other->active_tc.CP0_TCSchedule =3D arg1; - else + } else { other->tcs[other_tc].CP0_TCSchedule =3D arg1; + } } =20 void helper_mtc0_tcschefback(CPUMIPSState *env, target_ulong arg1) @@ -1374,10 +1413,11 @@ void helper_mttc0_tcschefback(CPUMIPSState *env, ta= rget_ulong arg1) int other_tc =3D env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); CPUMIPSState *other =3D mips_cpu_map_tc(env, &other_tc); =20 - if (other_tc =3D=3D other->current_tc) + if (other_tc =3D=3D other->current_tc) { other->active_tc.CP0_TCScheFBack =3D arg1; - else + } else { other->tcs[other_tc].CP0_TCScheFBack =3D arg1; + } } =20 void helper_mtc0_entrylo1(CPUMIPSState *env, target_ulong arg1) @@ -1703,9 +1743,15 @@ void helper_mtc0_status(CPUMIPSState *env, target_ul= ong arg1) case 3: qemu_log(", ERL\n"); break; - case MIPS_HFLAG_UM: qemu_log(", UM\n"); break; - case MIPS_HFLAG_SM: qemu_log(", SM\n"); break; - case MIPS_HFLAG_KM: qemu_log("\n"); break; + case MIPS_HFLAG_UM: + qemu_log(", UM\n"); + break; + case MIPS_HFLAG_SM: + qemu_log(", SM\n"); + break; + case MIPS_HFLAG_KM: + qemu_log("\n"); + break; default: cpu_abort(env_cpu(env), "Invalid MMU mode!\n"); break; @@ -1860,21 +1906,26 @@ void helper_mtc0_maari(CPUMIPSState *env, target_ul= ong arg1) { int index =3D arg1 & 0x3f; if (index =3D=3D 0x3f) { - /* Software may write all ones to INDEX to determine the - maximum value supported. */ + /* + * Software may write all ones to INDEX to determine the + * maximum value supported. + */ env->CP0_MAARI =3D MIPS_MAAR_MAX - 1; } else if (index < MIPS_MAAR_MAX) { env->CP0_MAARI =3D index; } - /* Other than the all ones, if the - value written is not supported, then INDEX is unchanged - from its previous value. */ + /* + * Other than the all ones, if the value written is not supported, + * then INDEX is unchanged from its previous value. + */ } =20 void helper_mtc0_watchlo(CPUMIPSState *env, target_ulong arg1, uint32_t se= l) { - /* Watch exceptions for instructions, data loads, data stores - not implemented. */ + /* + * Watch exceptions for instructions, data loads, data stores + * not implemented. + */ env->CP0_WatchLo[sel] =3D (arg1 & ~0x7); } =20 @@ -1899,10 +1950,11 @@ void helper_mtc0_framemask(CPUMIPSState *env, targe= t_ulong arg1) void helper_mtc0_debug(CPUMIPSState *env, target_ulong arg1) { env->CP0_Debug =3D (env->CP0_Debug & 0x8C03FC1F) | (arg1 & 0x13300120); - if (arg1 & (1 << CP0DB_DM)) + if (arg1 & (1 << CP0DB_DM)) { env->hflags |=3D MIPS_HFLAG_DM; - else + } else { env->hflags &=3D ~MIPS_HFLAG_DM; + } } =20 void helper_mttc0_debug(CPUMIPSState *env, target_ulong arg1) @@ -1912,10 +1964,11 @@ void helper_mttc0_debug(CPUMIPSState *env, target_u= long arg1) CPUMIPSState *other =3D mips_cpu_map_tc(env, &other_tc); =20 /* XXX: Might be wrong, check with EJTAG spec. */ - if (other_tc =3D=3D other->current_tc) + if (other_tc =3D=3D other->current_tc) { other->active_tc.CP0_Debug_tcstatus =3D val; - else + } else { other->tcs[other_tc].CP0_Debug_tcstatus =3D val; + } other->CP0_Debug =3D (other->CP0_Debug & ((1 << CP0DB_SSt) | (1 << CP0DB_Halt))) | (arg1 & ~((1 << CP0DB_SSt) | (1 << CP0DB_Halt))); @@ -1944,9 +1997,11 @@ void helper_mtc0_errctl(CPUMIPSState *env, target_ul= ong arg1) void helper_mtc0_taglo(CPUMIPSState *env, target_ulong arg1) { if (env->hflags & MIPS_HFLAG_ITC_CACHE) { - /* If CACHE instruction is configured for ITC tags then make all - CP0.TagLo bits writable. The actual write to ITC Configuration - Tag will take care of the read-only bits. */ + /* + * If CACHE instruction is configured for ITC tags then make all + * CP0.TagLo bits writable. The actual write to ITC Configuration + * Tag will take care of the read-only bits. + */ env->CP0_TagLo =3D arg1; } else { env->CP0_TagLo =3D arg1 & 0xFFFFFCF6; @@ -1974,10 +2029,11 @@ target_ulong helper_mftgpr(CPUMIPSState *env, uint3= 2_t sel) int other_tc =3D env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); CPUMIPSState *other =3D mips_cpu_map_tc(env, &other_tc); =20 - if (other_tc =3D=3D other->current_tc) + if (other_tc =3D=3D other->current_tc) { return other->active_tc.gpr[sel]; - else + } else { return other->tcs[other_tc].gpr[sel]; + } } =20 target_ulong helper_mftlo(CPUMIPSState *env, uint32_t sel) @@ -1985,10 +2041,11 @@ target_ulong helper_mftlo(CPUMIPSState *env, uint32= _t sel) int other_tc =3D env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); CPUMIPSState *other =3D mips_cpu_map_tc(env, &other_tc); =20 - if (other_tc =3D=3D other->current_tc) + if (other_tc =3D=3D other->current_tc) { return other->active_tc.LO[sel]; - else + } else { return other->tcs[other_tc].LO[sel]; + } } =20 target_ulong helper_mfthi(CPUMIPSState *env, uint32_t sel) @@ -1996,10 +2053,11 @@ target_ulong helper_mfthi(CPUMIPSState *env, uint32= _t sel) int other_tc =3D env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); CPUMIPSState *other =3D mips_cpu_map_tc(env, &other_tc); =20 - if (other_tc =3D=3D other->current_tc) + if (other_tc =3D=3D other->current_tc) { return other->active_tc.HI[sel]; - else + } else { return other->tcs[other_tc].HI[sel]; + } } =20 target_ulong helper_mftacx(CPUMIPSState *env, uint32_t sel) @@ -2007,10 +2065,11 @@ target_ulong helper_mftacx(CPUMIPSState *env, uint3= 2_t sel) int other_tc =3D env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); CPUMIPSState *other =3D mips_cpu_map_tc(env, &other_tc); =20 - if (other_tc =3D=3D other->current_tc) + if (other_tc =3D=3D other->current_tc) { return other->active_tc.ACX[sel]; - else + } else { return other->tcs[other_tc].ACX[sel]; + } } =20 target_ulong helper_mftdsp(CPUMIPSState *env) @@ -2018,10 +2077,11 @@ target_ulong helper_mftdsp(CPUMIPSState *env) int other_tc =3D env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); CPUMIPSState *other =3D mips_cpu_map_tc(env, &other_tc); =20 - if (other_tc =3D=3D other->current_tc) + if (other_tc =3D=3D other->current_tc) { return other->active_tc.DSPControl; - else + } else { return other->tcs[other_tc].DSPControl; + } } =20 void helper_mttgpr(CPUMIPSState *env, target_ulong arg1, uint32_t sel) @@ -2029,10 +2089,11 @@ void helper_mttgpr(CPUMIPSState *env, target_ulong = arg1, uint32_t sel) int other_tc =3D env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); CPUMIPSState *other =3D mips_cpu_map_tc(env, &other_tc); =20 - if (other_tc =3D=3D other->current_tc) + if (other_tc =3D=3D other->current_tc) { other->active_tc.gpr[sel] =3D arg1; - else + } else { other->tcs[other_tc].gpr[sel] =3D arg1; + } } =20 void helper_mttlo(CPUMIPSState *env, target_ulong arg1, uint32_t sel) @@ -2040,10 +2101,11 @@ void helper_mttlo(CPUMIPSState *env, target_ulong a= rg1, uint32_t sel) int other_tc =3D env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); CPUMIPSState *other =3D mips_cpu_map_tc(env, &other_tc); =20 - if (other_tc =3D=3D other->current_tc) + if (other_tc =3D=3D other->current_tc) { other->active_tc.LO[sel] =3D arg1; - else + } else { other->tcs[other_tc].LO[sel] =3D arg1; + } } =20 void helper_mtthi(CPUMIPSState *env, target_ulong arg1, uint32_t sel) @@ -2051,10 +2113,11 @@ void helper_mtthi(CPUMIPSState *env, target_ulong a= rg1, uint32_t sel) int other_tc =3D env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); CPUMIPSState *other =3D mips_cpu_map_tc(env, &other_tc); =20 - if (other_tc =3D=3D other->current_tc) + if (other_tc =3D=3D other->current_tc) { other->active_tc.HI[sel] =3D arg1; - else + } else { other->tcs[other_tc].HI[sel] =3D arg1; + } } =20 void helper_mttacx(CPUMIPSState *env, target_ulong arg1, uint32_t sel) @@ -2062,10 +2125,11 @@ void helper_mttacx(CPUMIPSState *env, target_ulong = arg1, uint32_t sel) int other_tc =3D env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); CPUMIPSState *other =3D mips_cpu_map_tc(env, &other_tc); =20 - if (other_tc =3D=3D other->current_tc) + if (other_tc =3D=3D other->current_tc) { other->active_tc.ACX[sel] =3D arg1; - else + } else { other->tcs[other_tc].ACX[sel] =3D arg1; + } } =20 void helper_mttdsp(CPUMIPSState *env, target_ulong arg1) @@ -2073,22 +2137,23 @@ void helper_mttdsp(CPUMIPSState *env, target_ulong = arg1) int other_tc =3D env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); CPUMIPSState *other =3D mips_cpu_map_tc(env, &other_tc); =20 - if (other_tc =3D=3D other->current_tc) + if (other_tc =3D=3D other->current_tc) { other->active_tc.DSPControl =3D arg1; - else + } else { other->tcs[other_tc].DSPControl =3D arg1; + } } =20 /* MIPS MT functions */ target_ulong helper_dmt(void) { - // TODO - return 0; + /* TODO */ + return 0; } =20 target_ulong helper_emt(void) { - // TODO + /* TODO */ return 0; } =20 @@ -2130,8 +2195,10 @@ target_ulong helper_evpe(CPUMIPSState *env) =20 void helper_fork(target_ulong arg1, target_ulong arg2) { - // arg1 =3D rt, arg2 =3D rs - // TODO: store to TC register + /* + * arg1 =3D rt, arg2 =3D rs + * TODO: store to TC register + */ } =20 target_ulong helper_yield(CPUMIPSState *env, target_ulong arg) @@ -2149,11 +2216,12 @@ target_ulong helper_yield(CPUMIPSState *env, target= _ulong arg) } } } else if (arg1 =3D=3D 0) { - if (0 /* TODO: TC underflow */) { + if (0) { + /* TODO: TC underflow */ env->CP0_VPEControl &=3D ~(0x7 << CP0VPECo_EXCPT); do_raise_exception(env, EXCP_THREAD, GETPC()); } else { - // TODO: Deallocate TC + /* TODO: Deallocate TC */ } } else if (arg1 > 0) { /* Yield qualifier inputs not implemented. */ @@ -2193,8 +2261,10 @@ target_ulong helper_evp(CPUMIPSState *env) CPU_FOREACH(other_cs) { MIPSCPU *other_cpu =3D MIPS_CPU(other_cs); if ((&other_cpu->env !=3D env) && !mips_vp_is_wfi(other_cpu)) { - /* If the VP is WFI, don't disturb its sleep. - * Otherwise, wake it up. */ + /* + * If the VP is WFI, don't disturb its sleep. + * Otherwise, wake it up. + */ mips_vpe_wake(other_cpu); } } @@ -2206,7 +2276,7 @@ target_ulong helper_evp(CPUMIPSState *env) =20 #ifndef CONFIG_USER_ONLY /* TLB management */ -static void r4k_mips_tlb_flush_extra (CPUMIPSState *env, int first) +static void r4k_mips_tlb_flush_extra(CPUMIPSState *env, int first) { /* Discard entries from env->tlb[first] onwards. */ while (env->tlb->tlb_in_use > first) { @@ -2308,8 +2378,10 @@ void r4k_helper_tlbwi(CPUMIPSState *env) XI1 =3D (env->CP0_EntryLo1 >> CP0EnLo_XI) &1; RI1 =3D (env->CP0_EntryLo1 >> CP0EnLo_RI) &1; =20 - /* Discard cached TLB entries, unless tlbwi is just upgrading access - permissions on the current entry. */ + /* + * Discard cached TLB entries, unless tlbwi is just upgrading access + * permissions on the current entry. + */ if (tlb->VPN !=3D VPN || tlb->ASID !=3D ASID || tlb->G !=3D G || (!tlb->EHINV && EHINV) || (tlb->V0 && !V0) || (tlb->D0 && !D0) || @@ -2370,7 +2442,7 @@ void r4k_helper_tlbp(CPUMIPSState *env) #endif /* Check ASID, virtual page number & size */ if ((tlb->G =3D=3D 1 || tlb->ASID =3D=3D ASID) && VPN =3D=3D t= ag) { - r4k_mips_tlb_flush_extra (env, i); + r4k_mips_tlb_flush_extra(env, i); break; } } @@ -2400,8 +2472,9 @@ void r4k_helper_tlbr(CPUMIPSState *env) tlb =3D &env->tlb->mmu.r4k.tlb[idx]; =20 /* If this will change the current ASID, flush qemu's TLB. */ - if (ASID !=3D tlb->ASID) + if (ASID !=3D tlb->ASID) { cpu_mips_tlb_flush(env); + } =20 r4k_mips_tlb_flush_extra(env, env->tlb->nb_tlb); =20 @@ -2476,10 +2549,12 @@ static void debug_pre_eret(CPUMIPSState *env) if (qemu_loglevel_mask(CPU_LOG_EXEC)) { qemu_log("ERET: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx, env->active_tc.PC, env->CP0_EPC); - if (env->CP0_Status & (1 << CP0St_ERL)) + if (env->CP0_Status & (1 << CP0St_ERL)) { qemu_log(" ErrorEPC " TARGET_FMT_lx, env->CP0_ErrorEPC); - if (env->hflags & MIPS_HFLAG_DM) + } + if (env->hflags & MIPS_HFLAG_DM) { qemu_log(" DEPC " TARGET_FMT_lx, env->CP0_DEPC); + } qemu_log("\n"); } } @@ -2489,17 +2564,25 @@ static void debug_post_eret(CPUMIPSState *env) if (qemu_loglevel_mask(CPU_LOG_EXEC)) { qemu_log(" =3D> PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx, env->active_tc.PC, env->CP0_EPC); - if (env->CP0_Status & (1 << CP0St_ERL)) + if (env->CP0_Status & (1 << CP0St_ERL)) { qemu_log(" ErrorEPC " TARGET_FMT_lx, env->CP0_ErrorEPC); - if (env->hflags & MIPS_HFLAG_DM) + } + if (env->hflags & MIPS_HFLAG_DM) { qemu_log(" DEPC " TARGET_FMT_lx, env->CP0_DEPC); + } switch (cpu_mmu_index(env, false)) { case 3: qemu_log(", ERL\n"); break; - case MIPS_HFLAG_UM: qemu_log(", UM\n"); break; - case MIPS_HFLAG_SM: qemu_log(", SM\n"); break; - case MIPS_HFLAG_KM: qemu_log("\n"); break; + case MIPS_HFLAG_UM: + qemu_log(", UM\n"); + break; + case MIPS_HFLAG_SM: + qemu_log(", SM\n"); + break; + case MIPS_HFLAG_KM: + qemu_log("\n"); + break; default: cpu_abort(env_cpu(env), "Invalid MMU mode!\n"); break; @@ -2609,8 +2692,9 @@ void helper_pmon(CPUMIPSState *env, int function) function /=3D 2; switch (function) { case 2: /* TODO: char inbyte(int waitflag); */ - if (env->active_tc.gpr[4] =3D=3D 0) + if (env->active_tc.gpr[4] =3D=3D 0) { env->active_tc.gpr[2] =3D -1; + } /* Fall through */ case 11: /* TODO: char inbyte (void); */ env->active_tc.gpr[2] =3D -1; @@ -2636,8 +2720,10 @@ void helper_wait(CPUMIPSState *env) =20 cs->halted =3D 1; cpu_reset_interrupt(cs, CPU_INTERRUPT_WAKE); - /* Last instruction in the block, PC was updated before - - no need to recover PC and icount */ + /* + * Last instruction in the block, PC was updated before + * - no need to recover PC and icount. + */ raise_exception(env, EXCP_HLT); } =20 @@ -2731,13 +2817,15 @@ target_ulong helper_cfc1(CPUMIPSState *env, uint32_= t reg) } break; case 25: - arg1 =3D ((env->active_fpu.fcr31 >> 24) & 0xfe) | ((env->active_fp= u.fcr31 >> 23) & 0x1); + arg1 =3D ((env->active_fpu.fcr31 >> 24) & 0xfe) | + ((env->active_fpu.fcr31 >> 23) & 0x1); break; case 26: arg1 =3D env->active_fpu.fcr31 & 0x0003f07c; break; case 28: - arg1 =3D (env->active_fpu.fcr31 & 0x00000f83) | ((env->active_fpu.= fcr31 >> 22) & 0x4); + arg1 =3D (env->active_fpu.fcr31 & 0x00000f83) | + ((env->active_fpu.fcr31 >> 22) & 0x4); break; default: arg1 =3D (int32_t)env->active_fpu.fcr31; @@ -2802,19 +2890,24 @@ void helper_ctc1(CPUMIPSState *env, target_ulong ar= g1, uint32_t fs, uint32_t rt) if ((env->insn_flags & ISA_MIPS32R6) || (arg1 & 0xffffff00)) { return; } - env->active_fpu.fcr31 =3D (env->active_fpu.fcr31 & 0x017fffff) | (= (arg1 & 0xfe) << 24) | - ((arg1 & 0x1) << 23); + env->active_fpu.fcr31 =3D (env->active_fpu.fcr31 & 0x017fffff) | + ((arg1 & 0xfe) << 24) | + ((arg1 & 0x1) << 23); break; case 26: - if (arg1 & 0x007c0000) + if (arg1 & 0x007c0000) { return; - env->active_fpu.fcr31 =3D (env->active_fpu.fcr31 & 0xfffc0f83) | (= arg1 & 0x0003f07c); + } + env->active_fpu.fcr31 =3D (env->active_fpu.fcr31 & 0xfffc0f83) | + (arg1 & 0x0003f07c); break; case 28: - if (arg1 & 0x007c0000) + if (arg1 & 0x007c0000) { return; - env->active_fpu.fcr31 =3D (env->active_fpu.fcr31 & 0xfefff07c) | (= arg1 & 0x00000f83) | - ((arg1 & 0x4) << 22); + } + env->active_fpu.fcr31 =3D (env->active_fpu.fcr31 & 0xfefff07c) | + (arg1 & 0x00000f83) | + ((arg1 & 0x4) << 22); break; case 31: env->active_fpu.fcr31 =3D (arg1 & env->active_fpu.fcr31_rw_bitmask= ) | @@ -2828,8 +2921,10 @@ void helper_ctc1(CPUMIPSState *env, target_ulong arg= 1, uint32_t fs, uint32_t rt) } restore_fp_status(env); set_float_exception_flags(0, &env->active_fpu.fp_status); - if ((GET_FP_ENABLE(env->active_fpu.fcr31) | 0x20) & GET_FP_CAUSE(env->= active_fpu.fcr31)) + if ((GET_FP_ENABLE(env->active_fpu.fcr31) | 0x20) & + GET_FP_CAUSE(env->active_fpu.fcr31)) { do_raise_exception(env, EXCP_FPE, GETPC()); + } } =20 int ieee_ex_to_mips(int xcpt) @@ -2857,7 +2952,8 @@ int ieee_ex_to_mips(int xcpt) =20 static inline void update_fcr31(CPUMIPSState *env, uintptr_t pc) { - int tmp =3D ieee_ex_to_mips(get_float_exception_flags(&env->active_fpu= .fp_status)); + int tmp =3D ieee_ex_to_mips(get_float_exception_flags( + &env->active_fpu.fp_status)); =20 SET_FP_CAUSE(env->active_fpu.fcr31, tmp); =20 @@ -2872,10 +2968,12 @@ static inline void update_fcr31(CPUMIPSState *env, = uintptr_t pc) } } =20 -/* Float support. - Single precition routines have a "s" suffix, double precision a - "d" suffix, 32bit integer "w", 64bit integer "l", paired single "ps", - paired single lower "pl", paired single upper "pu". */ +/* + * Float support. + * Single precition routines have a "s" suffix, double precision a + * "d" suffix, 32bit integer "w", 64bit integer "l", paired single "ps", + * paired single lower "pl", paired single upper "pu". + */ =20 /* unary operations, modifying fp status */ uint64_t helper_float_sqrt_d(CPUMIPSState *env, uint64_t fdt0) @@ -3056,7 +3154,8 @@ uint64_t helper_float_round_l_d(CPUMIPSState *env, ui= nt64_t fdt0) { uint64_t dt2; =20 - set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_= status); + set_float_rounding_mode(float_round_nearest_even, + &env->active_fpu.fp_status); dt2 =3D float64_to_int64(fdt0, &env->active_fpu.fp_status); restore_rounding_mode(env); if (get_float_exception_flags(&env->active_fpu.fp_status) @@ -3071,7 +3170,8 @@ uint64_t helper_float_round_l_s(CPUMIPSState *env, ui= nt32_t fst0) { uint64_t dt2; =20 - set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_= status); + set_float_rounding_mode(float_round_nearest_even, + &env->active_fpu.fp_status); dt2 =3D float32_to_int64(fst0, &env->active_fpu.fp_status); restore_rounding_mode(env); if (get_float_exception_flags(&env->active_fpu.fp_status) @@ -3086,7 +3186,8 @@ uint32_t helper_float_round_w_d(CPUMIPSState *env, ui= nt64_t fdt0) { uint32_t wt2; =20 - set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_= status); + set_float_rounding_mode(float_round_nearest_even, + &env->active_fpu.fp_status); wt2 =3D float64_to_int32(fdt0, &env->active_fpu.fp_status); restore_rounding_mode(env); if (get_float_exception_flags(&env->active_fpu.fp_status) @@ -3101,7 +3202,8 @@ uint32_t helper_float_round_w_s(CPUMIPSState *env, ui= nt32_t fst0) { uint32_t wt2; =20 - set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_= status); + set_float_rounding_mode(float_round_nearest_even, + &env->active_fpu.fp_status); wt2 =3D float32_to_int32(fst0, &env->active_fpu.fp_status); restore_rounding_mode(env); if (get_float_exception_flags(&env->active_fpu.fp_status) @@ -3116,7 +3218,8 @@ uint64_t helper_float_trunc_l_d(CPUMIPSState *env, ui= nt64_t fdt0) { uint64_t dt2; =20 - dt2 =3D float64_to_int64_round_to_zero(fdt0, &env->active_fpu.fp_statu= s); + dt2 =3D float64_to_int64_round_to_zero(fdt0, + &env->active_fpu.fp_status); if (get_float_exception_flags(&env->active_fpu.fp_status) & (float_flag_invalid | float_flag_overflow)) { dt2 =3D FP_TO_INT64_OVERFLOW; @@ -3697,7 +3800,8 @@ uint64_t helper_float_recip1_ps(CPUMIPSState *env, ui= nt64_t fdt0) uint32_t fst2; uint32_t fsth2; =20 - fst2 =3D float32_div(float32_one, fdt0 & 0XFFFFFFFF, &env->active_fpu.= fp_status); + fst2 =3D float32_div(float32_one, fdt0 & 0XFFFFFFFF, + &env->active_fpu.fp_status); fsth2 =3D float32_div(float32_one, fdt0 >> 32, &env->active_fpu.fp_sta= tus); update_fcr31(env, GETPC()); return ((uint64_t)fsth2 << 32) | fst2; @@ -3737,8 +3841,8 @@ uint64_t helper_float_rsqrt1_ps(CPUMIPSState *env, ui= nt64_t fdt0) } =20 #define FLOAT_RINT(name, bits) = \ -uint ## bits ## _t helper_float_ ## name (CPUMIPSState *env, = \ - uint ## bits ## _t fs) = \ +uint ## bits ## _t helper_float_ ## name(CPUMIPSState *env, = \ + uint ## bits ## _t fs) = \ { = \ uint ## bits ## _t fdret; = \ = \ @@ -3763,8 +3867,8 @@ FLOAT_RINT(rint_d, 64) #define FLOAT_CLASS_POSITIVE_ZERO 0x200 =20 #define FLOAT_CLASS(name, bits) \ -uint ## bits ## _t float_ ## name (uint ## bits ## _t arg, \ - float_status *status) \ +uint ## bits ## _t float_ ## name(uint ## bits ## _t arg, \ + float_status *status) \ { \ if (float ## bits ## _is_signaling_nan(arg, status)) { \ return FLOAT_CLASS_SIGNALING_NAN; \ @@ -3793,8 +3897,8 @@ uint ## bits ## _t float_ ## name (uint ## bits ## _t= arg, \ } \ } \ \ -uint ## bits ## _t helper_float_ ## name (CPUMIPSState *env, \ - uint ## bits ## _t arg) \ +uint ## bits ## _t helper_float_ ## name(CPUMIPSState *env, \ + uint ## bits ## _t arg) \ { \ return float_ ## name(arg, &env->active_fpu.fp_status); \ } @@ -3810,7 +3914,7 @@ uint64_t helper_float_ ## name ## _d(CPUMIPSState *en= v, \ { \ uint64_t dt2; \ \ - dt2 =3D float64_ ## name (fdt0, fdt1, &env->active_fpu.fp_status); = \ + dt2 =3D float64_ ## name(fdt0, fdt1, &env->active_fpu.fp_status);\ update_fcr31(env, GETPC()); \ return dt2; \ } \ @@ -3820,7 +3924,7 @@ uint32_t helper_float_ ## name ## _s(CPUMIPSState *en= v, \ { \ uint32_t wt2; \ \ - wt2 =3D float32_ ## name (fst0, fst1, &env->active_fpu.fp_status); = \ + wt2 =3D float32_ ## name(fst0, fst1, &env->active_fpu.fp_status);\ update_fcr31(env, GETPC()); \ return wt2; \ } \ @@ -3836,8 +3940,8 @@ uint64_t helper_float_ ## name ## _ps(CPUMIPSState *e= nv, \ uint32_t wt2; \ uint32_t wth2; \ \ - wt2 =3D float32_ ## name (fst0, fst1, &env->active_fpu.fp_status); = \ - wth2 =3D float32_ ## name (fsth0, fsth1, &env->active_fpu.fp_status); = \ + wt2 =3D float32_ ## name(fst0, fst1, &env->active_fpu.fp_status); \ + wth2 =3D float32_ ## name(fsth0, fsth1, &env->active_fpu.fp_status); \ update_fcr31(env, GETPC()); \ return ((uint64_t)wth2 << 32) | wt2; \ } @@ -3852,7 +3956,8 @@ FLOAT_BINOP(div) uint64_t helper_float_recip2_d(CPUMIPSState *env, uint64_t fdt0, uint64_t = fdt2) { fdt2 =3D float64_mul(fdt0, fdt2, &env->active_fpu.fp_status); - fdt2 =3D float64_chs(float64_sub(fdt2, float64_one, &env->active_fpu.f= p_status)); + fdt2 =3D float64_chs(float64_sub(fdt2, float64_one, + &env->active_fpu.fp_status)); update_fcr31(env, GETPC()); return fdt2; } @@ -3860,7 +3965,8 @@ uint64_t helper_float_recip2_d(CPUMIPSState *env, uin= t64_t fdt0, uint64_t fdt2) uint32_t helper_float_recip2_s(CPUMIPSState *env, uint32_t fst0, uint32_t = fst2) { fst2 =3D float32_mul(fst0, fst2, &env->active_fpu.fp_status); - fst2 =3D float32_chs(float32_sub(fst2, float32_one, &env->active_fpu.f= p_status)); + fst2 =3D float32_chs(float32_sub(fst2, float32_one, + &env->active_fpu.fp_status)); update_fcr31(env, GETPC()); return fst2; } @@ -3874,8 +3980,10 @@ uint64_t helper_float_recip2_ps(CPUMIPSState *env, u= int64_t fdt0, uint64_t fdt2) =20 fst2 =3D float32_mul(fst0, fst2, &env->active_fpu.fp_status); fsth2 =3D float32_mul(fsth0, fsth2, &env->active_fpu.fp_status); - fst2 =3D float32_chs(float32_sub(fst2, float32_one, &env->active_fpu.f= p_status)); - fsth2 =3D float32_chs(float32_sub(fsth2, float32_one, &env->active_fpu= .fp_status)); + fst2 =3D float32_chs(float32_sub(fst2, float32_one, + &env->active_fpu.fp_status)); + fsth2 =3D float32_chs(float32_sub(fsth2, float32_one, + &env->active_fpu.fp_status)); update_fcr31(env, GETPC()); return ((uint64_t)fsth2 << 32) | fst2; } @@ -3884,7 +3992,8 @@ uint64_t helper_float_rsqrt2_d(CPUMIPSState *env, uin= t64_t fdt0, uint64_t fdt2) { fdt2 =3D float64_mul(fdt0, fdt2, &env->active_fpu.fp_status); fdt2 =3D float64_sub(fdt2, float64_one, &env->active_fpu.fp_status); - fdt2 =3D float64_chs(float64_div(fdt2, FLOAT_TWO64, &env->active_fpu.f= p_status)); + fdt2 =3D float64_chs(float64_div(fdt2, FLOAT_TWO64, + &env->active_fpu.fp_status)); update_fcr31(env, GETPC()); return fdt2; } @@ -3893,7 +4002,8 @@ uint32_t helper_float_rsqrt2_s(CPUMIPSState *env, uin= t32_t fst0, uint32_t fst2) { fst2 =3D float32_mul(fst0, fst2, &env->active_fpu.fp_status); fst2 =3D float32_sub(fst2, float32_one, &env->active_fpu.fp_status); - fst2 =3D float32_chs(float32_div(fst2, FLOAT_TWO32, &env->active_fpu.f= p_status)); + fst2 =3D float32_chs(float32_div(fst2, FLOAT_TWO32, + &env->active_fpu.fp_status)); update_fcr31(env, GETPC()); return fst2; } @@ -3909,8 +4019,10 @@ uint64_t helper_float_rsqrt2_ps(CPUMIPSState *env, u= int64_t fdt0, uint64_t fdt2) fsth2 =3D float32_mul(fsth0, fsth2, &env->active_fpu.fp_status); fst2 =3D float32_sub(fst2, float32_one, &env->active_fpu.fp_status); fsth2 =3D float32_sub(fsth2, float32_one, &env->active_fpu.fp_status); - fst2 =3D float32_chs(float32_div(fst2, FLOAT_TWO32, &env->active_fpu.f= p_status)); - fsth2 =3D float32_chs(float32_div(fsth2, FLOAT_TWO32, &env->active_fpu= .fp_status)); + fst2 =3D float32_chs(float32_div(fst2, FLOAT_TWO32, + &env->active_fpu.fp_status)); + fsth2 =3D float32_chs(float32_div(fsth2, FLOAT_TWO32, + &env->active_fpu.fp_status)); update_fcr31(env, GETPC()); return ((uint64_t)fsth2 << 32) | fst2; } @@ -3924,8 +4036,8 @@ uint64_t helper_float_addr_ps(CPUMIPSState *env, uint= 64_t fdt0, uint64_t fdt1) uint32_t fst2; uint32_t fsth2; =20 - fst2 =3D float32_add (fst0, fsth0, &env->active_fpu.fp_status); - fsth2 =3D float32_add (fst1, fsth1, &env->active_fpu.fp_status); + fst2 =3D float32_add(fst0, fsth0, &env->active_fpu.fp_status); + fsth2 =3D float32_add(fst1, fsth1, &env->active_fpu.fp_status); update_fcr31(env, GETPC()); return ((uint64_t)fsth2 << 32) | fst2; } @@ -3939,16 +4051,16 @@ uint64_t helper_float_mulr_ps(CPUMIPSState *env, ui= nt64_t fdt0, uint64_t fdt1) uint32_t fst2; uint32_t fsth2; =20 - fst2 =3D float32_mul (fst0, fsth0, &env->active_fpu.fp_status); - fsth2 =3D float32_mul (fst1, fsth1, &env->active_fpu.fp_status); + fst2 =3D float32_mul(fst0, fsth0, &env->active_fpu.fp_status); + fsth2 =3D float32_mul(fst1, fsth1, &env->active_fpu.fp_status); update_fcr31(env, GETPC()); return ((uint64_t)fsth2 << 32) | fst2; } =20 #define FLOAT_MINMAX(name, bits, minmaxfunc) \ -uint ## bits ## _t helper_float_ ## name (CPUMIPSState *env, \ - uint ## bits ## _t fs, \ - uint ## bits ## _t ft) \ +uint ## bits ## _t helper_float_ ## name(CPUMIPSState *env, \ + uint ## bits ## _t fs, \ + uint ## bits ## _t ft) \ { \ uint ## bits ## _t fdret; \ \ @@ -4026,10 +4138,10 @@ FLOAT_FMA(nmsub, float_muladd_negate_result | float= _muladd_negate_c) #undef FLOAT_FMA =20 #define FLOAT_FMADDSUB(name, bits, muladd_arg) \ -uint ## bits ## _t helper_float_ ## name (CPUMIPSState *env, \ - uint ## bits ## _t fs, \ - uint ## bits ## _t ft, \ - uint ## bits ## _t fd) \ +uint ## bits ## _t helper_float_ ## name(CPUMIPSState *env, \ + uint ## bits ## _t fs, \ + uint ## bits ## _t ft, \ + uint ## bits ## _t fd) \ { \ uint ## bits ## _t fdret; \ \ @@ -4072,26 +4184,58 @@ void helper_cmpabs_d_ ## op(CPUMIPSState *env, uint= 64_t fdt0, \ CLEAR_FP_COND(cc, env->active_fpu); \ } =20 -/* NOTE: the comma operator will make "cond" to eval to false, - * but float64_unordered_quiet() is still called. */ -FOP_COND_D(f, (float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_s= tatus), 0)) -FOP_COND_D(un, float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_st= atus)) -FOP_COND_D(eq, float64_eq_quiet(fdt0, fdt1, &env->active_fpu.fp_status)) -FOP_COND_D(ueq, float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_st= atus) || float64_eq_quiet(fdt0, fdt1, &env->active_fpu.fp_status)) -FOP_COND_D(olt, float64_lt_quiet(fdt0, fdt1, &env->active_fpu.fp_status)) -FOP_COND_D(ult, float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_st= atus) || float64_lt_quiet(fdt0, fdt1, &env->active_fpu.fp_status)) -FOP_COND_D(ole, float64_le_quiet(fdt0, fdt1, &env->active_fpu.fp_status)) -FOP_COND_D(ule, float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_st= atus) || float64_le_quiet(fdt0, fdt1, &env->active_fpu.fp_status)) -/* NOTE: the comma operator will make "cond" to eval to false, - * but float64_unordered() is still called. */ -FOP_COND_D(sf, (float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status)= , 0)) -FOP_COND_D(ngle,float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status)) -FOP_COND_D(seq, float64_eq(fdt0, fdt1, &env->active_fpu.fp_status)) -FOP_COND_D(ngl, float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status) = || float64_eq(fdt0, fdt1, &env->active_fpu.fp_status)) -FOP_COND_D(lt, float64_lt(fdt0, fdt1, &env->active_fpu.fp_status)) -FOP_COND_D(nge, float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status) = || float64_lt(fdt0, fdt1, &env->active_fpu.fp_status)) -FOP_COND_D(le, float64_le(fdt0, fdt1, &env->active_fpu.fp_status)) -FOP_COND_D(ngt, float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status) = || float64_le(fdt0, fdt1, &env->active_fpu.fp_status)) +/* + * NOTE: the comma operator will make "cond" to eval to false, + * but float64_unordered_quiet() is still called. + */ +FOP_COND_D(f, (float64_unordered_quiet(fdt1, fdt0, + &env->active_fpu.fp_status), 0)) +FOP_COND_D(un, float64_unordered_quiet(fdt1, fdt0, + &env->active_fpu.fp_status)) +FOP_COND_D(eq, float64_eq_quiet(fdt0, fdt1, + &env->active_fpu.fp_status)) +FOP_COND_D(ueq, float64_unordered_quiet(fdt1, fdt0, + &env->active_fpu.fp_status) + || float64_eq_quiet(fdt0, fdt1, + &env->active_fpu.fp_status)) +FOP_COND_D(olt, float64_lt_quiet(fdt0, fdt1, + &env->active_fpu.fp_status)) +FOP_COND_D(ult, float64_unordered_quiet(fdt1, fdt0, + &env->active_fpu.fp_status) + || float64_lt_quiet(fdt0, fdt1, + &env->active_fpu.fp_status)) +FOP_COND_D(ole, float64_le_quiet(fdt0, fdt1, + &env->active_fpu.fp_status)) +FOP_COND_D(ule, float64_unordered_quiet(fdt1, fdt0, + &env->active_fpu.fp_status) + || float64_le_quiet(fdt0, fdt1, + &env->active_fpu.fp_status)) +/* + * NOTE: the comma operator will make "cond" to eval to false, + * but float64_unordered() is still called. + */ +FOP_COND_D(sf, (float64_unordered(fdt1, fdt0, + &env->active_fpu.fp_status), 0)) +FOP_COND_D(ngle, float64_unordered(fdt1, fdt0, + &env->active_fpu.fp_status)) +FOP_COND_D(seq, float64_eq(fdt0, fdt1, + &env->active_fpu.fp_status)) +FOP_COND_D(ngl, float64_unordered(fdt1, fdt0, + &env->active_fpu.fp_status) + || float64_eq(fdt0, fdt1, + &env->active_fpu.fp_status)) +FOP_COND_D(lt, float64_lt(fdt0, fdt1, + &env->active_fpu.fp_status)) +FOP_COND_D(nge, float64_unordered(fdt1, fdt0, + &env->active_fpu.fp_status) + || float64_lt(fdt0, fdt1, + &env->active_fpu.fp_status)) +FOP_COND_D(le, float64_le(fdt0, fdt1, + &env->active_fpu.fp_status)) +FOP_COND_D(ngt, float64_unordered(fdt1, fdt0, + &env->active_fpu.fp_status) + || float64_le(fdt0, fdt1, + &env->active_fpu.fp_status)) =20 #define FOP_COND_S(op, cond) \ void helper_cmp_s_ ## op(CPUMIPSState *env, uint32_t fst0, \ @@ -4119,26 +4263,58 @@ void helper_cmpabs_s_ ## op(CPUMIPSState *env, uint= 32_t fst0, \ CLEAR_FP_COND(cc, env->active_fpu); \ } =20 -/* NOTE: the comma operator will make "cond" to eval to false, - * but float32_unordered_quiet() is still called. */ -FOP_COND_S(f, (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_s= tatus), 0)) -FOP_COND_S(un, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_st= atus)) -FOP_COND_S(eq, float32_eq_quiet(fst0, fst1, &env->active_fpu.fp_status)) -FOP_COND_S(ueq, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_st= atus) || float32_eq_quiet(fst0, fst1, &env->active_fpu.fp_status)) -FOP_COND_S(olt, float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status)) -FOP_COND_S(ult, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_st= atus) || float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status)) -FOP_COND_S(ole, float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status)) -FOP_COND_S(ule, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_st= atus) || float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status)) -/* NOTE: the comma operator will make "cond" to eval to false, - * but float32_unordered() is still called. */ -FOP_COND_S(sf, (float32_unordered(fst1, fst0, &env->active_fpu.fp_status)= , 0)) -FOP_COND_S(ngle,float32_unordered(fst1, fst0, &env->active_fpu.fp_status)) -FOP_COND_S(seq, float32_eq(fst0, fst1, &env->active_fpu.fp_status)) -FOP_COND_S(ngl, float32_unordered(fst1, fst0, &env->active_fpu.fp_status) = || float32_eq(fst0, fst1, &env->active_fpu.fp_status)) -FOP_COND_S(lt, float32_lt(fst0, fst1, &env->active_fpu.fp_status)) -FOP_COND_S(nge, float32_unordered(fst1, fst0, &env->active_fpu.fp_status) = || float32_lt(fst0, fst1, &env->active_fpu.fp_status)) -FOP_COND_S(le, float32_le(fst0, fst1, &env->active_fpu.fp_status)) -FOP_COND_S(ngt, float32_unordered(fst1, fst0, &env->active_fpu.fp_status) = || float32_le(fst0, fst1, &env->active_fpu.fp_status)) +/* + * NOTE: the comma operator will make "cond" to eval to false, + * but float32_unordered_quiet() is still called. + */ +FOP_COND_S(f, (float32_unordered_quiet(fst1, fst0, + &env->active_fpu.fp_status), 0)) +FOP_COND_S(un, float32_unordered_quiet(fst1, fst0, + &env->active_fpu.fp_status)) +FOP_COND_S(eq, float32_eq_quiet(fst0, fst1, + &env->active_fpu.fp_status)) +FOP_COND_S(ueq, float32_unordered_quiet(fst1, fst0, + &env->active_fpu.fp_status) + || float32_eq_quiet(fst0, fst1, + &env->active_fpu.fp_status)) +FOP_COND_S(olt, float32_lt_quiet(fst0, fst1, + &env->active_fpu.fp_status)) +FOP_COND_S(ult, float32_unordered_quiet(fst1, fst0, + &env->active_fpu.fp_status) + || float32_lt_quiet(fst0, fst1, + &env->active_fpu.fp_status)) +FOP_COND_S(ole, float32_le_quiet(fst0, fst1, + &env->active_fpu.fp_status)) +FOP_COND_S(ule, float32_unordered_quiet(fst1, fst0, + &env->active_fpu.fp_status) + || float32_le_quiet(fst0, fst1, + &env->active_fpu.fp_status)) +/* + * NOTE: the comma operator will make "cond" to eval to false, + * but float32_unordered() is still called. + */ +FOP_COND_S(sf, (float32_unordered(fst1, fst0, + &env->active_fpu.fp_status), 0)) +FOP_COND_S(ngle, float32_unordered(fst1, fst0, + &env->active_fpu.fp_status)) +FOP_COND_S(seq, float32_eq(fst0, fst1, + &env->active_fpu.fp_status)) +FOP_COND_S(ngl, float32_unordered(fst1, fst0, + &env->active_fpu.fp_status) + || float32_eq(fst0, fst1, + &env->active_fpu.fp_status)) +FOP_COND_S(lt, float32_lt(fst0, fst1, + &env->active_fpu.fp_status)) +FOP_COND_S(nge, float32_unordered(fst1, fst0, + &env->active_fpu.fp_status) + || float32_lt(fst0, fst1, + &env->active_fpu.fp_status)) +FOP_COND_S(le, float32_le(fst0, fst1, + &env->active_fpu.fp_status)) +FOP_COND_S(ngt, float32_unordered(fst1, fst0, + &env->active_fpu.fp_status) + || float32_le(fst0, fst1, + &env->active_fpu.fp_status)) =20 #define FOP_COND_PS(op, condl, condh) \ void helper_cmp_ps_ ## op(CPUMIPSState *env, uint64_t fdt0, \ @@ -4184,47 +4360,107 @@ void helper_cmpabs_ps_ ## op(CPUMIPSState *env, ui= nt64_t fdt0, \ CLEAR_FP_COND(cc + 1, env->active_fpu); \ } =20 -/* NOTE: the comma operator will make "cond" to eval to false, - * but float32_unordered_quiet() is still called. */ -FOP_COND_PS(f, (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_= status), 0), - (float32_unordered_quiet(fsth1, fsth0, &env->active_fpu.f= p_status), 0)) -FOP_COND_PS(un, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_s= tatus), - float32_unordered_quiet(fsth1, fsth0, &env->active_fpu.fp= _status)) -FOP_COND_PS(eq, float32_eq_quiet(fst0, fst1, &env->active_fpu.fp_status), - float32_eq_quiet(fsth0, fsth1, &env->active_fpu.fp_status= )) -FOP_COND_PS(ueq, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_s= tatus) || float32_eq_quiet(fst0, fst1, &env->active_fpu.fp_status), - float32_unordered_quiet(fsth1, fsth0, &env->active_fpu.fp= _status) || float32_eq_quiet(fsth0, fsth1, &env->active_fpu.fp_status)) -FOP_COND_PS(olt, float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status), - float32_lt_quiet(fsth0, fsth1, &env->active_fpu.fp_status= )) -FOP_COND_PS(ult, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_s= tatus) || float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status), - float32_unordered_quiet(fsth1, fsth0, &env->active_fpu.fp= _status) || float32_lt_quiet(fsth0, fsth1, &env->active_fpu.fp_status)) -FOP_COND_PS(ole, float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status), - float32_le_quiet(fsth0, fsth1, &env->active_fpu.fp_status= )) -FOP_COND_PS(ule, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_s= tatus) || float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status), - float32_unordered_quiet(fsth1, fsth0, &env->active_fpu.fp= _status) || float32_le_quiet(fsth0, fsth1, &env->active_fpu.fp_status)) -/* NOTE: the comma operator will make "cond" to eval to false, - * but float32_unordered() is still called. */ -FOP_COND_PS(sf, (float32_unordered(fst1, fst0, &env->active_fpu.fp_status= ), 0), - (float32_unordered(fsth1, fsth0, &env->active_fpu.fp_stat= us), 0)) -FOP_COND_PS(ngle,float32_unordered(fst1, fst0, &env->active_fpu.fp_status), - float32_unordered(fsth1, fsth0, &env->active_fpu.fp_statu= s)) -FOP_COND_PS(seq, float32_eq(fst0, fst1, &env->active_fpu.fp_status), - float32_eq(fsth0, fsth1, &env->active_fpu.fp_status)) -FOP_COND_PS(ngl, float32_unordered(fst1, fst0, &env->active_fpu.fp_status)= || float32_eq(fst0, fst1, &env->active_fpu.fp_status), - float32_unordered(fsth1, fsth0, &env->active_fpu.fp_statu= s) || float32_eq(fsth0, fsth1, &env->active_fpu.fp_status)) -FOP_COND_PS(lt, float32_lt(fst0, fst1, &env->active_fpu.fp_status), - float32_lt(fsth0, fsth1, &env->active_fpu.fp_status)) -FOP_COND_PS(nge, float32_unordered(fst1, fst0, &env->active_fpu.fp_status)= || float32_lt(fst0, fst1, &env->active_fpu.fp_status), - float32_unordered(fsth1, fsth0, &env->active_fpu.fp_statu= s) || float32_lt(fsth0, fsth1, &env->active_fpu.fp_status)) -FOP_COND_PS(le, float32_le(fst0, fst1, &env->active_fpu.fp_status), - float32_le(fsth0, fsth1, &env->active_fpu.fp_status)) -FOP_COND_PS(ngt, float32_unordered(fst1, fst0, &env->active_fpu.fp_status)= || float32_le(fst0, fst1, &env->active_fpu.fp_status), - float32_unordered(fsth1, fsth0, &env->active_fpu.fp_statu= s) || float32_le(fsth0, fsth1, &env->active_fpu.fp_status)) +/* + * NOTE: the comma operator will make "cond" to eval to false, + * but float32_unordered_quiet() is still called. + */ +FOP_COND_PS(f, (float32_unordered_quiet(fst1, fst0, + &env->active_fpu.fp_status), 0), + (float32_unordered_quiet(fsth1, fsth0, + &env->active_fpu.fp_status), 0)) +FOP_COND_PS(un, float32_unordered_quiet(fst1, fst0, + &env->active_fpu.fp_status), + float32_unordered_quiet(fsth1, fsth0, + &env->active_fpu.fp_status)) +FOP_COND_PS(eq, float32_eq_quiet(fst0, fst1, + &env->active_fpu.fp_status), + float32_eq_quiet(fsth0, fsth1, + &env->active_fpu.fp_status)) +FOP_COND_PS(ueq, float32_unordered_quiet(fst1, fst0, + &env->active_fpu.fp_status) + || float32_eq_quiet(fst0, fst1, + &env->active_fpu.fp_status), + float32_unordered_quiet(fsth1, fsth0, + &env->active_fpu.fp_status) + || float32_eq_quiet(fsth0, fsth1, + &env->active_fpu.fp_status)) +FOP_COND_PS(olt, float32_lt_quiet(fst0, fst1, + &env->active_fpu.fp_status), + float32_lt_quiet(fsth0, fsth1, + &env->active_fpu.fp_status)) +FOP_COND_PS(ult, float32_unordered_quiet(fst1, fst0, + &env->active_fpu.fp_status) + || float32_lt_quiet(fst0, fst1, + &env->active_fpu.fp_status), + float32_unordered_quiet(fsth1, fsth0, + &env->active_fpu.fp_status) + || float32_lt_quiet(fsth0, fsth1, + &env->active_fpu.fp_status)) +FOP_COND_PS(ole, float32_le_quiet(fst0, fst1, + &env->active_fpu.fp_status), + float32_le_quiet(fsth0, fsth1, + &env->active_fpu.fp_status)) +FOP_COND_PS(ule, float32_unordered_quiet(fst1, fst0, + &env->active_fpu.fp_status) + || float32_le_quiet(fst0, fst1, + &env->active_fpu.fp_status), + float32_unordered_quiet(fsth1, fsth0, + &env->active_fpu.fp_status) + || float32_le_quiet(fsth0, fsth1, + &env->active_fpu.fp_status)) +/* + * NOTE: the comma operator will make "cond" to eval to false, + * but float32_unordered() is still called. + */ +FOP_COND_PS(sf, (float32_unordered(fst1, fst0, + &env->active_fpu.fp_status), 0), + (float32_unordered(fsth1, fsth0, + &env->active_fpu.fp_status), 0)) +FOP_COND_PS(ngle, float32_unordered(fst1, fst0, + &env->active_fpu.fp_status), + float32_unordered(fsth1, fsth0, + &env->active_fpu.fp_status)) +FOP_COND_PS(seq, float32_eq(fst0, fst1, + &env->active_fpu.fp_status), + float32_eq(fsth0, fsth1, + &env->active_fpu.fp_status)) +FOP_COND_PS(ngl, float32_unordered(fst1, fst0, + &env->active_fpu.fp_status) + || float32_eq(fst0, fst1, + &env->active_fpu.fp_status), + float32_unordered(fsth1, fsth0, + &env->active_fpu.fp_status) + || float32_eq(fsth0, fsth1, + &env->active_fpu.fp_status)) +FOP_COND_PS(lt, float32_lt(fst0, fst1, + &env->active_fpu.fp_status), + float32_lt(fsth0, fsth1, + &env->active_fpu.fp_status)) +FOP_COND_PS(nge, float32_unordered(fst1, fst0, + &env->active_fpu.fp_status) + || float32_lt(fst0, fst1, + &env->active_fpu.fp_status), + float32_unordered(fsth1, fsth0, + &env->active_fpu.fp_status) + || float32_lt(fsth0, fsth1, + &env->active_fpu.fp_status)) +FOP_COND_PS(le, float32_le(fst0, fst1, + &env->active_fpu.fp_status), + float32_le(fsth0, fsth1, + &env->active_fpu.fp_status)) +FOP_COND_PS(ngt, float32_unordered(fst1, fst0, + &env->active_fpu.fp_status) + || float32_le(fst0, fst1, + &env->active_fpu.fp_status), + float32_unordered(fsth1, fsth0, + &env->active_fpu.fp_status) + || float32_le(fsth0, fsth1, + &env->active_fpu.fp_status)) =20 /* R6 compare operations */ #define FOP_CONDN_D(op, cond) \ -uint64_t helper_r6_cmp_d_ ## op(CPUMIPSState * env, uint64_t fdt0, \ - uint64_t fdt1) \ +uint64_t helper_r6_cmp_d_ ## op(CPUMIPSState *env, uint64_t fdt0, \ + uint64_t fdt1) \ { \ uint64_t c; \ c =3D cond; \ @@ -4236,50 +4472,90 @@ uint64_t helper_r6_cmp_d_ ## op(CPUMIPSState * env,= uint64_t fdt0, \ } \ } =20 -/* NOTE: the comma operator will make "cond" to eval to false, - * but float64_unordered_quiet() is still called. */ -FOP_CONDN_D(af, (float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_= status), 0)) -FOP_CONDN_D(un, (float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_= status))) -FOP_CONDN_D(eq, (float64_eq_quiet(fdt0, fdt1, &env->active_fpu.fp_status)= )) -FOP_CONDN_D(ueq, (float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_= status) - || float64_eq_quiet(fdt0, fdt1, &env->active_fpu.fp_stat= us))) -FOP_CONDN_D(lt, (float64_lt_quiet(fdt0, fdt1, &env->active_fpu.fp_status)= )) -FOP_CONDN_D(ult, (float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_= status) - || float64_lt_quiet(fdt0, fdt1, &env->active_fpu.fp_stat= us))) -FOP_CONDN_D(le, (float64_le_quiet(fdt0, fdt1, &env->active_fpu.fp_status)= )) -FOP_CONDN_D(ule, (float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_= status) - || float64_le_quiet(fdt0, fdt1, &env->active_fpu.fp_stat= us))) -/* NOTE: the comma operator will make "cond" to eval to false, - * but float64_unordered() is still called. */ -FOP_CONDN_D(saf, (float64_unordered(fdt1, fdt0, &env->active_fpu.fp_statu= s), 0)) -FOP_CONDN_D(sun, (float64_unordered(fdt1, fdt0, &env->active_fpu.fp_statu= s))) -FOP_CONDN_D(seq, (float64_eq(fdt0, fdt1, &env->active_fpu.fp_status))) -FOP_CONDN_D(sueq, (float64_unordered(fdt1, fdt0, &env->active_fpu.fp_statu= s) - || float64_eq(fdt0, fdt1, &env->active_fpu.fp_status))) -FOP_CONDN_D(slt, (float64_lt(fdt0, fdt1, &env->active_fpu.fp_status))) -FOP_CONDN_D(sult, (float64_unordered(fdt1, fdt0, &env->active_fpu.fp_statu= s) - || float64_lt(fdt0, fdt1, &env->active_fpu.fp_status))) -FOP_CONDN_D(sle, (float64_le(fdt0, fdt1, &env->active_fpu.fp_status))) -FOP_CONDN_D(sule, (float64_unordered(fdt1, fdt0, &env->active_fpu.fp_statu= s) - || float64_le(fdt0, fdt1, &env->active_fpu.fp_status))) -FOP_CONDN_D(or, (float64_le_quiet(fdt1, fdt0, &env->active_fpu.fp_status) - || float64_le_quiet(fdt0, fdt1, &env->active_fpu.fp_sta= tus))) -FOP_CONDN_D(une, (float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp= _status) - || float64_lt_quiet(fdt1, fdt0, &env->active_fpu.fp_sta= tus) - || float64_lt_quiet(fdt0, fdt1, &env->active_fpu.fp_sta= tus))) -FOP_CONDN_D(ne, (float64_lt_quiet(fdt1, fdt0, &env->active_fpu.fp_status) - || float64_lt_quiet(fdt0, fdt1, &env->active_fpu.fp_sta= tus))) -FOP_CONDN_D(sor, (float64_le(fdt1, fdt0, &env->active_fpu.fp_status) - || float64_le(fdt0, fdt1, &env->active_fpu.fp_status))) -FOP_CONDN_D(sune, (float64_unordered(fdt1, fdt0, &env->active_fpu.fp_statu= s) - || float64_lt(fdt1, fdt0, &env->active_fpu.fp_status) - || float64_lt(fdt0, fdt1, &env->active_fpu.fp_status))) -FOP_CONDN_D(sne, (float64_lt(fdt1, fdt0, &env->active_fpu.fp_status) - || float64_lt(fdt0, fdt1, &env->active_fpu.fp_status))) +/* + * NOTE: the comma operator will make "cond" to eval to false, + * but float64_unordered_quiet() is still called. + */ +FOP_CONDN_D(af, (float64_unordered_quiet(fdt1, fdt0, + &env->active_fpu.fp_status), 0)) +FOP_CONDN_D(un, (float64_unordered_quiet(fdt1, fdt0, + &env->active_fpu.fp_status))) +FOP_CONDN_D(eq, (float64_eq_quiet(fdt0, fdt1, + &env->active_fpu.fp_status))) +FOP_CONDN_D(ueq, (float64_unordered_quiet(fdt1, fdt0, + &env->active_fpu.fp_status) + || float64_eq_quiet(fdt0, fdt1, + &env->active_fpu.fp_status))) +FOP_CONDN_D(lt, (float64_lt_quiet(fdt0, fdt1, + &env->active_fpu.fp_status))) +FOP_CONDN_D(ult, (float64_unordered_quiet(fdt1, fdt0, + &env->active_fpu.fp_status) + || float64_lt_quiet(fdt0, fdt1, + &env->active_fpu.fp_status))) +FOP_CONDN_D(le, (float64_le_quiet(fdt0, fdt1, + &env->active_fpu.fp_status))) +FOP_CONDN_D(ule, (float64_unordered_quiet(fdt1, fdt0, + &env->active_fpu.fp_status) + || float64_le_quiet(fdt0, fdt1, + &env->active_fpu.fp_status))) +/* + * NOTE: the comma operator will make "cond" to eval to false, + * but float64_unordered() is still called.\ + */ +FOP_CONDN_D(saf, (float64_unordered(fdt1, fdt0, + &env->active_fpu.fp_status), 0)) +FOP_CONDN_D(sun, (float64_unordered(fdt1, fdt0, + &env->active_fpu.fp_status))) +FOP_CONDN_D(seq, (float64_eq(fdt0, fdt1, + &env->active_fpu.fp_status))) +FOP_CONDN_D(sueq, (float64_unordered(fdt1, fdt0, + &env->active_fpu.fp_status) + || float64_eq(fdt0, fdt1, + &env->active_fpu.fp_status))) +FOP_CONDN_D(slt, (float64_lt(fdt0, fdt1, + &env->active_fpu.fp_status))) +FOP_CONDN_D(sult, (float64_unordered(fdt1, fdt0, + &env->active_fpu.fp_status) + || float64_lt(fdt0, fdt1, + &env->active_fpu.fp_status))) +FOP_CONDN_D(sle, (float64_le(fdt0, fdt1, + &env->active_fpu.fp_status))) +FOP_CONDN_D(sule, (float64_unordered(fdt1, fdt0, + &env->active_fpu.fp_status) + || float64_le(fdt0, fdt1, + &env->active_fpu.fp_status))) +FOP_CONDN_D(or, (float64_le_quiet(fdt1, fdt0, + &env->active_fpu.fp_status) + || float64_le_quiet(fdt0, fdt1, + &env->active_fpu.fp_status))) +FOP_CONDN_D(une, (float64_unordered_quiet(fdt1, fdt0, + &env->active_fpu.fp_status) + || float64_lt_quiet(fdt1, fdt0, + &env->active_fpu.fp_status) + || float64_lt_quiet(fdt0, fdt1, + &env->active_fpu.fp_status))) +FOP_CONDN_D(ne, (float64_lt_quiet(fdt1, fdt0, + &env->active_fpu.fp_status) + || float64_lt_quiet(fdt0, fdt1, + &env->active_fpu.fp_status))) +FOP_CONDN_D(sor, (float64_le(fdt1, fdt0, + &env->active_fpu.fp_status) + || float64_le(fdt0, fdt1, + &env->active_fpu.fp_status))) +FOP_CONDN_D(sune, (float64_unordered(fdt1, fdt0, + &env->active_fpu.fp_status) + || float64_lt(fdt1, fdt0, + &env->active_fpu.fp_status) + || float64_lt(fdt0, fdt1, + &env->active_fpu.fp_status))) +FOP_CONDN_D(sne, (float64_lt(fdt1, fdt0, + &env->active_fpu.fp_status) + || float64_lt(fdt0, fdt1, + &env->active_fpu.fp_status))) =20 #define FOP_CONDN_S(op, cond) \ -uint32_t helper_r6_cmp_s_ ## op(CPUMIPSState * env, uint32_t fst0, \ - uint32_t fst1) \ +uint32_t helper_r6_cmp_s_ ## op(CPUMIPSState *env, uint32_t fst0, \ + uint32_t fst1) \ { \ uint64_t c; \ c =3D cond; \ @@ -4291,46 +4567,86 @@ uint32_t helper_r6_cmp_s_ ## op(CPUMIPSState * env,= uint32_t fst0, \ } \ } =20 -/* NOTE: the comma operator will make "cond" to eval to false, - * but float32_unordered_quiet() is still called. */ -FOP_CONDN_S(af, (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp= _status), 0)) -FOP_CONDN_S(un, (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp= _status))) -FOP_CONDN_S(eq, (float32_eq_quiet(fst0, fst1, &env->active_fpu.fp_status= ))) -FOP_CONDN_S(ueq, (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp= _status) - || float32_eq_quiet(fst0, fst1, &env->active_fpu.fp_sta= tus))) -FOP_CONDN_S(lt, (float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status= ))) -FOP_CONDN_S(ult, (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp= _status) - || float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_sta= tus))) -FOP_CONDN_S(le, (float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status= ))) -FOP_CONDN_S(ule, (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp= _status) - || float32_le_quiet(fst0, fst1, &env->active_fpu.fp_sta= tus))) -/* NOTE: the comma operator will make "cond" to eval to false, - * but float32_unordered() is still called. */ -FOP_CONDN_S(saf, (float32_unordered(fst1, fst0, &env->active_fpu.fp_statu= s), 0)) -FOP_CONDN_S(sun, (float32_unordered(fst1, fst0, &env->active_fpu.fp_statu= s))) -FOP_CONDN_S(seq, (float32_eq(fst0, fst1, &env->active_fpu.fp_status))) -FOP_CONDN_S(sueq, (float32_unordered(fst1, fst0, &env->active_fpu.fp_statu= s) - || float32_eq(fst0, fst1, &env->active_fpu.fp_status))) -FOP_CONDN_S(slt, (float32_lt(fst0, fst1, &env->active_fpu.fp_status))) -FOP_CONDN_S(sult, (float32_unordered(fst1, fst0, &env->active_fpu.fp_statu= s) - || float32_lt(fst0, fst1, &env->active_fpu.fp_status))) -FOP_CONDN_S(sle, (float32_le(fst0, fst1, &env->active_fpu.fp_status))) -FOP_CONDN_S(sule, (float32_unordered(fst1, fst0, &env->active_fpu.fp_statu= s) - || float32_le(fst0, fst1, &env->active_fpu.fp_status))) -FOP_CONDN_S(or, (float32_le_quiet(fst1, fst0, &env->active_fpu.fp_status) - || float32_le_quiet(fst0, fst1, &env->active_fpu.fp_sta= tus))) -FOP_CONDN_S(une, (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp= _status) - || float32_lt_quiet(fst1, fst0, &env->active_fpu.fp_sta= tus) - || float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_sta= tus))) -FOP_CONDN_S(ne, (float32_lt_quiet(fst1, fst0, &env->active_fpu.fp_status) - || float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_sta= tus))) -FOP_CONDN_S(sor, (float32_le(fst1, fst0, &env->active_fpu.fp_status) - || float32_le(fst0, fst1, &env->active_fpu.fp_status))) -FOP_CONDN_S(sune, (float32_unordered(fst1, fst0, &env->active_fpu.fp_statu= s) - || float32_lt(fst1, fst0, &env->active_fpu.fp_status) - || float32_lt(fst0, fst1, &env->active_fpu.fp_status))) -FOP_CONDN_S(sne, (float32_lt(fst1, fst0, &env->active_fpu.fp_status) - || float32_lt(fst0, fst1, &env->active_fpu.fp_status))) +/* + * NOTE: the comma operator will make "cond" to eval to false, + * but float32_unordered_quiet() is still called. + */ +FOP_CONDN_S(af, (float32_unordered_quiet(fst1, fst0, + &env->active_fpu.fp_status), 0)) +FOP_CONDN_S(un, (float32_unordered_quiet(fst1, fst0, + &env->active_fpu.fp_status))) +FOP_CONDN_S(eq, (float32_eq_quiet(fst0, fst1, + &env->active_fpu.fp_status))) +FOP_CONDN_S(ueq, (float32_unordered_quiet(fst1, fst0, + &env->active_fpu.fp_status) + || float32_eq_quiet(fst0, fst1, + &env->active_fpu.fp_status))) +FOP_CONDN_S(lt, (float32_lt_quiet(fst0, fst1, + &env->active_fpu.fp_status))) +FOP_CONDN_S(ult, (float32_unordered_quiet(fst1, fst0, + &env->active_fpu.fp_status) + || float32_lt_quiet(fst0, fst1, + &env->active_fpu.fp_status))) +FOP_CONDN_S(le, (float32_le_quiet(fst0, fst1, + &env->active_fpu.fp_status))) +FOP_CONDN_S(ule, (float32_unordered_quiet(fst1, fst0, + &env->active_fpu.fp_status) + || float32_le_quiet(fst0, fst1, + &env->active_fpu.fp_status))) +/* + * NOTE: the comma operator will make "cond" to eval to false, + * but float32_unordered() is still called. + */ +FOP_CONDN_S(saf, (float32_unordered(fst1, fst0, + &env->active_fpu.fp_status), 0)) +FOP_CONDN_S(sun, (float32_unordered(fst1, fst0, + &env->active_fpu.fp_status))) +FOP_CONDN_S(seq, (float32_eq(fst0, fst1, + &env->active_fpu.fp_status))) +FOP_CONDN_S(sueq, (float32_unordered(fst1, fst0, + &env->active_fpu.fp_status) + || float32_eq(fst0, fst1, + &env->active_fpu.fp_status))) +FOP_CONDN_S(slt, (float32_lt(fst0, fst1, + &env->active_fpu.fp_status))) +FOP_CONDN_S(sult, (float32_unordered(fst1, fst0, + &env->active_fpu.fp_status) + || float32_lt(fst0, fst1, + &env->active_fpu.fp_status))) +FOP_CONDN_S(sle, (float32_le(fst0, fst1, + &env->active_fpu.fp_status))) +FOP_CONDN_S(sule, (float32_unordered(fst1, fst0, + &env->active_fpu.fp_status) + || float32_le(fst0, fst1, + &env->active_fpu.fp_status))) +FOP_CONDN_S(or, (float32_le_quiet(fst1, fst0, + &env->active_fpu.fp_status) + || float32_le_quiet(fst0, fst1, + &env->active_fpu.fp_status))) +FOP_CONDN_S(une, (float32_unordered_quiet(fst1, fst0, + &env->active_fpu.fp_status) + || float32_lt_quiet(fst1, fst0, + &env->active_fpu.fp_status) + || float32_lt_quiet(fst0, fst1, + &env->active_fpu.fp_status))) +FOP_CONDN_S(ne, (float32_lt_quiet(fst1, fst0, + &env->active_fpu.fp_status) + || float32_lt_quiet(fst0, fst1, + &env->active_fpu.fp_status))) +FOP_CONDN_S(sor, (float32_le(fst1, fst0, + &env->active_fpu.fp_status) + || float32_le(fst0, fst1, + &env->active_fpu.fp_status))) +FOP_CONDN_S(sune, (float32_unordered(fst1, fst0, + &env->active_fpu.fp_status) + || float32_lt(fst1, fst0, + &env->active_fpu.fp_status) + || float32_lt(fst0, fst1, + &env->active_fpu.fp_status))) +FOP_CONDN_S(sne, (float32_lt(fst1, fst0, + &env->active_fpu.fp_status) + || float32_lt(fst0, fst1, + &env->active_fpu.fp_status))) =20 /* MSA */ /* Data format min and max values */ @@ -4522,7 +4838,7 @@ void helper_msa_ld_d(CPUMIPSState *env, uint32_t wd, } =20 #define MSA_PAGESPAN(x) \ - ((((x) & ~TARGET_PAGE_MASK) + MSA_WRLEN/8 - 1) >=3D TARGET_PAGE_SI= ZE) + ((((x) & ~TARGET_PAGE_MASK) + MSA_WRLEN / 8 - 1) >=3D TARGET_PAGE_= SIZE) =20 static inline void ensure_writable_pages(CPUMIPSState *env, target_ulong addr, --=20 2.7.4 From nobody Sun May 5 20:08:25 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1570902095; cv=none; d=zoho.com; s=zohoarc; b=SEB8NfvunwQovNLb6QJ5v9pOyIMQjWqrIN8o9Uh7UuNfAWfvPcvsgEXn1nP6Hxio31O8Pwo2O0bjPq6AWimAbrQBrBfcK0zdtV0Uu2/2Qgjzt3pGKvn9hgJkUc5Ai87sL67ENUOpf9mE8Hk8Rnt3OCSiaP2kM4xcXprkUGml7uA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1570902095; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=vxJgU3ZueJKB0dEXhxscvy4kocHn2luVBjnZzAdNyTo=; b=DC7UOuMzhzQKEmd2ZPv4qadZuhUEjYyW9Dymu0fYFrgTs4/0EblzTqzo/xnYLXB6vZPPWCnZDfDnBE4dHSarIjcQ6ZGDx4CXhZQ8mmD6xTHMcqJCqeTXLWN65PolaFLDsdD0iwXMJdcYzjdVz5eTQcQjCkVBCWX6i9KwSlvW1NQ= ARC-Authentication-Results: i=1; mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 157090209530615.463465497632683; Sat, 12 Oct 2019 10:41:35 -0700 (PDT) Received: from localhost ([::1]:35126 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iJLOV-00039n-0q for importer@patchew.org; Sat, 12 Oct 2019 13:41:31 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:38563) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iJLM4-0001NW-AJ for qemu-devel@nongnu.org; Sat, 12 Oct 2019 13:39:02 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iJLM2-00026b-I1 for qemu-devel@nongnu.org; Sat, 12 Oct 2019 13:39:00 -0400 Received: from mx2.rt-rk.com ([89.216.37.149]:36008 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1iJLM2-0001o0-6i for qemu-devel@nongnu.org; Sat, 12 Oct 2019 13:38:58 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id 1B29E1A1FF4; Sat, 12 Oct 2019 19:37:53 +0200 (CEST) Received: from rtrkw774-lin.domain.local (rtrkw774-lin.domain.local [10.10.14.106]) by mail.rt-rk.com (Postfix) with ESMTPSA id EF39D1A0EDB; Sat, 12 Oct 2019 19:37:52 +0200 (CEST) X-Virus-Scanned: amavisd-new at rt-rk.com From: Aleksandar Markovic To: qemu-devel@nongnu.org Subject: [PATCH v3 3/6] MAINTAINERS: Update mail address of Aleksandar Rikalo Date: Sat, 12 Oct 2019 19:37:43 +0200 Message-Id: <1570901866-9548-4-git-send-email-aleksandar.markovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1570901866-9548-1-git-send-email-aleksandar.markovic@rt-rk.com> References: <1570901866-9548-1-git-send-email-aleksandar.markovic@rt-rk.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 89.216.37.149 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: aleksandar.rikalo@rt-rk.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" From: Aleksandar Markovic Aleksandar Rikalo wishes to change his primary mail address for QEMU. Some minor line order is corrected in .mailmap to be alphabetical, too. Signed-off-by: Aleksandar Markovic --- .mailmap | 5 +++-- MAINTAINERS | 18 +++++++++--------- 2 files changed, 12 insertions(+), 11 deletions(-) diff --git a/.mailmap b/.mailmap index 0756a0b..3816e4e 100644 --- a/.mailmap +++ b/.mailmap @@ -39,10 +39,11 @@ Julia Suvorova Julia Suvorova via Qemu= -devel Justin Terry (VM) via Qemu-devel= =20 # Next, replace old addresses by a more recent one. -Anthony Liguori Anthony Liguori -James Hogan Aleksandar Markovic Aleksandar Markovic +Aleksandar Rikalo +Anthony Liguori Anthony Liguori +James Hogan Paul Burton Paul Burton Paul Burton diff --git a/MAINTAINERS b/MAINTAINERS index 3ca8148..4964fbb 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -208,7 +208,7 @@ F: disas/microblaze.c MIPS TCG CPUs M: Aurelien Jarno M: Aleksandar Markovic -R: Aleksandar Rikalo +R: Aleksandar Rikalo S: Maintained F: target/mips/ F: default-configs/*mips* @@ -363,7 +363,7 @@ F: target/arm/kvm.c =20 MIPS KVM CPUs M: James Hogan -R: Aleksandar Rikalo +R: Aleksandar Rikalo S: Maintained F: target/mips/kvm.c =20 @@ -934,7 +934,7 @@ MIPS Machines ------------- Jazz M: Herv=C3=A9 Poussineau -R: Aleksandar Rikalo +R: Aleksandar Rikalo S: Maintained F: hw/mips/mips_jazz.c F: hw/display/jazz_led.c @@ -942,7 +942,7 @@ F: hw/dma/rc4030.c =20 Malta M: Aurelien Jarno -R: Aleksandar Rikalo +R: Aleksandar Rikalo S: Maintained F: hw/mips/mips_malta.c F: hw/mips/gt64xxx_pci.c @@ -950,20 +950,20 @@ F: tests/acceptance/linux_ssh_mips_malta.py =20 Mipssim M: Aleksandar Markovic -R: Aleksandar Rikalo +R: Aleksandar Rikalo S: Odd Fixes F: hw/mips/mips_mipssim.c F: hw/net/mipsnet.c =20 R4000 M: Aurelien Jarno -R: Aleksandar Rikalo +R: Aleksandar Rikalo S: Maintained F: hw/mips/mips_r4k.c =20 Fulong 2E M: Aleksandar Markovic -R: Aleksandar Rikalo +R: Aleksandar Rikalo S: Odd Fixes F: hw/mips/mips_fulong2e.c F: hw/isa/vt82c686.c @@ -972,7 +972,7 @@ F: include/hw/isa/vt82c686.h =20 Boston M: Paul Burton -R: Aleksandar Rikalo +R: Aleksandar Rikalo S: Maintained F: hw/core/loader-fit.c F: hw/mips/boston.c @@ -2348,7 +2348,7 @@ F: disas/i386.c =20 MIPS TCG target M: Aurelien Jarno -R: Aleksandar Rikalo +R: Aleksandar Rikalo S: Maintained F: tcg/mips/ =20 --=20 2.7.4 From nobody Sun May 5 20:08:25 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1570902101993115.01787021728808; Sat, 12 Oct 2019 10:41:41 -0700 (PDT) Received: from localhost ([::1]:35130 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iJLOX-0003GU-7e for importer@patchew.org; Sat, 12 Oct 2019 13:41:33 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:38574) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iJLM5-0001Nc-2J for qemu-devel@nongnu.org; Sat, 12 Oct 2019 13:39:02 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iJLM2-00026p-Lh for qemu-devel@nongnu.org; Sat, 12 Oct 2019 13:39:00 -0400 Received: from mx2.rt-rk.com ([89.216.37.149]:36010 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1iJLM2-0001o9-8U for qemu-devel@nongnu.org; Sat, 12 Oct 2019 13:38:58 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id 2BE8A1A0EDB; Sat, 12 Oct 2019 19:37:53 +0200 (CEST) Received: from rtrkw774-lin.domain.local (rtrkw774-lin.domain.local [10.10.14.106]) by mail.rt-rk.com (Postfix) with ESMTPSA id 004E91A1D39; Sat, 12 Oct 2019 19:37:52 +0200 (CEST) X-Virus-Scanned: amavisd-new at rt-rk.com From: Aleksandar Markovic To: qemu-devel@nongnu.org Subject: [PATCH v3 4/6] target/mips: msa: Split helpers for _A. Date: Sat, 12 Oct 2019 19:37:44 +0200 Message-Id: <1570901866-9548-5-git-send-email-aleksandar.markovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1570901866-9548-1-git-send-email-aleksandar.markovic@rt-rk.com> References: <1570901866-9548-1-git-send-email-aleksandar.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 89.216.37.149 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: aleksandar.rikalo@rt-rk.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Aleksandar Markovic Achieves clearer code and slightly better performance. Signed-off-by: Aleksandar Markovic --- target/mips/helper.h | 11 +++- target/mips/msa_helper.c | 163 ++++++++++++++++++++++++++++++++++++++++++-= ---- target/mips/translate.c | 38 +++++++++-- 3 files changed, 187 insertions(+), 25 deletions(-) diff --git a/target/mips/helper.h b/target/mips/helper.h index d615c83..cef4de6 100644 --- a/target/mips/helper.h +++ b/target/mips/helper.h @@ -877,6 +877,15 @@ DEF_HELPER_4(msa_div_u_h, void, env, i32, i32, i32) DEF_HELPER_4(msa_div_u_w, void, env, i32, i32, i32) DEF_HELPER_4(msa_div_u_d, void, env, i32, i32, i32) =20 +DEF_HELPER_4(msa_max_a_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_max_a_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_max_a_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_max_a_d, void, env, i32, i32, i32) +DEF_HELPER_4(msa_min_a_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_min_a_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_min_a_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_min_a_d, void, env, i32, i32, i32) + DEF_HELPER_4(msa_mod_u_b, void, env, i32, i32, i32) DEF_HELPER_4(msa_mod_u_h, void, env, i32, i32, i32) DEF_HELPER_4(msa_mod_u_w, void, env, i32, i32, i32) @@ -940,8 +949,6 @@ DEF_HELPER_5(msa_max_s_df, void, env, i32, i32, i32, i3= 2) DEF_HELPER_5(msa_max_u_df, void, env, i32, i32, i32, i32) DEF_HELPER_5(msa_min_s_df, void, env, i32, i32, i32, i32) DEF_HELPER_5(msa_min_u_df, void, env, i32, i32, i32, i32) -DEF_HELPER_5(msa_max_a_df, void, env, i32, i32, i32, i32) -DEF_HELPER_5(msa_min_a_df, void, env, i32, i32, i32, i32) DEF_HELPER_5(msa_add_a_df, void, env, i32, i32, i32, i32) DEF_HELPER_5(msa_adds_a_df, void, env, i32, i32, i32, i32) DEF_HELPER_5(msa_adds_s_df, void, env, i32, i32, i32, i32) diff --git a/target/mips/msa_helper.c b/target/mips/msa_helper.c index a2052ba..3eb0ab1 100644 --- a/target/mips/msa_helper.c +++ b/target/mips/msa_helper.c @@ -1736,7 +1736,152 @@ void helper_msa_div_u_d(CPUMIPSState *env, * +---------------+------------------------------------------------------= ----+ */ =20 -/* TODO: insert Int Max Min group helpers here */ +static inline int64_t msa_max_a_df(uint32_t df, int64_t arg1, int64_t arg2) +{ + uint64_t abs_arg1 =3D arg1 >=3D 0 ? arg1 : -arg1; + uint64_t abs_arg2 =3D arg2 >=3D 0 ? arg2 : -arg2; + return abs_arg1 > abs_arg2 ? arg1 : arg2; +} + +void helper_msa_max_a_b(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); + + pwd->b[0] =3D msa_max_a_df(DF_BYTE, pws->b[0], pwt->b[0]); + pwd->b[1] =3D msa_max_a_df(DF_BYTE, pws->b[1], pwt->b[1]); + pwd->b[2] =3D msa_max_a_df(DF_BYTE, pws->b[2], pwt->b[2]); + pwd->b[3] =3D msa_max_a_df(DF_BYTE, pws->b[3], pwt->b[3]); + pwd->b[4] =3D msa_max_a_df(DF_BYTE, pws->b[4], pwt->b[4]); + pwd->b[5] =3D msa_max_a_df(DF_BYTE, pws->b[5], pwt->b[5]); + pwd->b[6] =3D msa_max_a_df(DF_BYTE, pws->b[6], pwt->b[6]); + pwd->b[7] =3D msa_max_a_df(DF_BYTE, pws->b[7], pwt->b[7]); + pwd->b[8] =3D msa_max_a_df(DF_BYTE, pws->b[8], pwt->b[8]); + pwd->b[9] =3D msa_max_a_df(DF_BYTE, pws->b[9], pwt->b[9]); + pwd->b[10] =3D msa_max_a_df(DF_BYTE, pws->b[10], pwt->b[10]); + pwd->b[11] =3D msa_max_a_df(DF_BYTE, pws->b[11], pwt->b[11]); + pwd->b[12] =3D msa_max_a_df(DF_BYTE, pws->b[12], pwt->b[12]); + pwd->b[13] =3D msa_max_a_df(DF_BYTE, pws->b[13], pwt->b[13]); + pwd->b[14] =3D msa_max_a_df(DF_BYTE, pws->b[14], pwt->b[14]); + pwd->b[15] =3D msa_max_a_df(DF_BYTE, pws->b[15], pwt->b[15]); +} + +void helper_msa_max_a_h(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); + + pwd->h[0] =3D msa_max_a_df(DF_HALF, pws->h[0], pwt->h[0]); + pwd->h[1] =3D msa_max_a_df(DF_HALF, pws->h[1], pwt->h[1]); + pwd->h[2] =3D msa_max_a_df(DF_HALF, pws->h[2], pwt->h[2]); + pwd->h[3] =3D msa_max_a_df(DF_HALF, pws->h[3], pwt->h[3]); + pwd->h[4] =3D msa_max_a_df(DF_HALF, pws->h[4], pwt->h[4]); + pwd->h[5] =3D msa_max_a_df(DF_HALF, pws->h[5], pwt->h[5]); + pwd->h[6] =3D msa_max_a_df(DF_HALF, pws->h[6], pwt->h[6]); + pwd->h[7] =3D msa_max_a_df(DF_HALF, pws->h[7], pwt->h[7]); +} + +void helper_msa_max_a_w(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); + + pwd->w[0] =3D msa_max_a_df(DF_WORD, pws->w[0], pwt->w[0]); + pwd->w[1] =3D msa_max_a_df(DF_WORD, pws->w[1], pwt->w[1]); + pwd->w[2] =3D msa_max_a_df(DF_WORD, pws->w[2], pwt->w[2]); + pwd->w[3] =3D msa_max_a_df(DF_WORD, pws->w[3], pwt->w[3]); +} + +void helper_msa_max_a_d(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); + + pwd->d[0] =3D msa_max_a_df(DF_DOUBLE, pws->d[0], pwt->d[0]); + pwd->d[1] =3D msa_max_a_df(DF_DOUBLE, pws->d[1], pwt->d[1]); +} + + +static inline int64_t msa_min_a_df(uint32_t df, int64_t arg1, int64_t arg2) +{ + uint64_t abs_arg1 =3D arg1 >=3D 0 ? arg1 : -arg1; + uint64_t abs_arg2 =3D arg2 >=3D 0 ? arg2 : -arg2; + return abs_arg1 < abs_arg2 ? arg1 : arg2; +} + +void helper_msa_min_a_b(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); + + pwd->b[0] =3D msa_min_a_df(DF_BYTE, pws->b[0], pwt->b[0]); + pwd->b[1] =3D msa_min_a_df(DF_BYTE, pws->b[1], pwt->b[1]); + pwd->b[2] =3D msa_min_a_df(DF_BYTE, pws->b[2], pwt->b[2]); + pwd->b[3] =3D msa_min_a_df(DF_BYTE, pws->b[3], pwt->b[3]); + pwd->b[4] =3D msa_min_a_df(DF_BYTE, pws->b[4], pwt->b[4]); + pwd->b[5] =3D msa_min_a_df(DF_BYTE, pws->b[5], pwt->b[5]); + pwd->b[6] =3D msa_min_a_df(DF_BYTE, pws->b[6], pwt->b[6]); + pwd->b[7] =3D msa_min_a_df(DF_BYTE, pws->b[7], pwt->b[7]); + pwd->b[8] =3D msa_min_a_df(DF_BYTE, pws->b[8], pwt->b[8]); + pwd->b[9] =3D msa_min_a_df(DF_BYTE, pws->b[9], pwt->b[9]); + pwd->b[10] =3D msa_min_a_df(DF_BYTE, pws->b[10], pwt->b[10]); + pwd->b[11] =3D msa_min_a_df(DF_BYTE, pws->b[11], pwt->b[11]); + pwd->b[12] =3D msa_min_a_df(DF_BYTE, pws->b[12], pwt->b[12]); + pwd->b[13] =3D msa_min_a_df(DF_BYTE, pws->b[13], pwt->b[13]); + pwd->b[14] =3D msa_min_a_df(DF_BYTE, pws->b[14], pwt->b[14]); + pwd->b[15] =3D msa_min_a_df(DF_BYTE, pws->b[15], pwt->b[15]); +} + +void helper_msa_min_a_h(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); + + pwd->h[0] =3D msa_min_a_df(DF_HALF, pws->h[0], pwt->h[0]); + pwd->h[1] =3D msa_min_a_df(DF_HALF, pws->h[1], pwt->h[1]); + pwd->h[2] =3D msa_min_a_df(DF_HALF, pws->h[2], pwt->h[2]); + pwd->h[3] =3D msa_min_a_df(DF_HALF, pws->h[3], pwt->h[3]); + pwd->h[4] =3D msa_min_a_df(DF_HALF, pws->h[4], pwt->h[4]); + pwd->h[5] =3D msa_min_a_df(DF_HALF, pws->h[5], pwt->h[5]); + pwd->h[6] =3D msa_min_a_df(DF_HALF, pws->h[6], pwt->h[6]); + pwd->h[7] =3D msa_min_a_df(DF_HALF, pws->h[7], pwt->h[7]); +} + +void helper_msa_min_a_w(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); + + pwd->w[0] =3D msa_min_a_df(DF_WORD, pws->w[0], pwt->w[0]); + pwd->w[1] =3D msa_min_a_df(DF_WORD, pws->w[1], pwt->w[1]); + pwd->w[2] =3D msa_min_a_df(DF_WORD, pws->w[2], pwt->w[2]); + pwd->w[3] =3D msa_min_a_df(DF_WORD, pws->w[3], pwt->w[3]); +} + +void helper_msa_min_a_d(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); + + pwd->d[0] =3D msa_min_a_df(DF_DOUBLE, pws->d[0], pwt->d[0]); + pwd->d[1] =3D msa_min_a_df(DF_DOUBLE, pws->d[1], pwt->d[1]); +} =20 =20 /* @@ -2456,20 +2601,6 @@ MSA_TEROP_IMMU_DF(binsli, binsl) MSA_TEROP_IMMU_DF(binsri, binsr) #undef MSA_TEROP_IMMU_DF =20 -static inline int64_t msa_max_a_df(uint32_t df, int64_t arg1, int64_t arg2) -{ - uint64_t abs_arg1 =3D arg1 >=3D 0 ? arg1 : -arg1; - uint64_t abs_arg2 =3D arg2 >=3D 0 ? arg2 : -arg2; - return abs_arg1 > abs_arg2 ? arg1 : arg2; -} - -static inline int64_t msa_min_a_df(uint32_t df, int64_t arg1, int64_t arg2) -{ - uint64_t abs_arg1 =3D arg1 >=3D 0 ? arg1 : -arg1; - uint64_t abs_arg2 =3D arg2 >=3D 0 ? arg2 : -arg2; - return abs_arg1 < abs_arg2 ? arg1 : arg2; -} - static inline int64_t msa_add_a_df(uint32_t df, int64_t arg1, int64_t arg2) { uint64_t abs_arg1 =3D arg1 >=3D 0 ? arg1 : -arg1; @@ -2773,8 +2904,6 @@ MSA_BINOP_DF(max_s) MSA_BINOP_DF(max_u) MSA_BINOP_DF(min_s) MSA_BINOP_DF(min_u) -MSA_BINOP_DF(max_a) -MSA_BINOP_DF(min_a) MSA_BINOP_DF(add_a) MSA_BINOP_DF(adds_a) MSA_BINOP_DF(adds_s) diff --git a/target/mips/translate.c b/target/mips/translate.c index 5039716..8e26548 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -28642,6 +28642,38 @@ static void gen_msa_3r(CPUMIPSState *env, DisasCon= text *ctx) break; } break; + case OPC_MAX_A_df: + switch (df) { + case DF_BYTE: + gen_helper_msa_max_a_b(cpu_env, twd, tws, twt); + break; + case DF_HALF: + gen_helper_msa_max_a_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_max_a_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_max_a_d(cpu_env, twd, tws, twt); + break; + } + break; + case OPC_MIN_A_df: + switch (df) { + case DF_BYTE: + gen_helper_msa_min_a_b(cpu_env, twd, tws, twt); + break; + case DF_HALF: + gen_helper_msa_min_a_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_min_a_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_min_a_d(cpu_env, twd, tws, twt); + break; + } + break; case OPC_MOD_S_df: switch (df) { case DF_BYTE: @@ -28767,15 +28799,9 @@ static void gen_msa_3r(CPUMIPSState *env, DisasCon= text *ctx) case OPC_ILVR_df: gen_helper_msa_ilvr_df(cpu_env, tdf, twd, tws, twt); break; - case OPC_MAX_A_df: - gen_helper_msa_max_a_df(cpu_env, tdf, twd, tws, twt); - break; case OPC_ILVEV_df: gen_helper_msa_ilvev_df(cpu_env, tdf, twd, tws, twt); break; - case OPC_MIN_A_df: - gen_helper_msa_min_a_df(cpu_env, tdf, twd, tws, twt); - break; case OPC_ILVOD_df: gen_helper_msa_ilvod_df(cpu_env, tdf, twd, tws, twt); break; --=20 2.7.4 From nobody Sun May 5 20:08:25 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1570902106; cv=none; d=zoho.com; s=zohoarc; b=Rvn4th8hL0s1kHtXaNJB3fmaOTEgoGG5tghgl9VEsScmBm6jRRoeFTpM22kUI0cW0/i1S55C7jz//nUMMo5JtsWxd5TI3eMBzjaS86cmJw4/SbN5Qz68wq3i983JCWOgFgk7uozAiWI8id4DoZ/oV/3YGdltdxxwwIR/p+B0kJY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1570902106; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To; bh=BmFVApihcE6rpnhqwKlbU4WJ4ERkfrHTlR3RdA5qPHM=; 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Sat, 12 Oct 2019 13:39:02 -0400 Received: from mx2.rt-rk.com ([89.216.37.149]:36012 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1iJLM2-0001oD-5s for qemu-devel@nongnu.org; Sat, 12 Oct 2019 13:38:58 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id 30C991A20BF; Sat, 12 Oct 2019 19:37:53 +0200 (CEST) Received: from rtrkw774-lin.domain.local (rtrkw774-lin.domain.local [10.10.14.106]) by mail.rt-rk.com (Postfix) with ESMTPSA id 06AC51A1E28; Sat, 12 Oct 2019 19:37:53 +0200 (CEST) X-Virus-Scanned: amavisd-new at rt-rk.com From: Aleksandar Markovic To: qemu-devel@nongnu.org Subject: [PATCH v3 5/6] target/mips: msa: Split helpers for _. Date: Sat, 12 Oct 2019 19:37:45 +0200 Message-Id: <1570901866-9548-6-git-send-email-aleksandar.markovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1570901866-9548-1-git-send-email-aleksandar.markovic@rt-rk.com> References: <1570901866-9548-1-git-send-email-aleksandar.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 89.216.37.149 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: aleksandar.rikalo@rt-rk.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Aleksandar Markovic Achieves clearer code and slightly better performance. Signed-off-by: Aleksandar Markovic --- target/mips/helper.h | 20 ++- target/mips/msa_helper.c | 320 ++++++++++++++++++++++++++++++++++++++++++-= ---- target/mips/translate.c | 76 +++++++++-- 3 files changed, 372 insertions(+), 44 deletions(-) diff --git a/target/mips/helper.h b/target/mips/helper.h index cef4de6..6419bb8 100644 --- a/target/mips/helper.h +++ b/target/mips/helper.h @@ -881,10 +881,26 @@ DEF_HELPER_4(msa_max_a_b, void, env, i32, i32, i32) DEF_HELPER_4(msa_max_a_h, void, env, i32, i32, i32) DEF_HELPER_4(msa_max_a_w, void, env, i32, i32, i32) DEF_HELPER_4(msa_max_a_d, void, env, i32, i32, i32) +DEF_HELPER_4(msa_max_s_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_max_s_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_max_s_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_max_s_d, void, env, i32, i32, i32) +DEF_HELPER_4(msa_max_u_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_max_u_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_max_u_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_max_u_d, void, env, i32, i32, i32) DEF_HELPER_4(msa_min_a_b, void, env, i32, i32, i32) DEF_HELPER_4(msa_min_a_h, void, env, i32, i32, i32) DEF_HELPER_4(msa_min_a_w, void, env, i32, i32, i32) DEF_HELPER_4(msa_min_a_d, void, env, i32, i32, i32) +DEF_HELPER_4(msa_min_s_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_min_s_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_min_s_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_min_s_d, void, env, i32, i32, i32) +DEF_HELPER_4(msa_min_u_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_min_u_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_min_u_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_min_u_d, void, env, i32, i32, i32) =20 DEF_HELPER_4(msa_mod_u_b, void, env, i32, i32, i32) DEF_HELPER_4(msa_mod_u_h, void, env, i32, i32, i32) @@ -945,10 +961,6 @@ DEF_HELPER_5(msa_binsl_df, void, env, i32, i32, i32, i= 32) DEF_HELPER_5(msa_binsr_df, void, env, i32, i32, i32, i32) DEF_HELPER_5(msa_addv_df, void, env, i32, i32, i32, i32) DEF_HELPER_5(msa_subv_df, void, env, i32, i32, i32, i32) -DEF_HELPER_5(msa_max_s_df, void, env, i32, i32, i32, i32) -DEF_HELPER_5(msa_max_u_df, void, env, i32, i32, i32, i32) -DEF_HELPER_5(msa_min_s_df, void, env, i32, i32, i32, i32) -DEF_HELPER_5(msa_min_u_df, void, env, i32, i32, i32, i32) DEF_HELPER_5(msa_add_a_df, void, env, i32, i32, i32, i32) DEF_HELPER_5(msa_adds_a_df, void, env, i32, i32, i32, i32) DEF_HELPER_5(msa_adds_s_df, void, env, i32, i32, i32, i32) diff --git a/target/mips/msa_helper.c b/target/mips/msa_helper.c index 3eb0ab1..65df15d 100644 --- a/target/mips/msa_helper.c +++ b/target/mips/msa_helper.c @@ -1810,6 +1810,152 @@ void helper_msa_max_a_d(CPUMIPSState *env, } =20 =20 +static inline int64_t msa_max_s_df(uint32_t df, int64_t arg1, int64_t arg2) +{ + return arg1 > arg2 ? arg1 : arg2; +} + +void helper_msa_max_s_b(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); + + pwd->b[0] =3D msa_max_s_df(DF_BYTE, pws->b[0], pwt->b[0]); + pwd->b[1] =3D msa_max_s_df(DF_BYTE, pws->b[1], pwt->b[1]); + pwd->b[2] =3D msa_max_s_df(DF_BYTE, pws->b[2], pwt->b[2]); + pwd->b[3] =3D msa_max_s_df(DF_BYTE, pws->b[3], pwt->b[3]); + pwd->b[4] =3D msa_max_s_df(DF_BYTE, pws->b[4], pwt->b[4]); + pwd->b[5] =3D msa_max_s_df(DF_BYTE, pws->b[5], pwt->b[5]); + pwd->b[6] =3D msa_max_s_df(DF_BYTE, pws->b[6], pwt->b[6]); + pwd->b[7] =3D msa_max_s_df(DF_BYTE, pws->b[7], pwt->b[7]); + pwd->b[8] =3D msa_max_s_df(DF_BYTE, pws->b[8], pwt->b[8]); + pwd->b[9] =3D msa_max_s_df(DF_BYTE, pws->b[9], pwt->b[9]); + pwd->b[10] =3D msa_max_s_df(DF_BYTE, pws->b[10], pwt->b[10]); + pwd->b[11] =3D msa_max_s_df(DF_BYTE, pws->b[11], pwt->b[11]); + pwd->b[12] =3D msa_max_s_df(DF_BYTE, pws->b[12], pwt->b[12]); + pwd->b[13] =3D msa_max_s_df(DF_BYTE, pws->b[13], pwt->b[13]); + pwd->b[14] =3D msa_max_s_df(DF_BYTE, pws->b[14], pwt->b[14]); + pwd->b[15] =3D msa_max_s_df(DF_BYTE, pws->b[15], pwt->b[15]); +} + +void helper_msa_max_s_h(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); + + pwd->h[0] =3D msa_max_s_df(DF_HALF, pws->h[0], pwt->h[0]); + pwd->h[1] =3D msa_max_s_df(DF_HALF, pws->h[1], pwt->h[1]); + pwd->h[2] =3D msa_max_s_df(DF_HALF, pws->h[2], pwt->h[2]); + pwd->h[3] =3D msa_max_s_df(DF_HALF, pws->h[3], pwt->h[3]); + pwd->h[4] =3D msa_max_s_df(DF_HALF, pws->h[4], pwt->h[4]); + pwd->h[5] =3D msa_max_s_df(DF_HALF, pws->h[5], pwt->h[5]); + pwd->h[6] =3D msa_max_s_df(DF_HALF, pws->h[6], pwt->h[6]); + pwd->h[7] =3D msa_max_s_df(DF_HALF, pws->h[7], pwt->h[7]); +} + +void helper_msa_max_s_w(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); + + pwd->w[0] =3D msa_max_s_df(DF_WORD, pws->w[0], pwt->w[0]); + pwd->w[1] =3D msa_max_s_df(DF_WORD, pws->w[1], pwt->w[1]); + pwd->w[2] =3D msa_max_s_df(DF_WORD, pws->w[2], pwt->w[2]); + pwd->w[3] =3D msa_max_s_df(DF_WORD, pws->w[3], pwt->w[3]); +} + +void helper_msa_max_s_d(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); + + pwd->d[0] =3D msa_max_s_df(DF_DOUBLE, pws->d[0], pwt->d[0]); + pwd->d[1] =3D msa_max_s_df(DF_DOUBLE, pws->d[1], pwt->d[1]); +} + + +static inline int64_t msa_max_u_df(uint32_t df, int64_t arg1, int64_t arg2) +{ + uint64_t u_arg1 =3D UNSIGNED(arg1, df); + uint64_t u_arg2 =3D UNSIGNED(arg2, df); + return u_arg1 > u_arg2 ? arg1 : arg2; +} + +void helper_msa_max_u_b(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); + + pwd->b[0] =3D msa_max_u_df(DF_BYTE, pws->b[0], pwt->b[0]); + pwd->b[1] =3D msa_max_u_df(DF_BYTE, pws->b[1], pwt->b[1]); + pwd->b[2] =3D msa_max_u_df(DF_BYTE, pws->b[2], pwt->b[2]); + pwd->b[3] =3D msa_max_u_df(DF_BYTE, pws->b[3], pwt->b[3]); + pwd->b[4] =3D msa_max_u_df(DF_BYTE, pws->b[4], pwt->b[4]); + pwd->b[5] =3D msa_max_u_df(DF_BYTE, pws->b[5], pwt->b[5]); + pwd->b[6] =3D msa_max_u_df(DF_BYTE, pws->b[6], pwt->b[6]); + pwd->b[7] =3D msa_max_u_df(DF_BYTE, pws->b[7], pwt->b[7]); + pwd->b[8] =3D msa_max_u_df(DF_BYTE, pws->b[8], pwt->b[8]); + pwd->b[9] =3D msa_max_u_df(DF_BYTE, pws->b[9], pwt->b[9]); + pwd->b[10] =3D msa_max_u_df(DF_BYTE, pws->b[10], pwt->b[10]); + pwd->b[11] =3D msa_max_u_df(DF_BYTE, pws->b[11], pwt->b[11]); + pwd->b[12] =3D msa_max_u_df(DF_BYTE, pws->b[12], pwt->b[12]); + pwd->b[13] =3D msa_max_u_df(DF_BYTE, pws->b[13], pwt->b[13]); + pwd->b[14] =3D msa_max_u_df(DF_BYTE, pws->b[14], pwt->b[14]); + pwd->b[15] =3D msa_max_u_df(DF_BYTE, pws->b[15], pwt->b[15]); +} + +void helper_msa_max_u_h(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); + + pwd->h[0] =3D msa_max_u_df(DF_HALF, pws->h[0], pwt->h[0]); + pwd->h[1] =3D msa_max_u_df(DF_HALF, pws->h[1], pwt->h[1]); + pwd->h[2] =3D msa_max_u_df(DF_HALF, pws->h[2], pwt->h[2]); + pwd->h[3] =3D msa_max_u_df(DF_HALF, pws->h[3], pwt->h[3]); + pwd->h[4] =3D msa_max_u_df(DF_HALF, pws->h[4], pwt->h[4]); + pwd->h[5] =3D msa_max_u_df(DF_HALF, pws->h[5], pwt->h[5]); + pwd->h[6] =3D msa_max_u_df(DF_HALF, pws->h[6], pwt->h[6]); + pwd->h[7] =3D msa_max_u_df(DF_HALF, pws->h[7], pwt->h[7]); +} + +void helper_msa_max_u_w(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); + + pwd->w[0] =3D msa_max_u_df(DF_WORD, pws->w[0], pwt->w[0]); + pwd->w[1] =3D msa_max_u_df(DF_WORD, pws->w[1], pwt->w[1]); + pwd->w[2] =3D msa_max_u_df(DF_WORD, pws->w[2], pwt->w[2]); + pwd->w[3] =3D msa_max_u_df(DF_WORD, pws->w[3], pwt->w[3]); +} + +void helper_msa_max_u_d(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); + + pwd->d[0] =3D msa_max_u_df(DF_DOUBLE, pws->d[0], pwt->d[0]); + pwd->d[1] =3D msa_max_u_df(DF_DOUBLE, pws->d[1], pwt->d[1]); +} + + static inline int64_t msa_min_a_df(uint32_t df, int64_t arg1, int64_t arg2) { uint64_t abs_arg1 =3D arg1 >=3D 0 ? arg1 : -arg1; @@ -1884,6 +2030,152 @@ void helper_msa_min_a_d(CPUMIPSState *env, } =20 =20 +static inline int64_t msa_min_s_df(uint32_t df, int64_t arg1, int64_t arg2) +{ + return arg1 < arg2 ? arg1 : arg2; +} + +void helper_msa_min_s_b(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); + + pwd->b[0] =3D msa_min_s_df(DF_BYTE, pws->b[0], pwt->b[0]); + pwd->b[1] =3D msa_min_s_df(DF_BYTE, pws->b[1], pwt->b[1]); + pwd->b[2] =3D msa_min_s_df(DF_BYTE, pws->b[2], pwt->b[2]); + pwd->b[3] =3D msa_min_s_df(DF_BYTE, pws->b[3], pwt->b[3]); + pwd->b[4] =3D msa_min_s_df(DF_BYTE, pws->b[4], pwt->b[4]); + pwd->b[5] =3D msa_min_s_df(DF_BYTE, pws->b[5], pwt->b[5]); + pwd->b[6] =3D msa_min_s_df(DF_BYTE, pws->b[6], pwt->b[6]); + pwd->b[7] =3D msa_min_s_df(DF_BYTE, pws->b[7], pwt->b[7]); + pwd->b[8] =3D msa_min_s_df(DF_BYTE, pws->b[8], pwt->b[8]); + pwd->b[9] =3D msa_min_s_df(DF_BYTE, pws->b[9], pwt->b[9]); + pwd->b[10] =3D msa_min_s_df(DF_BYTE, pws->b[10], pwt->b[10]); + pwd->b[11] =3D msa_min_s_df(DF_BYTE, pws->b[11], pwt->b[11]); + pwd->b[12] =3D msa_min_s_df(DF_BYTE, pws->b[12], pwt->b[12]); + pwd->b[13] =3D msa_min_s_df(DF_BYTE, pws->b[13], pwt->b[13]); + pwd->b[14] =3D msa_min_s_df(DF_BYTE, pws->b[14], pwt->b[14]); + pwd->b[15] =3D msa_min_s_df(DF_BYTE, pws->b[15], pwt->b[15]); +} + +void helper_msa_min_s_h(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); + + pwd->h[0] =3D msa_min_s_df(DF_HALF, pws->h[0], pwt->h[0]); + pwd->h[1] =3D msa_min_s_df(DF_HALF, pws->h[1], pwt->h[1]); + pwd->h[2] =3D msa_min_s_df(DF_HALF, pws->h[2], pwt->h[2]); + pwd->h[3] =3D msa_min_s_df(DF_HALF, pws->h[3], pwt->h[3]); + pwd->h[4] =3D msa_min_s_df(DF_HALF, pws->h[4], pwt->h[4]); + pwd->h[5] =3D msa_min_s_df(DF_HALF, pws->h[5], pwt->h[5]); + pwd->h[6] =3D msa_min_s_df(DF_HALF, pws->h[6], pwt->h[6]); + pwd->h[7] =3D msa_min_s_df(DF_HALF, pws->h[7], pwt->h[7]); +} + +void helper_msa_min_s_w(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); + + pwd->w[0] =3D msa_min_s_df(DF_WORD, pws->w[0], pwt->w[0]); + pwd->w[1] =3D msa_min_s_df(DF_WORD, pws->w[1], pwt->w[1]); + pwd->w[2] =3D msa_min_s_df(DF_WORD, pws->w[2], pwt->w[2]); + pwd->w[3] =3D msa_min_s_df(DF_WORD, pws->w[3], pwt->w[3]); +} + +void helper_msa_min_s_d(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); + + pwd->d[0] =3D msa_min_s_df(DF_DOUBLE, pws->d[0], pwt->d[0]); + pwd->d[1] =3D msa_min_s_df(DF_DOUBLE, pws->d[1], pwt->d[1]); +} + + +static inline int64_t msa_min_u_df(uint32_t df, int64_t arg1, int64_t arg2) +{ + uint64_t u_arg1 =3D UNSIGNED(arg1, df); + uint64_t u_arg2 =3D UNSIGNED(arg2, df); + return u_arg1 < u_arg2 ? arg1 : arg2; +} + +void helper_msa_min_u_b(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); + + pwd->b[0] =3D msa_min_u_df(DF_BYTE, pws->b[0], pwt->b[0]); + pwd->b[1] =3D msa_min_u_df(DF_BYTE, pws->b[1], pwt->b[1]); + pwd->b[2] =3D msa_min_u_df(DF_BYTE, pws->b[2], pwt->b[2]); + pwd->b[3] =3D msa_min_u_df(DF_BYTE, pws->b[3], pwt->b[3]); + pwd->b[4] =3D msa_min_u_df(DF_BYTE, pws->b[4], pwt->b[4]); + pwd->b[5] =3D msa_min_u_df(DF_BYTE, pws->b[5], pwt->b[5]); + pwd->b[6] =3D msa_min_u_df(DF_BYTE, pws->b[6], pwt->b[6]); + pwd->b[7] =3D msa_min_u_df(DF_BYTE, pws->b[7], pwt->b[7]); + pwd->b[8] =3D msa_min_u_df(DF_BYTE, pws->b[8], pwt->b[8]); + pwd->b[9] =3D msa_min_u_df(DF_BYTE, pws->b[9], pwt->b[9]); + pwd->b[10] =3D msa_min_u_df(DF_BYTE, pws->b[10], pwt->b[10]); + pwd->b[11] =3D msa_min_u_df(DF_BYTE, pws->b[11], pwt->b[11]); + pwd->b[12] =3D msa_min_u_df(DF_BYTE, pws->b[12], pwt->b[12]); + pwd->b[13] =3D msa_min_u_df(DF_BYTE, pws->b[13], pwt->b[13]); + pwd->b[14] =3D msa_min_u_df(DF_BYTE, pws->b[14], pwt->b[14]); + pwd->b[15] =3D msa_min_u_df(DF_BYTE, pws->b[15], pwt->b[15]); +} + +void helper_msa_min_u_h(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); + + pwd->h[0] =3D msa_min_u_df(DF_HALF, pws->h[0], pwt->h[0]); + pwd->h[1] =3D msa_min_u_df(DF_HALF, pws->h[1], pwt->h[1]); + pwd->h[2] =3D msa_min_u_df(DF_HALF, pws->h[2], pwt->h[2]); + pwd->h[3] =3D msa_min_u_df(DF_HALF, pws->h[3], pwt->h[3]); + pwd->h[4] =3D msa_min_u_df(DF_HALF, pws->h[4], pwt->h[4]); + pwd->h[5] =3D msa_min_u_df(DF_HALF, pws->h[5], pwt->h[5]); + pwd->h[6] =3D msa_min_u_df(DF_HALF, pws->h[6], pwt->h[6]); + pwd->h[7] =3D msa_min_u_df(DF_HALF, pws->h[7], pwt->h[7]); +} + +void helper_msa_min_u_w(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); + + pwd->w[0] =3D msa_min_u_df(DF_WORD, pws->w[0], pwt->w[0]); + pwd->w[1] =3D msa_min_u_df(DF_WORD, pws->w[1], pwt->w[1]); + pwd->w[2] =3D msa_min_u_df(DF_WORD, pws->w[2], pwt->w[2]); + pwd->w[3] =3D msa_min_u_df(DF_WORD, pws->w[3], pwt->w[3]); +} + +void helper_msa_min_u_d(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); + + pwd->d[0] =3D msa_min_u_df(DF_DOUBLE, pws->d[0], pwt->d[0]); + pwd->d[1] =3D msa_min_u_df(DF_DOUBLE, pws->d[1], pwt->d[1]); +} + + /* * Int Modulo * ---------- @@ -2354,30 +2646,6 @@ static inline int64_t msa_subv_df(uint32_t df, int64= _t arg1, int64_t arg2) return arg1 - arg2; } =20 -static inline int64_t msa_max_s_df(uint32_t df, int64_t arg1, int64_t arg2) -{ - return arg1 > arg2 ? arg1 : arg2; -} - -static inline int64_t msa_max_u_df(uint32_t df, int64_t arg1, int64_t arg2) -{ - uint64_t u_arg1 =3D UNSIGNED(arg1, df); - uint64_t u_arg2 =3D UNSIGNED(arg2, df); - return u_arg1 > u_arg2 ? arg1 : arg2; -} - -static inline int64_t msa_min_s_df(uint32_t df, int64_t arg1, int64_t arg2) -{ - return arg1 < arg2 ? arg1 : arg2; -} - -static inline int64_t msa_min_u_df(uint32_t df, int64_t arg1, int64_t arg2) -{ - uint64_t u_arg1 =3D UNSIGNED(arg1, df); - uint64_t u_arg2 =3D UNSIGNED(arg2, df); - return u_arg1 < u_arg2 ? arg1 : arg2; -} - #define MSA_BINOP_IMM_DF(helper, func) \ void helper_msa_ ## helper ## _df(CPUMIPSState *env, uint32_t df, \ uint32_t wd, uint32_t ws, int32_t u5) \ @@ -2900,10 +3168,6 @@ MSA_BINOP_DF(sra) MSA_BINOP_DF(srl) MSA_BINOP_DF(addv) MSA_BINOP_DF(subv) -MSA_BINOP_DF(max_s) -MSA_BINOP_DF(max_u) -MSA_BINOP_DF(min_s) -MSA_BINOP_DF(min_u) MSA_BINOP_DF(add_a) MSA_BINOP_DF(adds_a) MSA_BINOP_DF(adds_s) diff --git a/target/mips/translate.c b/target/mips/translate.c index 8e26548..7a35c26 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -28658,6 +28658,38 @@ static void gen_msa_3r(CPUMIPSState *env, DisasCon= text *ctx) break; } break; + case OPC_MAX_S_df: + switch (df) { + case DF_BYTE: + gen_helper_msa_max_s_b(cpu_env, twd, tws, twt); + break; + case DF_HALF: + gen_helper_msa_max_s_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_max_s_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_max_s_d(cpu_env, twd, tws, twt); + break; + } + break; + case OPC_MAX_U_df: + switch (df) { + case DF_BYTE: + gen_helper_msa_max_u_b(cpu_env, twd, tws, twt); + break; + case DF_HALF: + gen_helper_msa_max_u_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_max_u_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_max_u_d(cpu_env, twd, tws, twt); + break; + } + break; case OPC_MIN_A_df: switch (df) { case DF_BYTE: @@ -28674,6 +28706,38 @@ static void gen_msa_3r(CPUMIPSState *env, DisasCon= text *ctx) break; } break; + case OPC_MIN_S_df: + switch (df) { + case DF_BYTE: + gen_helper_msa_min_s_b(cpu_env, twd, tws, twt); + break; + case DF_HALF: + gen_helper_msa_min_s_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_min_s_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_min_s_d(cpu_env, twd, tws, twt); + break; + } + break; + case OPC_MIN_U_df: + switch (df) { + case DF_BYTE: + gen_helper_msa_min_u_b(cpu_env, twd, tws, twt); + break; + case DF_HALF: + gen_helper_msa_min_u_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_min_u_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_min_u_d(cpu_env, twd, tws, twt); + break; + } + break; case OPC_MOD_S_df: switch (df) { case DF_BYTE: @@ -28751,9 +28815,6 @@ static void gen_msa_3r(CPUMIPSState *env, DisasCont= ext *ctx) case OPC_SRL_df: gen_helper_msa_srl_df(cpu_env, tdf, twd, tws, twt); break; - case OPC_MAX_S_df: - gen_helper_msa_max_s_df(cpu_env, tdf, twd, tws, twt); - break; case OPC_ADDS_S_df: gen_helper_msa_adds_s_df(cpu_env, tdf, twd, tws, twt); break; @@ -28769,9 +28830,6 @@ static void gen_msa_3r(CPUMIPSState *env, DisasCont= ext *ctx) case OPC_SRLR_df: gen_helper_msa_srlr_df(cpu_env, tdf, twd, tws, twt); break; - case OPC_MAX_U_df: - gen_helper_msa_max_u_df(cpu_env, tdf, twd, tws, twt); - break; case OPC_ADDS_U_df: gen_helper_msa_adds_u_df(cpu_env, tdf, twd, tws, twt); break; @@ -28781,18 +28839,12 @@ static void gen_msa_3r(CPUMIPSState *env, DisasCo= ntext *ctx) case OPC_PCKOD_df: gen_helper_msa_pckod_df(cpu_env, tdf, twd, tws, twt); break; - case OPC_MIN_S_df: - gen_helper_msa_min_s_df(cpu_env, tdf, twd, tws, twt); - break; case OPC_ASUB_S_df: gen_helper_msa_asub_s_df(cpu_env, tdf, twd, tws, twt); break; case OPC_ILVL_df: gen_helper_msa_ilvl_df(cpu_env, tdf, twd, tws, twt); break; - case OPC_MIN_U_df: - gen_helper_msa_min_u_df(cpu_env, tdf, twd, tws, twt); - break; case OPC_ASUB_U_df: gen_helper_msa_asub_u_df(cpu_env, tdf, twd, tws, twt); break; --=20 2.7.4 From nobody Sun May 5 20:08:25 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; 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Sat, 12 Oct 2019 19:37:53 +0200 (CEST) X-Virus-Scanned: amavisd-new at rt-rk.com From: Aleksandar Markovic To: qemu-devel@nongnu.org Subject: [PATCH v3 6/6] target/mips: msa: Split helpers for ILV. Date: Sat, 12 Oct 2019 19:37:46 +0200 Message-Id: <1570901866-9548-7-git-send-email-aleksandar.markovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1570901866-9548-1-git-send-email-aleksandar.markovic@rt-rk.com> References: <1570901866-9548-1-git-send-email-aleksandar.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 89.216.37.149 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: aleksandar.rikalo@rt-rk.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Aleksandar Markovic Achieves clearer code and slightly better performance. Signed-off-by: Aleksandar Markovic --- target/mips/helper.h | 21 +- target/mips/msa_helper.c | 768 +++++++++++++++++++++++++------------------= ---- target/mips/translate.c | 76 ++++- 3 files changed, 496 insertions(+), 369 deletions(-) diff --git a/target/mips/helper.h b/target/mips/helper.h index 6419bb8..f3df187 100644 --- a/target/mips/helper.h +++ b/target/mips/helper.h @@ -912,6 +912,23 @@ DEF_HELPER_4(msa_mod_s_h, void, env, i32, i32, i32) DEF_HELPER_4(msa_mod_s_w, void, env, i32, i32, i32) DEF_HELPER_4(msa_mod_s_d, void, env, i32, i32, i32) =20 +DEF_HELPER_4(msa_ilvev_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_ilvev_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_ilvev_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_ilvev_d, void, env, i32, i32, i32) +DEF_HELPER_4(msa_ilvod_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_ilvod_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_ilvod_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_ilvod_d, void, env, i32, i32, i32) +DEF_HELPER_4(msa_ilvl_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_ilvl_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_ilvl_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_ilvl_d, void, env, i32, i32, i32) +DEF_HELPER_4(msa_ilvr_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_ilvr_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_ilvr_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_ilvr_d, void, env, i32, i32, i32) + DEF_HELPER_4(msa_and_v, void, env, i32, i32, i32) DEF_HELPER_4(msa_nor_v, void, env, i32, i32, i32) DEF_HELPER_4(msa_or_v, void, env, i32, i32, i32) @@ -984,10 +1001,6 @@ DEF_HELPER_5(msa_sld_df, void, env, i32, i32, i32, i3= 2) DEF_HELPER_5(msa_splat_df, void, env, i32, i32, i32, i32) DEF_HELPER_5(msa_pckev_df, void, env, i32, i32, i32, i32) DEF_HELPER_5(msa_pckod_df, void, env, i32, i32, i32, i32) -DEF_HELPER_5(msa_ilvl_df, void, env, i32, i32, i32, i32) -DEF_HELPER_5(msa_ilvr_df, void, env, i32, i32, i32, i32) -DEF_HELPER_5(msa_ilvev_df, void, env, i32, i32, i32, i32) -DEF_HELPER_5(msa_ilvod_df, void, env, i32, i32, i32, i32) DEF_HELPER_5(msa_vshf_df, void, env, i32, i32, i32, i32) DEF_HELPER_5(msa_srar_df, void, env, i32, i32, i32, i32) DEF_HELPER_5(msa_srlr_df, void, env, i32, i32, i32, i32) diff --git a/target/mips/msa_helper.c b/target/mips/msa_helper.c index 65df15d..499fcde 100644 --- a/target/mips/msa_helper.c +++ b/target/mips/msa_helper.c @@ -2432,7 +2432,421 @@ void helper_msa_mod_u_d(CPUMIPSState *env, * +---------------+------------------------------------------------------= ----+ */ =20 -/* TODO: insert Interleave group helpers here */ + +void helper_msa_ilvev_b(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); + +#if defined(HOST_WORDS_BIGENDIAN) + pwd->b[8] =3D pws->b[9]; + pwd->b[9] =3D pwt->b[9]; + pwd->b[10] =3D pws->b[11]; + pwd->b[11] =3D pwt->b[11]; + pwd->b[12] =3D pws->b[13]; + pwd->b[13] =3D pwt->b[13]; + pwd->b[14] =3D pws->b[15]; + pwd->b[15] =3D pwt->b[15]; + pwd->b[0] =3D pws->b[1]; + pwd->b[1] =3D pwt->b[1]; + pwd->b[2] =3D pws->b[3]; + pwd->b[3] =3D pwt->b[3]; + pwd->b[4] =3D pws->b[5]; + pwd->b[5] =3D pwt->b[5]; + pwd->b[6] =3D pws->b[7]; + pwd->b[7] =3D pwt->b[7]; +#else + pwd->b[15] =3D pws->b[14]; + pwd->b[14] =3D pwt->b[14]; + pwd->b[13] =3D pws->b[12]; + pwd->b[12] =3D pwt->b[12]; + pwd->b[11] =3D pws->b[10]; + pwd->b[10] =3D pwt->b[10]; + pwd->b[9] =3D pws->b[8]; + pwd->b[8] =3D pwt->b[8]; + pwd->b[7] =3D pws->b[6]; + pwd->b[6] =3D pwt->b[6]; + pwd->b[5] =3D pws->b[4]; + pwd->b[4] =3D pwt->b[4]; + pwd->b[3] =3D pws->b[2]; + pwd->b[2] =3D pwt->b[2]; + pwd->b[1] =3D pws->b[0]; + pwd->b[0] =3D pwt->b[0]; +#endif +} + +void helper_msa_ilvev_h(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); + +#if defined(HOST_WORDS_BIGENDIAN) + pwd->h[4] =3D pws->h[5]; + pwd->h[5] =3D pwt->h[5]; + pwd->h[6] =3D pws->h[7]; + pwd->h[7] =3D pwt->h[7]; + pwd->h[0] =3D pws->h[1]; + pwd->h[1] =3D pwt->h[1]; + pwd->h[2] =3D pws->h[3]; + pwd->h[3] =3D pwt->h[3]; +#else + pwd->h[7] =3D pws->h[6]; + pwd->h[6] =3D pwt->h[6]; + pwd->h[5] =3D pws->h[4]; + pwd->h[4] =3D pwt->h[4]; + pwd->h[3] =3D pws->h[2]; + pwd->h[2] =3D pwt->h[2]; + pwd->h[1] =3D pws->h[0]; + pwd->h[0] =3D pwt->h[0]; +#endif +} + +void helper_msa_ilvev_w(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); + +#if defined(HOST_WORDS_BIGENDIAN) + pwd->w[2] =3D pws->w[3]; + pwd->w[3] =3D pwt->w[3]; + pwd->w[0] =3D pws->w[1]; + pwd->w[1] =3D pwt->w[1]; +#else + pwd->w[3] =3D pws->w[2]; + pwd->w[2] =3D pwt->w[2]; + pwd->w[1] =3D pws->w[0]; + pwd->w[0] =3D pwt->w[0]; +#endif +} + +void helper_msa_ilvev_d(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); + + pwd->d[1] =3D pws->d[0]; + pwd->d[0] =3D pwt->d[0]; +} + + +void helper_msa_ilvod_b(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); + +#if defined(HOST_WORDS_BIGENDIAN) + pwd->b[7] =3D pwt->b[6]; + pwd->b[6] =3D pws->b[6]; + pwd->b[5] =3D pwt->b[4]; + pwd->b[4] =3D pws->b[4]; + pwd->b[3] =3D pwt->b[2]; + pwd->b[2] =3D pws->b[2]; + pwd->b[1] =3D pwt->b[0]; + pwd->b[0] =3D pws->b[0]; + pwd->b[15] =3D pwt->b[14]; + pwd->b[14] =3D pws->b[14]; + pwd->b[13] =3D pwt->b[12]; + pwd->b[12] =3D pws->b[12]; + pwd->b[11] =3D pwt->b[10]; + pwd->b[10] =3D pws->b[10]; + pwd->b[9] =3D pwt->b[8]; + pwd->b[8] =3D pws->b[8]; +#else + pwd->b[0] =3D pwt->b[1]; + pwd->b[1] =3D pws->b[1]; + pwd->b[2] =3D pwt->b[3]; + pwd->b[3] =3D pws->b[3]; + pwd->b[4] =3D pwt->b[5]; + pwd->b[5] =3D pws->b[5]; + pwd->b[6] =3D pwt->b[7]; + pwd->b[7] =3D pws->b[7]; + pwd->b[8] =3D pwt->b[9]; + pwd->b[9] =3D pws->b[9]; + pwd->b[10] =3D pwt->b[11]; + pwd->b[11] =3D pws->b[11]; + pwd->b[12] =3D pwt->b[13]; + pwd->b[13] =3D pws->b[13]; + pwd->b[14] =3D pwt->b[15]; + pwd->b[15] =3D pws->b[15]; +#endif +} + +void helper_msa_ilvod_h(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); + +#if defined(HOST_WORDS_BIGENDIAN) + pwd->h[3] =3D pwt->h[2]; + pwd->h[2] =3D pws->h[2]; + pwd->h[1] =3D pwt->h[0]; + pwd->h[0] =3D pws->h[0]; + pwd->h[7] =3D pwt->h[6]; + pwd->h[6] =3D pws->h[6]; + pwd->h[5] =3D pwt->h[4]; + pwd->h[4] =3D pws->h[4]; +#else + pwd->h[0] =3D pwt->h[1]; + pwd->h[1] =3D pws->h[1]; + pwd->h[2] =3D pwt->h[3]; + pwd->h[3] =3D pws->h[3]; + pwd->h[4] =3D pwt->h[5]; + pwd->h[5] =3D pws->h[5]; + pwd->h[6] =3D pwt->h[7]; + pwd->h[7] =3D pws->h[7]; +#endif +} + +void helper_msa_ilvod_w(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); + +#if defined(HOST_WORDS_BIGENDIAN) + pwd->w[1] =3D pwt->w[0]; + pwd->w[0] =3D pws->w[0]; + pwd->w[3] =3D pwt->w[2]; + pwd->w[2] =3D pws->w[2]; +#else + pwd->w[0] =3D pwt->w[1]; + pwd->w[1] =3D pws->w[1]; + pwd->w[2] =3D pwt->w[3]; + pwd->w[3] =3D pws->w[3]; +#endif +} + +void helper_msa_ilvod_d(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); + + pwd->d[0] =3D pwt->d[1]; + pwd->d[1] =3D pws->d[1]; +} + + +void helper_msa_ilvl_b(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); + +#if defined(HOST_WORDS_BIGENDIAN) + pwd->b[7] =3D pwt->b[15]; + pwd->b[6] =3D pws->b[15]; + pwd->b[5] =3D pwt->b[14]; + pwd->b[4] =3D pws->b[14]; + pwd->b[3] =3D pwt->b[13]; + pwd->b[2] =3D pws->b[13]; + pwd->b[1] =3D pwt->b[12]; + pwd->b[0] =3D pws->b[12]; + pwd->b[15] =3D pwt->b[11]; + pwd->b[14] =3D pws->b[11]; + pwd->b[13] =3D pwt->b[10]; + pwd->b[12] =3D pws->b[10]; + pwd->b[11] =3D pwt->b[9]; + pwd->b[10] =3D pws->b[9]; + pwd->b[9] =3D pwt->b[8]; + pwd->b[8] =3D pws->b[8]; +#else + pwd->b[0] =3D pwt->b[8]; + pwd->b[1] =3D pws->b[8]; + pwd->b[2] =3D pwt->b[9]; + pwd->b[3] =3D pws->b[9]; + pwd->b[4] =3D pwt->b[10]; + pwd->b[5] =3D pws->b[10]; + pwd->b[6] =3D pwt->b[11]; + pwd->b[7] =3D pws->b[11]; + pwd->b[8] =3D pwt->b[12]; + pwd->b[9] =3D pws->b[12]; + pwd->b[10] =3D pwt->b[13]; + pwd->b[11] =3D pws->b[13]; + pwd->b[12] =3D pwt->b[14]; + pwd->b[13] =3D pws->b[14]; + pwd->b[14] =3D pwt->b[15]; + pwd->b[15] =3D pws->b[15]; +#endif +} + +void helper_msa_ilvl_h(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); + +#if defined(HOST_WORDS_BIGENDIAN) + pwd->h[3] =3D pwt->h[7]; + pwd->h[2] =3D pws->h[7]; + pwd->h[1] =3D pwt->h[6]; + pwd->h[0] =3D pws->h[6]; + pwd->h[7] =3D pwt->h[5]; + pwd->h[6] =3D pws->h[5]; + pwd->h[5] =3D pwt->h[4]; + pwd->h[4] =3D pws->h[4]; +#else + pwd->h[0] =3D pwt->h[4]; + pwd->h[1] =3D pws->h[4]; + pwd->h[2] =3D pwt->h[5]; + pwd->h[3] =3D pws->h[5]; + pwd->h[4] =3D pwt->h[6]; + pwd->h[5] =3D pws->h[6]; + pwd->h[6] =3D pwt->h[7]; + pwd->h[7] =3D pws->h[7]; +#endif +} + +void helper_msa_ilvl_w(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); + +#if defined(HOST_WORDS_BIGENDIAN) + pwd->w[1] =3D pwt->w[3]; + pwd->w[0] =3D pws->w[3]; + pwd->w[3] =3D pwt->w[2]; + pwd->w[2] =3D pws->w[2]; +#else + pwd->w[0] =3D pwt->w[2]; + pwd->w[1] =3D pws->w[2]; + pwd->w[2] =3D pwt->w[3]; + pwd->w[3] =3D pws->w[3]; +#endif +} + +void helper_msa_ilvl_d(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); + + pwd->d[0] =3D pwt->d[1]; + pwd->d[1] =3D pws->d[1]; +} + + +void helper_msa_ilvr_b(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); + +#if defined(HOST_WORDS_BIGENDIAN) + pwd->b[8] =3D pws->b[0]; + pwd->b[9] =3D pwt->b[0]; + pwd->b[10] =3D pws->b[1]; + pwd->b[11] =3D pwt->b[1]; + pwd->b[12] =3D pws->b[2]; + pwd->b[13] =3D pwt->b[2]; + pwd->b[14] =3D pws->b[3]; + pwd->b[15] =3D pwt->b[3]; + pwd->b[0] =3D pws->b[4]; + pwd->b[1] =3D pwt->b[4]; + pwd->b[2] =3D pws->b[5]; + pwd->b[3] =3D pwt->b[5]; + pwd->b[4] =3D pws->b[6]; + pwd->b[5] =3D pwt->b[6]; + pwd->b[6] =3D pws->b[7]; + pwd->b[7] =3D pwt->b[7]; +#else + pwd->b[15] =3D pws->b[7]; + pwd->b[14] =3D pwt->b[7]; + pwd->b[13] =3D pws->b[6]; + pwd->b[12] =3D pwt->b[6]; + pwd->b[11] =3D pws->b[5]; + pwd->b[10] =3D pwt->b[5]; + pwd->b[9] =3D pws->b[4]; + pwd->b[8] =3D pwt->b[4]; + pwd->b[7] =3D pws->b[3]; + pwd->b[6] =3D pwt->b[3]; + pwd->b[5] =3D pws->b[2]; + pwd->b[4] =3D pwt->b[2]; + pwd->b[3] =3D pws->b[1]; + pwd->b[2] =3D pwt->b[1]; + pwd->b[1] =3D pws->b[0]; + pwd->b[0] =3D pwt->b[0]; +#endif +} + +void helper_msa_ilvr_h(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); + +#if defined(HOST_WORDS_BIGENDIAN) + pwd->h[4] =3D pws->h[0]; + pwd->h[5] =3D pwt->h[0]; + pwd->h[6] =3D pws->h[1]; + pwd->h[7] =3D pwt->h[1]; + pwd->h[0] =3D pws->h[2]; + pwd->h[1] =3D pwt->h[2]; + pwd->h[2] =3D pws->h[3]; + pwd->h[3] =3D pwt->h[3]; +#else + pwd->h[7] =3D pws->h[3]; + pwd->h[6] =3D pwt->h[3]; + pwd->h[5] =3D pws->h[2]; + pwd->h[4] =3D pwt->h[2]; + pwd->h[3] =3D pws->h[1]; + pwd->h[2] =3D pwt->h[1]; + pwd->h[1] =3D pws->h[0]; + pwd->h[0] =3D pwt->h[0]; +#endif +} + +void helper_msa_ilvr_w(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); + +#if defined(HOST_WORDS_BIGENDIAN) + pwd->w[2] =3D pws->w[0]; + pwd->w[3] =3D pwt->w[0]; + pwd->w[0] =3D pws->w[1]; + pwd->w[1] =3D pwt->w[1]; +#else + pwd->w[3] =3D pws->w[1]; + pwd->w[2] =3D pwt->w[1]; + pwd->w[1] =3D pws->w[0]; + pwd->w[0] =3D pwt->w[0]; +#endif +} + +void helper_msa_ilvr_d(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); + + pwd->d[1] =3D pws->d[0]; + pwd->d[0] =3D pwt->d[0]; +} =20 =20 /* @@ -3522,358 +3936,6 @@ MSA_FN_DF(vshf_df) #undef MSA_FN_DF =20 =20 -void helper_msa_ilvev_df(CPUMIPSState *env, uint32_t df, uint32_t wd, - uint32_t ws, uint32_t wt) -{ - wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); - wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); - wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); - - switch (df) { - case DF_BYTE: -#if defined(HOST_WORDS_BIGENDIAN) - pwd->b[8] =3D pws->b[9]; - pwd->b[9] =3D pwt->b[9]; - pwd->b[10] =3D pws->b[11]; - pwd->b[11] =3D pwt->b[11]; - pwd->b[12] =3D pws->b[13]; - pwd->b[13] =3D pwt->b[13]; - pwd->b[14] =3D pws->b[15]; - pwd->b[15] =3D pwt->b[15]; - pwd->b[0] =3D pws->b[1]; - pwd->b[1] =3D pwt->b[1]; - pwd->b[2] =3D pws->b[3]; - pwd->b[3] =3D pwt->b[3]; - pwd->b[4] =3D pws->b[5]; - pwd->b[5] =3D pwt->b[5]; - pwd->b[6] =3D pws->b[7]; - pwd->b[7] =3D pwt->b[7]; -#else - pwd->b[15] =3D pws->b[14]; - pwd->b[14] =3D pwt->b[14]; - pwd->b[13] =3D pws->b[12]; - pwd->b[12] =3D pwt->b[12]; - pwd->b[11] =3D pws->b[10]; - pwd->b[10] =3D pwt->b[10]; - pwd->b[9] =3D pws->b[8]; - pwd->b[8] =3D pwt->b[8]; - pwd->b[7] =3D pws->b[6]; - pwd->b[6] =3D pwt->b[6]; - pwd->b[5] =3D pws->b[4]; - pwd->b[4] =3D pwt->b[4]; - pwd->b[3] =3D pws->b[2]; - pwd->b[2] =3D pwt->b[2]; - pwd->b[1] =3D pws->b[0]; - pwd->b[0] =3D pwt->b[0]; -#endif - break; - case DF_HALF: -#if defined(HOST_WORDS_BIGENDIAN) - pwd->h[4] =3D pws->h[5]; - pwd->h[5] =3D pwt->h[5]; - pwd->h[6] =3D pws->h[7]; - pwd->h[7] =3D pwt->h[7]; - pwd->h[0] =3D pws->h[1]; - pwd->h[1] =3D pwt->h[1]; - pwd->h[2] =3D pws->h[3]; - pwd->h[3] =3D pwt->h[3]; -#else - pwd->h[7] =3D pws->h[6]; - pwd->h[6] =3D pwt->h[6]; - pwd->h[5] =3D pws->h[4]; - pwd->h[4] =3D pwt->h[4]; - pwd->h[3] =3D pws->h[2]; - pwd->h[2] =3D pwt->h[2]; - pwd->h[1] =3D pws->h[0]; - pwd->h[0] =3D pwt->h[0]; -#endif - break; - case DF_WORD: -#if defined(HOST_WORDS_BIGENDIAN) - pwd->w[2] =3D pws->w[3]; - pwd->w[3] =3D pwt->w[3]; - pwd->w[0] =3D pws->w[1]; - pwd->w[1] =3D pwt->w[1]; -#else - pwd->w[3] =3D pws->w[2]; - pwd->w[2] =3D pwt->w[2]; - pwd->w[1] =3D pws->w[0]; - pwd->w[0] =3D pwt->w[0]; -#endif - break; - case DF_DOUBLE: - pwd->d[1] =3D pws->d[0]; - pwd->d[0] =3D pwt->d[0]; - break; - default: - assert(0); - } -} - -void helper_msa_ilvod_df(CPUMIPSState *env, uint32_t df, uint32_t wd, - uint32_t ws, uint32_t wt) -{ - wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); - wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); - wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); - - switch (df) { - case DF_BYTE: -#if defined(HOST_WORDS_BIGENDIAN) - pwd->b[7] =3D pwt->b[6]; - pwd->b[6] =3D pws->b[6]; - pwd->b[5] =3D pwt->b[4]; - pwd->b[4] =3D pws->b[4]; - pwd->b[3] =3D pwt->b[2]; - pwd->b[2] =3D pws->b[2]; - pwd->b[1] =3D pwt->b[0]; - pwd->b[0] =3D pws->b[0]; - pwd->b[15] =3D pwt->b[14]; - pwd->b[14] =3D pws->b[14]; - pwd->b[13] =3D pwt->b[12]; - pwd->b[12] =3D pws->b[12]; - pwd->b[11] =3D pwt->b[10]; - pwd->b[10] =3D pws->b[10]; - pwd->b[9] =3D pwt->b[8]; - pwd->b[8] =3D pws->b[8]; -#else - pwd->b[0] =3D pwt->b[1]; - pwd->b[1] =3D pws->b[1]; - pwd->b[2] =3D pwt->b[3]; - pwd->b[3] =3D pws->b[3]; - pwd->b[4] =3D pwt->b[5]; - pwd->b[5] =3D pws->b[5]; - pwd->b[6] =3D pwt->b[7]; - pwd->b[7] =3D pws->b[7]; - pwd->b[8] =3D pwt->b[9]; - pwd->b[9] =3D pws->b[9]; - pwd->b[10] =3D pwt->b[11]; - pwd->b[11] =3D pws->b[11]; - pwd->b[12] =3D pwt->b[13]; - pwd->b[13] =3D pws->b[13]; - pwd->b[14] =3D pwt->b[15]; - pwd->b[15] =3D pws->b[15]; -#endif - break; - case DF_HALF: -#if defined(HOST_WORDS_BIGENDIAN) - pwd->h[3] =3D pwt->h[2]; - pwd->h[2] =3D pws->h[2]; - pwd->h[1] =3D pwt->h[0]; - pwd->h[0] =3D pws->h[0]; - pwd->h[7] =3D pwt->h[6]; - pwd->h[6] =3D pws->h[6]; - pwd->h[5] =3D pwt->h[4]; - pwd->h[4] =3D pws->h[4]; -#else - pwd->h[0] =3D pwt->h[1]; - pwd->h[1] =3D pws->h[1]; - pwd->h[2] =3D pwt->h[3]; - pwd->h[3] =3D pws->h[3]; - pwd->h[4] =3D pwt->h[5]; - pwd->h[5] =3D pws->h[5]; - pwd->h[6] =3D pwt->h[7]; - pwd->h[7] =3D pws->h[7]; -#endif - break; - case DF_WORD: -#if defined(HOST_WORDS_BIGENDIAN) - pwd->w[1] =3D pwt->w[0]; - pwd->w[0] =3D pws->w[0]; - pwd->w[3] =3D pwt->w[2]; - pwd->w[2] =3D pws->w[2]; -#else - pwd->w[0] =3D pwt->w[1]; - pwd->w[1] =3D pws->w[1]; - pwd->w[2] =3D pwt->w[3]; - pwd->w[3] =3D pws->w[3]; -#endif - break; - case DF_DOUBLE: - pwd->d[0] =3D pwt->d[1]; - pwd->d[1] =3D pws->d[1]; - break; - default: - assert(0); - } -} - -void helper_msa_ilvl_df(CPUMIPSState *env, uint32_t df, uint32_t wd, - uint32_t ws, uint32_t wt) -{ - wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); - wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); - wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); - - switch (df) { - case DF_BYTE: -#if defined(HOST_WORDS_BIGENDIAN) - pwd->b[7] =3D pwt->b[15]; - pwd->b[6] =3D pws->b[15]; - pwd->b[5] =3D pwt->b[14]; - pwd->b[4] =3D pws->b[14]; - pwd->b[3] =3D pwt->b[13]; - pwd->b[2] =3D pws->b[13]; - pwd->b[1] =3D pwt->b[12]; - pwd->b[0] =3D pws->b[12]; - pwd->b[15] =3D pwt->b[11]; - pwd->b[14] =3D pws->b[11]; - pwd->b[13] =3D pwt->b[10]; - pwd->b[12] =3D pws->b[10]; - pwd->b[11] =3D pwt->b[9]; - pwd->b[10] =3D pws->b[9]; - pwd->b[9] =3D pwt->b[8]; - pwd->b[8] =3D pws->b[8]; -#else - pwd->b[0] =3D pwt->b[8]; - pwd->b[1] =3D pws->b[8]; - pwd->b[2] =3D pwt->b[9]; - pwd->b[3] =3D pws->b[9]; - pwd->b[4] =3D pwt->b[10]; - pwd->b[5] =3D pws->b[10]; - pwd->b[6] =3D pwt->b[11]; - pwd->b[7] =3D pws->b[11]; - pwd->b[8] =3D pwt->b[12]; - pwd->b[9] =3D pws->b[12]; - pwd->b[10] =3D pwt->b[13]; - pwd->b[11] =3D pws->b[13]; - pwd->b[12] =3D pwt->b[14]; - pwd->b[13] =3D pws->b[14]; - pwd->b[14] =3D pwt->b[15]; - pwd->b[15] =3D pws->b[15]; -#endif - break; - case DF_HALF: -#if defined(HOST_WORDS_BIGENDIAN) - pwd->h[3] =3D pwt->h[7]; - pwd->h[2] =3D pws->h[7]; - pwd->h[1] =3D pwt->h[6]; - pwd->h[0] =3D pws->h[6]; - pwd->h[7] =3D pwt->h[5]; - pwd->h[6] =3D pws->h[5]; - pwd->h[5] =3D pwt->h[4]; - pwd->h[4] =3D pws->h[4]; -#else - pwd->h[0] =3D pwt->h[4]; - pwd->h[1] =3D pws->h[4]; - pwd->h[2] =3D pwt->h[5]; - pwd->h[3] =3D pws->h[5]; - pwd->h[4] =3D pwt->h[6]; - pwd->h[5] =3D pws->h[6]; - pwd->h[6] =3D pwt->h[7]; - pwd->h[7] =3D pws->h[7]; -#endif - break; - case DF_WORD: -#if defined(HOST_WORDS_BIGENDIAN) - pwd->w[1] =3D pwt->w[3]; - pwd->w[0] =3D pws->w[3]; - pwd->w[3] =3D pwt->w[2]; - pwd->w[2] =3D pws->w[2]; -#else - pwd->w[0] =3D pwt->w[2]; - pwd->w[1] =3D pws->w[2]; - pwd->w[2] =3D pwt->w[3]; - pwd->w[3] =3D pws->w[3]; -#endif - break; - case DF_DOUBLE: - pwd->d[0] =3D pwt->d[1]; - pwd->d[1] =3D pws->d[1]; - break; - default: - assert(0); - } -} - -void helper_msa_ilvr_df(CPUMIPSState *env, uint32_t df, uint32_t wd, - uint32_t ws, uint32_t wt) -{ - wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); - wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); - wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); - - switch (df) { - case DF_BYTE: -#if defined(HOST_WORDS_BIGENDIAN) - pwd->b[8] =3D pws->b[0]; - pwd->b[9] =3D pwt->b[0]; - pwd->b[10] =3D pws->b[1]; - pwd->b[11] =3D pwt->b[1]; - pwd->b[12] =3D pws->b[2]; - pwd->b[13] =3D pwt->b[2]; - pwd->b[14] =3D pws->b[3]; - pwd->b[15] =3D pwt->b[3]; - pwd->b[0] =3D pws->b[4]; - pwd->b[1] =3D pwt->b[4]; - pwd->b[2] =3D pws->b[5]; - pwd->b[3] =3D pwt->b[5]; - pwd->b[4] =3D pws->b[6]; - pwd->b[5] =3D pwt->b[6]; - pwd->b[6] =3D pws->b[7]; - pwd->b[7] =3D pwt->b[7]; -#else - pwd->b[15] =3D pws->b[7]; - pwd->b[14] =3D pwt->b[7]; - pwd->b[13] =3D pws->b[6]; - pwd->b[12] =3D pwt->b[6]; - pwd->b[11] =3D pws->b[5]; - pwd->b[10] =3D pwt->b[5]; - pwd->b[9] =3D pws->b[4]; - pwd->b[8] =3D pwt->b[4]; - pwd->b[7] =3D pws->b[3]; - pwd->b[6] =3D pwt->b[3]; - pwd->b[5] =3D pws->b[2]; - pwd->b[4] =3D pwt->b[2]; - pwd->b[3] =3D pws->b[1]; - pwd->b[2] =3D pwt->b[1]; - pwd->b[1] =3D pws->b[0]; - pwd->b[0] =3D pwt->b[0]; -#endif - break; - case DF_HALF: -#if defined(HOST_WORDS_BIGENDIAN) - pwd->h[4] =3D pws->h[0]; - pwd->h[5] =3D pwt->h[0]; - pwd->h[6] =3D pws->h[1]; - pwd->h[7] =3D pwt->h[1]; - pwd->h[0] =3D pws->h[2]; - pwd->h[1] =3D pwt->h[2]; - pwd->h[2] =3D pws->h[3]; - pwd->h[3] =3D pwt->h[3]; -#else - pwd->h[7] =3D pws->h[3]; - pwd->h[6] =3D pwt->h[3]; - pwd->h[5] =3D pws->h[2]; - pwd->h[4] =3D pwt->h[2]; - pwd->h[3] =3D pws->h[1]; - pwd->h[2] =3D pwt->h[1]; - pwd->h[1] =3D pws->h[0]; - pwd->h[0] =3D pwt->h[0]; -#endif - break; - case DF_WORD: -#if defined(HOST_WORDS_BIGENDIAN) - pwd->w[2] =3D pws->w[0]; - pwd->w[3] =3D pwt->w[0]; - pwd->w[0] =3D pws->w[1]; - pwd->w[1] =3D pwt->w[1]; -#else - pwd->w[3] =3D pws->w[1]; - pwd->w[2] =3D pwt->w[1]; - pwd->w[1] =3D pws->w[0]; - pwd->w[0] =3D pwt->w[0]; -#endif - break; - case DF_DOUBLE: - pwd->d[1] =3D pws->d[0]; - pwd->d[0] =3D pwt->d[0]; - break; - default: - assert(0); - } -} - void helper_msa_pckev_df(CPUMIPSState *env, uint32_t df, uint32_t wd, uint32_t ws, uint32_t wt) { diff --git a/target/mips/translate.c b/target/mips/translate.c index 7a35c26..ea8b8f4 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -28770,6 +28770,70 @@ static void gen_msa_3r(CPUMIPSState *env, DisasCon= text *ctx) break; } break; + case OPC_ILVEV_df: + switch (df) { + case DF_BYTE: + gen_helper_msa_ilvev_b(cpu_env, twd, tws, twt); + break; + case DF_HALF: + gen_helper_msa_ilvev_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_ilvev_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_ilvev_d(cpu_env, twd, tws, twt); + break; + } + break; + case OPC_ILVOD_df: + switch (df) { + case DF_BYTE: + gen_helper_msa_ilvod_b(cpu_env, twd, tws, twt); + break; + case DF_HALF: + gen_helper_msa_ilvod_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_ilvod_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_ilvod_d(cpu_env, twd, tws, twt); + break; + } + break; + case OPC_ILVL_df: + switch (df) { + case DF_BYTE: + gen_helper_msa_ilvl_b(cpu_env, twd, tws, twt); + break; + case DF_HALF: + gen_helper_msa_ilvl_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_ilvl_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_ilvl_d(cpu_env, twd, tws, twt); + break; + } + break; + case OPC_ILVR_df: + switch (df) { + case DF_BYTE: + gen_helper_msa_ilvr_b(cpu_env, twd, tws, twt); + break; + case DF_HALF: + gen_helper_msa_ilvr_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_ilvr_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_ilvr_d(cpu_env, twd, tws, twt); + break; + } + break; case OPC_SLL_df: gen_helper_msa_sll_df(cpu_env, tdf, twd, tws, twt); break; @@ -28842,21 +28906,9 @@ static void gen_msa_3r(CPUMIPSState *env, DisasCon= text *ctx) case OPC_ASUB_S_df: gen_helper_msa_asub_s_df(cpu_env, tdf, twd, tws, twt); break; - case OPC_ILVL_df: - gen_helper_msa_ilvl_df(cpu_env, tdf, twd, tws, twt); - break; case OPC_ASUB_U_df: gen_helper_msa_asub_u_df(cpu_env, tdf, twd, tws, twt); break; - case OPC_ILVR_df: - gen_helper_msa_ilvr_df(cpu_env, tdf, twd, tws, twt); - break; - case OPC_ILVEV_df: - gen_helper_msa_ilvev_df(cpu_env, tdf, twd, tws, twt); - break; - case OPC_ILVOD_df: - gen_helper_msa_ilvod_df(cpu_env, tdf, twd, tws, twt); - break; =20 case OPC_DOTP_S_df: case OPC_DOTP_U_df: --=20 2.7.4