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X-Received-From: 2a00:1450:4864:20::432 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Dmitry Poletaev Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Dmitry Poletaev There is a problem, that you don't have access to the data using cpu_memory= _rw_debug() function when in SMM. You can't remotely debug SMM mode program= because of that for example. Likely attrs version of get_phys_page_debug should be used to get correct a= sidx at the end to handle access properly. Here the patch to fix it. Signed-off-by: Dmitry Poletaev Signed-off-by: Paolo Bonzini --- target/i386/cpu.c | 2 +- target/i386/cpu.h | 3 ++- target/i386/helper.c | 5 ++++- 3 files changed, 7 insertions(+), 3 deletions(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 313a2ef..8fcb571 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -6245,7 +6245,7 @@ static void x86_cpu_common_class_init(ObjectClass *oc= , void *data) #ifndef CONFIG_USER_ONLY cc->asidx_from_attrs =3D x86_asidx_from_attrs; cc->get_memory_mapping =3D x86_cpu_get_memory_mapping; - cc->get_phys_page_debug =3D x86_cpu_get_phys_page_debug; + cc->get_phys_page_attrs_debug =3D x86_cpu_get_phys_page_attrs_debug; cc->write_elf64_note =3D x86_cpu_write_elf64_note; cc->write_elf64_qemunote =3D x86_cpu_write_elf64_qemunote; cc->write_elf32_note =3D x86_cpu_write_elf32_note; diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 033991c..eaa5395 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -1690,7 +1690,8 @@ void x86_cpu_get_memory_mapping(CPUState *cpu, Memory= MappingList *list, =20 void x86_cpu_dump_state(CPUState *cs, FILE *f, int flags); =20 -hwaddr x86_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); +hwaddr x86_cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr, + MemTxAttrs *attrs); =20 int x86_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg); int x86_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); diff --git a/target/i386/helper.c b/target/i386/helper.c index 0fa51be..c3a6e4f 100644 --- a/target/i386/helper.c +++ b/target/i386/helper.c @@ -715,7 +715,8 @@ void cpu_x86_update_cr4(CPUX86State *env, uint32_t new_= cr4) } =20 #if !defined(CONFIG_USER_ONLY) -hwaddr x86_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) +hwaddr x86_cpu_get_phys_page_attrs_debug(CPUState *cs, vaddr addr, + MemTxAttrs *attrs) { X86CPU *cpu =3D X86_CPU(cs); CPUX86State *env =3D &cpu->env; @@ -725,6 +726,8 @@ hwaddr x86_cpu_get_phys_page_debug(CPUState *cs, vaddr = addr) uint32_t page_offset; int page_size; =20 + *attrs =3D cpu_get_mem_attrs(env); + a20_mask =3D x86_get_a20_mask(env); if (!(env->cr[0] & CR0_PG_MASK)) { pte =3D addr & a20_mask; --=20 1.8.3.1