From nobody Tue Feb 10 14:33:38 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1569944573; cv=none; d=zoho.com; s=zohoarc; b=TdJd1NNd6WPtVn/tIGRkwI5UvcMor0/DALamGi7cRK5vaxiXbmitm4+UVLHNle1nnVx+DB8+39N2pOHyvWTbvdMqucZrD9lKbYrmX+KFNvBACTiUCSurL2yHT7GbBj7AJEdPS/Svp936KJIL4BdXwmWiXElJj8WEv0lZPb+/Rvc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1569944573; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=87fS+veVYvALbQ9BBKug99F/Sq7EBfYV+NZdntH9mLU=; b=F13p8q23pr5UJhxIFNTGzxwfs/KsAtv91luawuB/2Q0I370nuWsEJblDHxRKXhODUC+a1z6cPxZ025wg4KbprWZk0faGOzqT8DDl72aY7n13+dNl1vy0lLSgrTIyaSDjEp+HzWrq1wbjLxRoeurrYnBOc6xoGlZpG4xtPElhp28= ARC-Authentication-Results: i=1; mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1569944573658273.1034786584878; Tue, 1 Oct 2019 08:42:53 -0700 (PDT) Received: from localhost ([::1]:43592 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iFKId-0003xc-UV for importer@patchew.org; Tue, 01 Oct 2019 11:42:51 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:45464) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iFJtr-0004x3-Sq for qemu-devel@nongnu.org; Tue, 01 Oct 2019 11:17:17 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iFJtp-00025G-GG for qemu-devel@nongnu.org; Tue, 01 Oct 2019 11:17:15 -0400 Received: from mx2.rt-rk.com ([89.216.37.149]:59983 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1iFJtp-0001ug-5g for qemu-devel@nongnu.org; Tue, 01 Oct 2019 11:17:13 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id 4D4231A23C5; Tue, 1 Oct 2019 17:15:55 +0200 (CEST) Received: from rtrkw774-lin.domain.local (rtrkw774-lin.domain.local [10.10.13.55]) by mail.rt-rk.com (Postfix) with ESMTPSA id 0A0E81A23C0; Tue, 1 Oct 2019 17:15:55 +0200 (CEST) X-Virus-Scanned: amavisd-new at rt-rk.com From: Aleksandar Markovic To: qemu-devel@nongnu.org Subject: [PULL 16/18] target/mips: msa: Split helpers for MOD_. Date: Tue, 1 Oct 2019 17:15:42 +0200 Message-Id: <1569942944-10381-17-git-send-email-aleksandar.markovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1569942944-10381-1-git-send-email-aleksandar.markovic@rt-rk.com> References: <1569942944-10381-1-git-send-email-aleksandar.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 89.216.37.149 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, amarkovic@wavecomp.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Aleksandar Markovic Achieves clearer code and slightly better performance. Signed-off-by: Aleksandar Markovic Reviewed-by: Aleksandar Rikalo Message-Id: <1569415572-19635-19-git-send-email-aleksandar.markovic@rt-rk.c= om> --- target/mips/helper.h | 12 +++- target/mips/msa_helper.c | 164 +++++++++++++++++++++++++++++++++++++++++--= ---- target/mips/translate.c | 38 +++++++++-- 3 files changed, 188 insertions(+), 26 deletions(-) diff --git a/target/mips/helper.h b/target/mips/helper.h index ec4982f..cc216f7 100644 --- a/target/mips/helper.h +++ b/target/mips/helper.h @@ -877,6 +877,16 @@ DEF_HELPER_4(msa_div_u_h, void, env, i32, i32, i32) DEF_HELPER_4(msa_div_u_w, void, env, i32, i32, i32) DEF_HELPER_4(msa_div_u_d, void, env, i32, i32, i32) =20 +DEF_HELPER_4(msa_mod_u_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_mod_u_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_mod_u_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_mod_u_d, void, env, i32, i32, i32) + +DEF_HELPER_4(msa_mod_s_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_mod_s_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_mod_s_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_mod_s_d, void, env, i32, i32, i32) + =20 DEF_HELPER_4(msa_andi_b, void, env, i32, i32, i32) DEF_HELPER_4(msa_ori_b, void, env, i32, i32, i32) @@ -939,8 +949,6 @@ DEF_HELPER_5(msa_asub_u_df, void, env, i32, i32, i32, i= 32) DEF_HELPER_5(msa_mulv_df, void, env, i32, i32, i32, i32) DEF_HELPER_5(msa_maddv_df, void, env, i32, i32, i32, i32) DEF_HELPER_5(msa_msubv_df, void, env, i32, i32, i32, i32) -DEF_HELPER_5(msa_mod_s_df, void, env, i32, i32, i32, i32) -DEF_HELPER_5(msa_mod_u_df, void, env, i32, i32, i32, i32) DEF_HELPER_5(msa_dotp_s_df, void, env, i32, i32, i32, i32) DEF_HELPER_5(msa_dotp_u_df, void, env, i32, i32, i32, i32) DEF_HELPER_5(msa_dpadd_s_df, void, env, i32, i32, i32, i32) diff --git a/target/mips/msa_helper.c b/target/mips/msa_helper.c index ceccd8f..04fee66 100644 --- a/target/mips/msa_helper.c +++ b/target/mips/msa_helper.c @@ -1755,7 +1755,152 @@ void helper_msa_div_u_d(CPUMIPSState *env, * +---------------+------------------------------------------------------= ----+ */ =20 -/* TODO: insert Int Modulo group helpers here */ +static inline int64_t msa_mod_s_df(uint32_t df, int64_t arg1, int64_t arg2) +{ + if (arg1 =3D=3D DF_MIN_INT(df) && arg2 =3D=3D -1) { + return 0; + } + return arg2 ? arg1 % arg2 : arg1; +} + +void helper_msa_mod_s_b(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); + + pwd->b[0] =3D msa_mod_s_df(DF_BYTE, pws->b[0], pwt->b[0]); + pwd->b[1] =3D msa_mod_s_df(DF_BYTE, pws->b[1], pwt->b[1]); + pwd->b[2] =3D msa_mod_s_df(DF_BYTE, pws->b[2], pwt->b[2]); + pwd->b[3] =3D msa_mod_s_df(DF_BYTE, pws->b[3], pwt->b[3]); + pwd->b[4] =3D msa_mod_s_df(DF_BYTE, pws->b[4], pwt->b[4]); + pwd->b[5] =3D msa_mod_s_df(DF_BYTE, pws->b[5], pwt->b[5]); + pwd->b[6] =3D msa_mod_s_df(DF_BYTE, pws->b[6], pwt->b[6]); + pwd->b[7] =3D msa_mod_s_df(DF_BYTE, pws->b[7], pwt->b[7]); + pwd->b[8] =3D msa_mod_s_df(DF_BYTE, pws->b[8], pwt->b[8]); + pwd->b[9] =3D msa_mod_s_df(DF_BYTE, pws->b[9], pwt->b[9]); + pwd->b[10] =3D msa_mod_s_df(DF_BYTE, pws->b[10], pwt->b[10]); + pwd->b[11] =3D msa_mod_s_df(DF_BYTE, pws->b[11], pwt->b[11]); + pwd->b[12] =3D msa_mod_s_df(DF_BYTE, pws->b[12], pwt->b[12]); + pwd->b[13] =3D msa_mod_s_df(DF_BYTE, pws->b[13], pwt->b[13]); + pwd->b[14] =3D msa_mod_s_df(DF_BYTE, pws->b[14], pwt->b[14]); + pwd->b[15] =3D msa_mod_s_df(DF_BYTE, pws->b[15], pwt->b[15]); +} + +void helper_msa_mod_s_h(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); + + pwd->h[0] =3D msa_mod_s_df(DF_HALF, pws->h[0], pwt->h[0]); + pwd->h[1] =3D msa_mod_s_df(DF_HALF, pws->h[1], pwt->h[1]); + pwd->h[2] =3D msa_mod_s_df(DF_HALF, pws->h[2], pwt->h[2]); + pwd->h[3] =3D msa_mod_s_df(DF_HALF, pws->h[3], pwt->h[3]); + pwd->h[4] =3D msa_mod_s_df(DF_HALF, pws->h[4], pwt->h[4]); + pwd->h[5] =3D msa_mod_s_df(DF_HALF, pws->h[5], pwt->h[5]); + pwd->h[6] =3D msa_mod_s_df(DF_HALF, pws->h[6], pwt->h[6]); + pwd->h[7] =3D msa_mod_s_df(DF_HALF, pws->h[7], pwt->h[7]); +} + +void helper_msa_mod_s_w(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); + + pwd->w[0] =3D msa_mod_s_df(DF_WORD, pws->w[0], pwt->w[0]); + pwd->w[1] =3D msa_mod_s_df(DF_WORD, pws->w[1], pwt->w[1]); + pwd->w[2] =3D msa_mod_s_df(DF_WORD, pws->w[2], pwt->w[2]); + pwd->w[3] =3D msa_mod_s_df(DF_WORD, pws->w[3], pwt->w[3]); +} + +void helper_msa_mod_s_d(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); + + pwd->d[0] =3D msa_mod_s_df(DF_DOUBLE, pws->d[0], pwt->d[0]); + pwd->d[1] =3D msa_mod_s_df(DF_DOUBLE, pws->d[1], pwt->d[1]); +} + +static inline int64_t msa_mod_u_df(uint32_t df, int64_t arg1, int64_t arg2) +{ + uint64_t u_arg1 =3D UNSIGNED(arg1, df); + uint64_t u_arg2 =3D UNSIGNED(arg2, df); + return u_arg2 ? u_arg1 % u_arg2 : u_arg1; +} + +void helper_msa_mod_u_b(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); + + pwd->b[0] =3D msa_mod_u_df(DF_BYTE, pws->b[0], pwt->b[0]); + pwd->b[1] =3D msa_mod_u_df(DF_BYTE, pws->b[1], pwt->b[1]); + pwd->b[2] =3D msa_mod_u_df(DF_BYTE, pws->b[2], pwt->b[2]); + pwd->b[3] =3D msa_mod_u_df(DF_BYTE, pws->b[3], pwt->b[3]); + pwd->b[4] =3D msa_mod_u_df(DF_BYTE, pws->b[4], pwt->b[4]); + pwd->b[5] =3D msa_mod_u_df(DF_BYTE, pws->b[5], pwt->b[5]); + pwd->b[6] =3D msa_mod_u_df(DF_BYTE, pws->b[6], pwt->b[6]); + pwd->b[7] =3D msa_mod_u_df(DF_BYTE, pws->b[7], pwt->b[7]); + pwd->b[8] =3D msa_mod_u_df(DF_BYTE, pws->b[8], pwt->b[8]); + pwd->b[9] =3D msa_mod_u_df(DF_BYTE, pws->b[9], pwt->b[9]); + pwd->b[10] =3D msa_mod_u_df(DF_BYTE, pws->b[10], pwt->b[10]); + pwd->b[11] =3D msa_mod_u_df(DF_BYTE, pws->b[11], pwt->b[11]); + pwd->b[12] =3D msa_mod_u_df(DF_BYTE, pws->b[12], pwt->b[12]); + pwd->b[13] =3D msa_mod_u_df(DF_BYTE, pws->b[13], pwt->b[13]); + pwd->b[14] =3D msa_mod_u_df(DF_BYTE, pws->b[14], pwt->b[14]); + pwd->b[15] =3D msa_mod_u_df(DF_BYTE, pws->b[15], pwt->b[15]); +} + +void helper_msa_mod_u_h(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); + + pwd->h[0] =3D msa_mod_u_df(DF_HALF, pws->h[0], pwt->h[0]); + pwd->h[1] =3D msa_mod_u_df(DF_HALF, pws->h[1], pwt->h[1]); + pwd->h[2] =3D msa_mod_u_df(DF_HALF, pws->h[2], pwt->h[2]); + pwd->h[3] =3D msa_mod_u_df(DF_HALF, pws->h[3], pwt->h[3]); + pwd->h[4] =3D msa_mod_u_df(DF_HALF, pws->h[4], pwt->h[4]); + pwd->h[5] =3D msa_mod_u_df(DF_HALF, pws->h[5], pwt->h[5]); + pwd->h[6] =3D msa_mod_u_df(DF_HALF, pws->h[6], pwt->h[6]); + pwd->h[7] =3D msa_mod_u_df(DF_HALF, pws->h[7], pwt->h[7]); +} + +void helper_msa_mod_u_w(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); + + pwd->w[0] =3D msa_mod_u_df(DF_WORD, pws->w[0], pwt->w[0]); + pwd->w[1] =3D msa_mod_u_df(DF_WORD, pws->w[1], pwt->w[1]); + pwd->w[2] =3D msa_mod_u_df(DF_WORD, pws->w[2], pwt->w[2]); + pwd->w[3] =3D msa_mod_u_df(DF_WORD, pws->w[3], pwt->w[3]); +} + +void helper_msa_mod_u_d(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); + + pwd->d[0] =3D msa_mod_u_df(DF_DOUBLE, pws->d[0], pwt->d[0]); + pwd->d[1] =3D msa_mod_u_df(DF_DOUBLE, pws->d[1], pwt->d[1]); +} =20 =20 /* @@ -2434,21 +2579,6 @@ static inline int64_t msa_mulv_df(uint32_t df, int64= _t arg1, int64_t arg2) return arg1 * arg2; } =20 -static inline int64_t msa_mod_s_df(uint32_t df, int64_t arg1, int64_t arg2) -{ - if (arg1 =3D=3D DF_MIN_INT(df) && arg2 =3D=3D -1) { - return 0; - } - return arg2 ? arg1 % arg2 : arg1; -} - -static inline int64_t msa_mod_u_df(uint32_t df, int64_t arg1, int64_t arg2) -{ - uint64_t u_arg1 =3D UNSIGNED(arg1, df); - uint64_t u_arg2 =3D UNSIGNED(arg2, df); - return u_arg2 ? u_arg1 % u_arg2 : u_arg1; -} - #define SIGNED_EVEN(a, df) \ ((((int64_t)(a)) << (64 - DF_BITS(df) / 2)) >> (64 - DF_BITS(df) /= 2)) =20 @@ -2654,8 +2784,6 @@ MSA_BINOP_DF(subsuu_s) MSA_BINOP_DF(asub_s) MSA_BINOP_DF(asub_u) MSA_BINOP_DF(mulv) -MSA_BINOP_DF(mod_s) -MSA_BINOP_DF(mod_u) MSA_BINOP_DF(dotp_s) MSA_BINOP_DF(dotp_u) MSA_BINOP_DF(srar) diff --git a/target/mips/translate.c b/target/mips/translate.c index 27eca0a..5039716 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -28642,6 +28642,38 @@ static void gen_msa_3r(CPUMIPSState *env, DisasCon= text *ctx) break; } break; + case OPC_MOD_S_df: + switch (df) { + case DF_BYTE: + gen_helper_msa_mod_s_b(cpu_env, twd, tws, twt); + break; + case DF_HALF: + gen_helper_msa_mod_s_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_mod_s_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_mod_s_d(cpu_env, twd, tws, twt); + break; + } + break; + case OPC_MOD_U_df: + switch (df) { + case DF_BYTE: + gen_helper_msa_mod_u_b(cpu_env, twd, tws, twt); + break; + case DF_HALF: + gen_helper_msa_mod_u_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_mod_u_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_mod_u_d(cpu_env, twd, tws, twt); + break; + } + break; case OPC_SLL_df: gen_helper_msa_sll_df(cpu_env, tdf, twd, tws, twt); break; @@ -28738,18 +28770,12 @@ static void gen_msa_3r(CPUMIPSState *env, DisasCo= ntext *ctx) case OPC_MAX_A_df: gen_helper_msa_max_a_df(cpu_env, tdf, twd, tws, twt); break; - case OPC_MOD_S_df: - gen_helper_msa_mod_s_df(cpu_env, tdf, twd, tws, twt); - break; case OPC_ILVEV_df: gen_helper_msa_ilvev_df(cpu_env, tdf, twd, tws, twt); break; case OPC_MIN_A_df: gen_helper_msa_min_a_df(cpu_env, tdf, twd, tws, twt); break; - case OPC_MOD_U_df: - gen_helper_msa_mod_u_df(cpu_env, tdf, twd, tws, twt); - break; case OPC_ILVOD_df: gen_helper_msa_ilvod_df(cpu_env, tdf, twd, tws, twt); break; --=20 2.7.4