From nobody Sat May 4 18:23:24 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1569943208; cv=none; d=zoho.com; s=zohoarc; b=og64/0SNAZFwJtST1wvPSKEjV1EKsZh9xcf1fnkLlwgJWPhqMjHcZ/aYUR1hPY7xFCA5r6Bx8f8CU9z357oHqIo98/60s/qXqUcXECwcx5UPCS7ju215ZMuaDRbfHaRlAT4gUCnoNc1YrfGXTrSf2Ck1nG22/OBO3kbD6QoBJJ4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1569943208; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=obw8AhChUs4mjvwzmOyrRFgrcy9esJljOpmTu/4I9D0=; b=gALw/u16NiWqeNy4f4V3h+bNwuj54xuxfa6lbTatqGwLp0sG80c+lzAtfamt15wb1pWx1EuvUs/Vyb4T7qqSTyrFlMEiaPjusHshWBD+cYMOtTzYJK+72OEBFGn0qsZoBrsu93MbqPnLqcniASdLK3NYFuqqZqJOD8tNFvgbL2c= ARC-Authentication-Results: i=1; mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (209.51.188.17 [209.51.188.17]) by mx.zohomail.com with SMTPS id 1569943208299954.808691891157; Tue, 1 Oct 2019 08:20:08 -0700 (PDT) Received: from localhost ([::1]:43328 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iFJwU-0006SC-ER for importer@patchew.org; Tue, 01 Oct 2019 11:19:58 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:45306) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iFJte-0004gs-Ci for qemu-devel@nongnu.org; Tue, 01 Oct 2019 11:17:04 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iFJtc-0001sc-Mv for qemu-devel@nongnu.org; Tue, 01 Oct 2019 11:17:02 -0400 Received: from mx2.rt-rk.com ([89.216.37.149]:53431 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1iFJtc-0000zH-Av for qemu-devel@nongnu.org; Tue, 01 Oct 2019 11:17:00 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id A75C81A2397; Tue, 1 Oct 2019 17:15:54 +0200 (CEST) Received: from rtrkw774-lin.domain.local (rtrkw774-lin.domain.local [10.10.13.55]) by mail.rt-rk.com (Postfix) with ESMTPSA id 6579D1A22D4; Tue, 1 Oct 2019 17:15:54 +0200 (CEST) X-Virus-Scanned: amavisd-new at rt-rk.com From: Aleksandar Markovic To: qemu-devel@nongnu.org Subject: [PULL 01/18] target/mips: Clean up internal.h Date: Tue, 1 Oct 2019 17:15:27 +0200 Message-Id: <1569942944-10381-2-git-send-email-aleksandar.markovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1569942944-10381-1-git-send-email-aleksandar.markovic@rt-rk.com> References: <1569942944-10381-1-git-send-email-aleksandar.markovic@rt-rk.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 89.216.37.149 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, amarkovic@wavecomp.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" From: Aleksandar Markovic Mostly fix errors and warnings reported by 'checkpatch.pl -f'. Signed-off-by: Aleksandar Markovic Reviewed-by: Aleksandar Rikalo Reviewed-by: Philippe Mathieu-Daud=C3=A9 Message-Id: <1569331602-2586-3-git-send-email-aleksandar.markovic@rt-rk.com> --- target/mips/internal.h | 60 +++++++++++++++++++++++++++++++---------------= ---- 1 file changed, 37 insertions(+), 23 deletions(-) diff --git a/target/mips/internal.h b/target/mips/internal.h index 685e8d6..3f435b5 100644 --- a/target/mips/internal.h +++ b/target/mips/internal.h @@ -1,4 +1,5 @@ -/* mips internal definitions and helpers +/* + * MIPS internal definitions and helpers * * This work is licensed under the terms of the GNU GPL, version 2 or late= r. * See the COPYING file in the top-level directory. @@ -9,8 +10,10 @@ =20 #include "fpu/softfloat-helpers.h" =20 -/* MMU types, the first four entries have the same layout as the - CP0C0_MT field. */ +/* + * MMU types, the first four entries have the same layout as the + * CP0C0_MT field. + */ enum mips_mmu_types { MMU_TYPE_NONE, MMU_TYPE_R4000, @@ -160,9 +163,11 @@ static inline bool cpu_mips_hw_interrupts_enabled(CPUM= IPSState *env) !(env->CP0_Status & (1 << CP0St_EXL)) && !(env->CP0_Status & (1 << CP0St_ERL)) && !(env->hflags & MIPS_HFLAG_DM) && - /* Note that the TCStatus IXMT field is initialized to zero, - and only MT capable cores can set it to one. So we don't - need to check for MT capabilities here. */ + /* + * Note that the TCStatus IXMT field is initialized to zero, + * and only MT capable cores can set it to one. So we don't + * need to check for MT capabilities here. + */ !(env->active_tc.CP0_TCStatus & (1 << CP0TCSt_IXMT)); } =20 @@ -177,14 +182,18 @@ static inline bool cpu_mips_hw_interrupts_pending(CPU= MIPSState *env) status =3D env->CP0_Status & CP0Ca_IP_mask; =20 if (env->CP0_Config3 & (1 << CP0C3_VEIC)) { - /* A MIPS configured with a vectorizing external interrupt control= ler - will feed a vector into the Cause pending lines. The core treats - the status lines as a vector level, not as indiviual masks. */ + /* + * A MIPS configured with a vectorizing external interrupt control= ler + * will feed a vector into the Cause pending lines. The core treats + * the status lines as a vector level, not as indiviual masks. + */ r =3D pending > status; } else { - /* A MIPS configured with compatibility or VInt (Vectored Interrup= ts) - treats the pending lines as individual interrupt lines, the sta= tus - lines are individual masks. */ + /* + * A MIPS configured with compatibility or VInt (Vectored Interrup= ts) + * treats the pending lines as individual interrupt lines, the sta= tus + * lines are individual masks. + */ r =3D (pending & status) !=3D 0; } return r; @@ -275,12 +284,14 @@ static inline int mips_vpe_active(CPUMIPSState *env) active =3D 0; } =20 - /* Now verify that there are active thread contexts in the VPE. - - This assumes the CPU model will internally reschedule threads - if the active one goes to sleep. If there are no threads available - the active one will be in a sleeping state, and we can turn off - the entire VPE. */ + /* + * Now verify that there are active thread contexts in the VPE. + * + * This assumes the CPU model will internally reschedule threads + * if the active one goes to sleep. If there are no threads available + * the active one will be in a sleeping state, and we can turn off + * the entire VPE. + */ if (!(env->active_tc.CP0_TCStatus & (1 << CP0TCSt_A))) { /* TC is not activated. */ active =3D 0; @@ -326,7 +337,8 @@ static inline void compute_hflags(CPUMIPSState *env) if (!(env->CP0_Status & (1 << CP0St_EXL)) && !(env->CP0_Status & (1 << CP0St_ERL)) && !(env->hflags & MIPS_HFLAG_DM)) { - env->hflags |=3D (env->CP0_Status >> CP0St_KSU) & MIPS_HFLAG_KSU; + env->hflags |=3D (env->CP0_Status >> CP0St_KSU) & + MIPS_HFLAG_KSU; } #if defined(TARGET_MIPS64) if ((env->insn_flags & ISA_MIPS3) && @@ -403,10 +415,12 @@ static inline void compute_hflags(CPUMIPSState *env) env->hflags |=3D MIPS_HFLAG_COP1X; } } else if (env->insn_flags & ISA_MIPS4) { - /* All supported MIPS IV CPUs use the XX (CU3) to enable - and disable the MIPS IV extensions to the MIPS III ISA. - Some other MIPS IV CPUs ignore the bit, so the check here - would be too restrictive for them. */ + /* + * All supported MIPS IV CPUs use the XX (CU3) to enable + * and disable the MIPS IV extensions to the MIPS III ISA. + * Some other MIPS IV CPUs ignore the bit, so the check here + * would be too restrictive for them. + */ if (env->CP0_Status & (1U << CP0St_CU3)) { env->hflags |=3D MIPS_HFLAG_COP1X; } --=20 2.7.4 From nobody Sat May 4 18:23:24 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1569943208; cv=none; d=zoho.com; s=zohoarc; b=Vk6GLS/NQsEiuarKuVmuTkMYlr5Acm4mU8P+DMr4FQ85DVL0WHuLQ2BffyBjpMcRdwHgiuGY/WLn5nda9eeK3DNmwNejE2iRp6yMxhO3P/WyGJyOH7qMiTUyE/C0Csy9KStQEHrMNb5uOQpyNaSQD3uJGZB1TipcLGbAvAbBmzk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1569943208; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; 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Tue, 01 Oct 2019 11:17:01 -0400 Received: from mx2.rt-rk.com ([89.216.37.149]:53328 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1iFJtc-0000z3-8p for qemu-devel@nongnu.org; Tue, 01 Oct 2019 11:17:00 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id 9A3021A22DC; Tue, 1 Oct 2019 17:15:54 +0200 (CEST) Received: from rtrkw774-lin.domain.local (rtrkw774-lin.domain.local [10.10.13.55]) by mail.rt-rk.com (Postfix) with ESMTPSA id 6AE7D1A22D5; Tue, 1 Oct 2019 17:15:54 +0200 (CEST) X-Virus-Scanned: amavisd-new at rt-rk.com From: Aleksandar Markovic To: qemu-devel@nongnu.org Subject: [PULL 02/18] target/mips: Clean up kvm_mips.h Date: Tue, 1 Oct 2019 17:15:28 +0200 Message-Id: <1569942944-10381-3-git-send-email-aleksandar.markovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1569942944-10381-1-git-send-email-aleksandar.markovic@rt-rk.com> References: <1569942944-10381-1-git-send-email-aleksandar.markovic@rt-rk.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 89.216.37.149 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, amarkovic@wavecomp.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" From: Aleksandar Markovic Mostly fix errors and warnings reported by 'checkpatch.pl -f'. Signed-off-by: Aleksandar Markovic Reviewed-by: Aleksandar Rikalo Reviewed-by: Philippe Mathieu-Daud=C3=A9 Message-Id: <1569331602-2586-4-git-send-email-aleksandar.markovic@rt-rk.com> --- target/mips/kvm_mips.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/mips/kvm_mips.h b/target/mips/kvm_mips.h index ae957f3..1e40147 100644 --- a/target/mips/kvm_mips.h +++ b/target/mips/kvm_mips.h @@ -7,7 +7,7 @@ * * Copyright (C) 2012-2014 Imagination Technologies Ltd. * Authors: Sanjay Lal -*/ + */ =20 #ifndef KVM_MIPS_H #define KVM_MIPS_H --=20 2.7.4 From nobody Sat May 4 18:23:24 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1569943495; cv=none; d=zoho.com; s=zohoarc; b=a6yNLImgaX95Y3ccJnHG7jZSpXf+yo74afebQBKvZEZkJ9Wxx+SJ9UJi7lDJcV8bo6hMShHT5EeK0F4OE54s7ejBUbU0yvMZO0X2JpL1kuqwWVfNeTOHTDDxxzIFwrR9wj1ZhL7gnNWVcjz1greFFMJ8QZVFeJYBm5S/J4ecImk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1569943495; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=wG31zoD2OyIGgEOVCQodV6+tYjws5tk634OoePUqWCU=; b=StknU7Tb8LaAfCEEOxz/Ga4eCqNDypnLqwE477nlbJ6aVEejOTMZKxtDySUdlvyEVAHag6FRGP0PfYuMI5NLkRpSGl7uNqlH3m+eGKmzWyKKcMlIIfwiNE1BmTOZO18nFDllky8zlh6MvJahfWF+fw6TB8AtbIBCD2QJYdjAWPA= ARC-Authentication-Results: i=1; mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1569943495629149.59655644935629; Tue, 1 Oct 2019 08:24:55 -0700 (PDT) Received: from localhost ([::1]:43382 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iFK1F-0002zC-Tl for importer@patchew.org; Tue, 01 Oct 2019 11:24:53 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:45309) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iFJte-0004gt-IR for qemu-devel@nongnu.org; Tue, 01 Oct 2019 11:17:05 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iFJtc-0001sX-Mb for qemu-devel@nongnu.org; Tue, 01 Oct 2019 11:17:02 -0400 Received: from mx2.rt-rk.com ([89.216.37.149]:53433 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1iFJtc-0000zG-AK for qemu-devel@nongnu.org; Tue, 01 Oct 2019 11:17:00 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id B46351A23B4; Tue, 1 Oct 2019 17:15:54 +0200 (CEST) Received: from rtrkw774-lin.domain.local (rtrkw774-lin.domain.local [10.10.13.55]) by mail.rt-rk.com (Postfix) with ESMTPSA id 718971A22D9; Tue, 1 Oct 2019 17:15:54 +0200 (CEST) X-Virus-Scanned: amavisd-new at rt-rk.com From: Aleksandar Markovic To: qemu-devel@nongnu.org Subject: [PULL 03/18] target/mips: Clean up mips-defs.h Date: Tue, 1 Oct 2019 17:15:29 +0200 Message-Id: <1569942944-10381-4-git-send-email-aleksandar.markovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1569942944-10381-1-git-send-email-aleksandar.markovic@rt-rk.com> References: <1569942944-10381-1-git-send-email-aleksandar.markovic@rt-rk.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 89.216.37.149 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, amarkovic@wavecomp.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" From: Aleksandar Markovic Mostly fix errors and warnings reported by 'checkpatch.pl -f'. Signed-off-by: Aleksandar Markovic Reviewed-by: Aleksandar Rikalo Reviewed-by: Philippe Mathieu-Daud=C3=A9 Message-Id: <1569331602-2586-5-git-send-email-aleksandar.markovic@rt-rk.com> --- target/mips/mips-defs.h | 58 +++++++++++++++++++++++++++------------------= ---- 1 file changed, 32 insertions(+), 26 deletions(-) diff --git a/target/mips/mips-defs.h b/target/mips/mips-defs.h index bbf056a..a831bb4 100644 --- a/target/mips/mips-defs.h +++ b/target/mips/mips-defs.h @@ -1,8 +1,11 @@ #ifndef QEMU_MIPS_DEFS_H #define QEMU_MIPS_DEFS_H =20 -/* If we want to use host float regs... */ -//#define USE_HOST_FLOAT_REGS +/* + * If we want to use host float regs... + * + * #define USE_HOST_FLOAT_REGS + */ =20 /* Real pages are variable size... */ #define MIPS_TLB_MAX 128 @@ -57,43 +60,46 @@ #define ASE_MXU 0x0200000000000000ULL =20 /* MIPS CPU defines. */ -#define CPU_MIPS1 (ISA_MIPS1) -#define CPU_MIPS2 (CPU_MIPS1 | ISA_MIPS2) -#define CPU_MIPS3 (CPU_MIPS2 | ISA_MIPS3) -#define CPU_MIPS4 (CPU_MIPS3 | ISA_MIPS4) -#define CPU_VR54XX (CPU_MIPS4 | INSN_VR54XX) -#define CPU_R5900 (CPU_MIPS3 | INSN_R5900) -#define CPU_LOONGSON2E (CPU_MIPS3 | INSN_LOONGSON2E) -#define CPU_LOONGSON2F (CPU_MIPS3 | INSN_LOONGSON2F) +#define CPU_MIPS1 (ISA_MIPS1) +#define CPU_MIPS2 (CPU_MIPS1 | ISA_MIPS2) +#define CPU_MIPS3 (CPU_MIPS2 | ISA_MIPS3) +#define CPU_MIPS4 (CPU_MIPS3 | ISA_MIPS4) +#define CPU_VR54XX (CPU_MIPS4 | INSN_VR54XX) +#define CPU_R5900 (CPU_MIPS3 | INSN_R5900) +#define CPU_LOONGSON2E (CPU_MIPS3 | INSN_LOONGSON2E) +#define CPU_LOONGSON2F (CPU_MIPS3 | INSN_LOONGSON2F) =20 -#define CPU_MIPS5 (CPU_MIPS4 | ISA_MIPS5) +#define CPU_MIPS5 (CPU_MIPS4 | ISA_MIPS5) =20 /* MIPS Technologies "Release 1" */ -#define CPU_MIPS32 (CPU_MIPS2 | ISA_MIPS32) -#define CPU_MIPS64 (CPU_MIPS5 | CPU_MIPS32 | ISA_MIPS64) +#define CPU_MIPS32 (CPU_MIPS2 | ISA_MIPS32) +#define CPU_MIPS64 (CPU_MIPS5 | CPU_MIPS32 | ISA_MIPS64) =20 /* MIPS Technologies "Release 2" */ -#define CPU_MIPS32R2 (CPU_MIPS32 | ISA_MIPS32R2) -#define CPU_MIPS64R2 (CPU_MIPS64 | CPU_MIPS32R2 | ISA_MIPS64R2) +#define CPU_MIPS32R2 (CPU_MIPS32 | ISA_MIPS32R2) +#define CPU_MIPS64R2 (CPU_MIPS64 | CPU_MIPS32R2 | ISA_MIPS64R2) =20 /* MIPS Technologies "Release 3" */ -#define CPU_MIPS32R3 (CPU_MIPS32R2 | ISA_MIPS32R3) -#define CPU_MIPS64R3 (CPU_MIPS64R2 | CPU_MIPS32R3 | ISA_MIPS64R3) +#define CPU_MIPS32R3 (CPU_MIPS32R2 | ISA_MIPS32R3) +#define CPU_MIPS64R3 (CPU_MIPS64R2 | CPU_MIPS32R3 | ISA_MIPS64R3) =20 /* MIPS Technologies "Release 5" */ -#define CPU_MIPS32R5 (CPU_MIPS32R3 | ISA_MIPS32R5) -#define CPU_MIPS64R5 (CPU_MIPS64R3 | CPU_MIPS32R5 | ISA_MIPS64R5) +#define CPU_MIPS32R5 (CPU_MIPS32R3 | ISA_MIPS32R5) +#define CPU_MIPS64R5 (CPU_MIPS64R3 | CPU_MIPS32R5 | ISA_MIPS64R5) =20 /* MIPS Technologies "Release 6" */ -#define CPU_MIPS32R6 (CPU_MIPS32R5 | ISA_MIPS32R6) -#define CPU_MIPS64R6 (CPU_MIPS64R5 | CPU_MIPS32R6 | ISA_MIPS64R6) +#define CPU_MIPS32R6 (CPU_MIPS32R5 | ISA_MIPS32R6) +#define CPU_MIPS64R6 (CPU_MIPS64R5 | CPU_MIPS32R6 | ISA_MIPS64R6) =20 /* Wave Computing: "nanoMIPS" */ -#define CPU_NANOMIPS32 (CPU_MIPS32R6 | ISA_NANOMIPS32) +#define CPU_NANOMIPS32 (CPU_MIPS32R6 | ISA_NANOMIPS32) =20 -/* Strictly follow the architecture standard: - - Disallow "special" instruction handling for PMON/SPIM. - Note that we still maintain Count/Compare to match the host clock. */ -//#define MIPS_STRICT_STANDARD 1 +/* + * Strictly follow the architecture standard: + * - Disallow "special" instruction handling for PMON/SPIM. + * Note that we still maintain Count/Compare to match the host clock. + * + * #define MIPS_STRICT_STANDARD 1 + */ =20 #endif /* QEMU_MIPS_DEFS_H */ --=20 2.7.4 From nobody Sat May 4 18:23:24 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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Tue, 01 Oct 2019 11:17:00 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id ABAD71A23AB; Tue, 1 Oct 2019 17:15:54 +0200 (CEST) Received: from rtrkw774-lin.domain.local (rtrkw774-lin.domain.local [10.10.13.55]) by mail.rt-rk.com (Postfix) with ESMTPSA id 779AA1A22D8; Tue, 1 Oct 2019 17:15:54 +0200 (CEST) X-Virus-Scanned: amavisd-new at rt-rk.com From: Aleksandar Markovic To: qemu-devel@nongnu.org Subject: [PULL 04/18] target/mips: Clean up translate.c Date: Tue, 1 Oct 2019 17:15:30 +0200 Message-Id: <1569942944-10381-5-git-send-email-aleksandar.markovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1569942944-10381-1-git-send-email-aleksandar.markovic@rt-rk.com> References: <1569942944-10381-1-git-send-email-aleksandar.markovic@rt-rk.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 89.216.37.149 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, amarkovic@wavecomp.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" From: Aleksandar Markovic Mostly fix errors and warnings reported by 'checkpatch.pl -f'. Signed-off-by: Aleksandar Markovic Reviewed-by: Aleksandar Rikalo Reviewed-by: Philippe Mathieu-Daud=C3=A9 Message-Id: <1569331602-2586-7-git-send-email-aleksandar.markovic@rt-rk.com> --- target/mips/translate.c | 30 ++++++++++++++++++------------ 1 file changed, 18 insertions(+), 12 deletions(-) diff --git a/target/mips/translate.c b/target/mips/translate.c index f211995..cc5af2a 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -7118,7 +7118,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int= reg, int sel) tcg_gen_andi_tl(arg, arg, ~0xffff); register_name =3D "BadInstrX"; break; - default: + default: goto cp0_unimplemented; } break; @@ -7545,7 +7545,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int= reg, int sel) case CP0_REG31__KSCRATCH6: CP0_CHECK(ctx->kscrexist & (1 << sel)); tcg_gen_ld_tl(arg, cpu_env, - offsetof(CPUMIPSState, CP0_KScratch[sel-2])); + offsetof(CPUMIPSState, CP0_KScratch[sel - 2])); tcg_gen_ext32s_tl(arg, arg); register_name =3D "KScratch"; break; @@ -8295,7 +8295,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int= reg, int sel) case CP0_REG31__KSCRATCH6: CP0_CHECK(ctx->kscrexist & (1 << sel)); tcg_gen_st_tl(arg, cpu_env, - offsetof(CPUMIPSState, CP0_KScratch[sel-2])); + offsetof(CPUMIPSState, CP0_KScratch[sel - 2])); register_name =3D "KScratch"; break; default: @@ -8387,17 +8387,20 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, = int reg, int sel) break; case CP0_REG01__YQMASK: CP0_CHECK(ctx->insn_flags & ASE_MT); - tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_YQMask)= ); + tcg_gen_ld_tl(arg, cpu_env, + offsetof(CPUMIPSState, CP0_YQMask)); register_name =3D "YQMask"; break; case CP0_REG01__VPESCHEDULE: CP0_CHECK(ctx->insn_flags & ASE_MT); - tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_VPESche= dule)); + tcg_gen_ld_tl(arg, cpu_env, + offsetof(CPUMIPSState, CP0_VPESchedule)); register_name =3D "VPESchedule"; break; case CP0_REG01__VPESCHEFBACK: CP0_CHECK(ctx->insn_flags & ASE_MT); - tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_VPESche= FBack)); + tcg_gen_ld_tl(arg, cpu_env, + offsetof(CPUMIPSState, CP0_VPEScheFBack)); register_name =3D "VPEScheFBack"; break; case CP0_REG01__VPEOPT: @@ -8412,7 +8415,8 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, in= t reg, int sel) case CP0_REGISTER_02: switch (sel) { case CP0_REG02__ENTRYLO0: - tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_EntryLo= 0)); + tcg_gen_ld_tl(arg, cpu_env, + offsetof(CPUMIPSState, CP0_EntryLo0)); register_name =3D "EntryLo0"; break; case CP0_REG02__TCSTATUS: @@ -8756,7 +8760,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, in= t reg, int sel) gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config5)); register_name =3D "Config5"; break; - /* 6,7 are implementation dependent */ + /* 6,7 are implementation dependent */ case CP0_REG16__CONFIG6: gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config6)); register_name =3D "Config6"; @@ -8837,7 +8841,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, in= t reg, int sel) } break; case CP0_REGISTER_21: - /* Officially reserved, but sel 0 is used for R1x000 framemask */ + /* Officially reserved, but sel 0 is used for R1x000 framemask */ CP0_CHECK(!(ctx->insn_flags & ISA_MIPS32R6)); switch (sel) { case 0: @@ -9022,7 +9026,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, in= t reg, int sel) case CP0_REG31__KSCRATCH6: CP0_CHECK(ctx->kscrexist & (1 << sel)); tcg_gen_ld_tl(arg, cpu_env, - offsetof(CPUMIPSState, CP0_KScratch[sel-2])); + offsetof(CPUMIPSState, CP0_KScratch[sel - 2])); register_name =3D "KScratch"; break; default: @@ -9112,12 +9116,14 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, = int reg, int sel) break; case CP0_REG01__VPESCHEDULE: CP0_CHECK(ctx->insn_flags & ASE_MT); - tcg_gen_st_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_VPESche= dule)); + tcg_gen_st_tl(arg, cpu_env, + offsetof(CPUMIPSState, CP0_VPESchedule)); register_name =3D "VPESchedule"; break; case CP0_REG01__VPESCHEFBACK: CP0_CHECK(ctx->insn_flags & ASE_MT); - tcg_gen_st_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_VPESche= FBack)); + tcg_gen_st_tl(arg, cpu_env, + offsetof(CPUMIPSState, CP0_VPEScheFBack)); register_name =3D "VPEScheFBack"; break; case CP0_REG01__VPEOPT: --=20 2.7.4 From nobody Sat May 4 18:23:24 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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Tue, 01 Oct 2019 11:17:01 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id E09891A22D8; Tue, 1 Oct 2019 17:15:54 +0200 (CEST) Received: from rtrkw774-lin.domain.local (rtrkw774-lin.domain.local [10.10.13.55]) by mail.rt-rk.com (Postfix) with ESMTPSA id 7D5621A239A; Tue, 1 Oct 2019 17:15:54 +0200 (CEST) X-Virus-Scanned: amavisd-new at rt-rk.com From: Aleksandar Markovic To: qemu-devel@nongnu.org Subject: [PULL 05/18] target/mips: msa: Split helpers for . Date: Tue, 1 Oct 2019 17:15:31 +0200 Message-Id: <1569942944-10381-6-git-send-email-aleksandar.markovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1569942944-10381-1-git-send-email-aleksandar.markovic@rt-rk.com> References: <1569942944-10381-1-git-send-email-aleksandar.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 89.216.37.149 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, amarkovic@wavecomp.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Aleksandar Markovic Achieves clearer code and slightly better performance. Signed-off-by: Aleksandar Markovic Reviewed-by: Aleksandar Rikalo Message-Id: <1569415572-19635-8-git-send-email-aleksandar.markovic@rt-rk.co= m> --- target/mips/helper.h | 14 +++- target/mips/msa_helper.c | 170 +++++++++++++++++++++++++++++++++++++++----= ---- target/mips/translate.c | 30 ++++++++- 3 files changed, 181 insertions(+), 33 deletions(-) diff --git a/target/mips/helper.h b/target/mips/helper.h index 51f0e1c..d709083 100644 --- a/target/mips/helper.h +++ b/target/mips/helper.h @@ -777,6 +777,18 @@ DEF_HELPER_FLAGS_3(wrdsp, 0, void, tl, tl, env) DEF_HELPER_FLAGS_2(rddsp, 0, tl, tl, env) =20 /* MIPS SIMD Architecture */ + +DEF_HELPER_3(msa_nloc_b, void, env, i32, i32) +DEF_HELPER_3(msa_nloc_h, void, env, i32, i32) +DEF_HELPER_3(msa_nloc_w, void, env, i32, i32) +DEF_HELPER_3(msa_nloc_d, void, env, i32, i32) + +DEF_HELPER_3(msa_nlzc_b, void, env, i32, i32) +DEF_HELPER_3(msa_nlzc_h, void, env, i32, i32) +DEF_HELPER_3(msa_nlzc_w, void, env, i32, i32) +DEF_HELPER_3(msa_nlzc_d, void, env, i32, i32) + + DEF_HELPER_4(msa_andi_b, void, env, i32, i32, i32) DEF_HELPER_4(msa_ori_b, void, env, i32, i32, i32) DEF_HELPER_4(msa_nori_b, void, env, i32, i32, i32) @@ -935,8 +947,6 @@ DEF_HELPER_4(msa_bmz_v, void, env, i32, i32, i32) DEF_HELPER_4(msa_bsel_v, void, env, i32, i32, i32) DEF_HELPER_4(msa_fill_df, void, env, i32, i32, i32) DEF_HELPER_4(msa_pcnt_df, void, env, i32, i32, i32) -DEF_HELPER_4(msa_nloc_df, void, env, i32, i32, i32) -DEF_HELPER_4(msa_nlzc_df, void, env, i32, i32, i32) =20 DEF_HELPER_4(msa_copy_s_b, void, env, i32, i32, i32) DEF_HELPER_4(msa_copy_s_h, void, env, i32, i32, i32) diff --git a/target/mips/msa_helper.c b/target/mips/msa_helper.c index f24061e..8c27c1b 100644 --- a/target/mips/msa_helper.c +++ b/target/mips/msa_helper.c @@ -65,7 +65,147 @@ * +---------------+------------------------------------------------------= ----+ */ =20 -/* TODO: insert Bit Count group helpers here */ +static inline int64_t msa_nlzc_df(uint32_t df, int64_t arg) +{ + uint64_t x, y; + int n, c; + + x =3D UNSIGNED(arg, df); + n =3D DF_BITS(df); + c =3D DF_BITS(df) / 2; + + do { + y =3D x >> c; + if (y !=3D 0) { + n =3D n - c; + x =3D y; + } + c =3D c >> 1; + } while (c !=3D 0); + + return n - x; +} + +static inline int64_t msa_nloc_df(uint32_t df, int64_t arg) +{ + return msa_nlzc_df(df, UNSIGNED((~arg), df)); +} + +void helper_msa_nloc_b(CPUMIPSState *env, uint32_t wd, uint32_t ws) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + + pwd->b[0] =3D msa_nloc_df(DF_BYTE, pws->b[0]); + pwd->b[1] =3D msa_nloc_df(DF_BYTE, pws->b[1]); + pwd->b[2] =3D msa_nloc_df(DF_BYTE, pws->b[2]); + pwd->b[3] =3D msa_nloc_df(DF_BYTE, pws->b[3]); + pwd->b[4] =3D msa_nloc_df(DF_BYTE, pws->b[4]); + pwd->b[5] =3D msa_nloc_df(DF_BYTE, pws->b[5]); + pwd->b[6] =3D msa_nloc_df(DF_BYTE, pws->b[6]); + pwd->b[7] =3D msa_nloc_df(DF_BYTE, pws->b[7]); + pwd->b[8] =3D msa_nloc_df(DF_BYTE, pws->b[8]); + pwd->b[9] =3D msa_nloc_df(DF_BYTE, pws->b[9]); + pwd->b[10] =3D msa_nloc_df(DF_BYTE, pws->b[10]); + pwd->b[11] =3D msa_nloc_df(DF_BYTE, pws->b[11]); + pwd->b[12] =3D msa_nloc_df(DF_BYTE, pws->b[12]); + pwd->b[13] =3D msa_nloc_df(DF_BYTE, pws->b[13]); + pwd->b[14] =3D msa_nloc_df(DF_BYTE, pws->b[14]); + pwd->b[15] =3D msa_nloc_df(DF_BYTE, pws->b[15]); +} + +void helper_msa_nloc_h(CPUMIPSState *env, uint32_t wd, uint32_t ws) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + + pwd->h[0] =3D msa_nloc_df(DF_HALF, pws->h[0]); + pwd->h[1] =3D msa_nloc_df(DF_HALF, pws->h[1]); + pwd->h[2] =3D msa_nloc_df(DF_HALF, pws->h[2]); + pwd->h[3] =3D msa_nloc_df(DF_HALF, pws->h[3]); + pwd->h[4] =3D msa_nloc_df(DF_HALF, pws->h[4]); + pwd->h[5] =3D msa_nloc_df(DF_HALF, pws->h[5]); + pwd->h[6] =3D msa_nloc_df(DF_HALF, pws->h[6]); + pwd->h[7] =3D msa_nloc_df(DF_HALF, pws->h[7]); +} + +void helper_msa_nloc_w(CPUMIPSState *env, uint32_t wd, uint32_t ws) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + + pwd->w[0] =3D msa_nloc_df(DF_WORD, pws->w[0]); + pwd->w[1] =3D msa_nloc_df(DF_WORD, pws->w[1]); + pwd->w[2] =3D msa_nloc_df(DF_WORD, pws->w[2]); + pwd->w[3] =3D msa_nloc_df(DF_WORD, pws->w[3]); +} + +void helper_msa_nloc_d(CPUMIPSState *env, uint32_t wd, uint32_t ws) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + + pwd->d[0] =3D msa_nloc_df(DF_DOUBLE, pws->d[0]); + pwd->d[1] =3D msa_nloc_df(DF_DOUBLE, pws->d[1]); +} + +void helper_msa_nlzc_b(CPUMIPSState *env, uint32_t wd, uint32_t ws) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + + pwd->b[0] =3D msa_nlzc_df(DF_BYTE, pws->b[0]); + pwd->b[1] =3D msa_nlzc_df(DF_BYTE, pws->b[1]); + pwd->b[2] =3D msa_nlzc_df(DF_BYTE, pws->b[2]); + pwd->b[3] =3D msa_nlzc_df(DF_BYTE, pws->b[3]); + pwd->b[4] =3D msa_nlzc_df(DF_BYTE, pws->b[4]); + pwd->b[5] =3D msa_nlzc_df(DF_BYTE, pws->b[5]); + pwd->b[6] =3D msa_nlzc_df(DF_BYTE, pws->b[6]); + pwd->b[7] =3D msa_nlzc_df(DF_BYTE, pws->b[7]); + pwd->b[8] =3D msa_nlzc_df(DF_BYTE, pws->b[8]); + pwd->b[9] =3D msa_nlzc_df(DF_BYTE, pws->b[9]); + pwd->b[10] =3D msa_nlzc_df(DF_BYTE, pws->b[10]); + pwd->b[11] =3D msa_nlzc_df(DF_BYTE, pws->b[11]); + pwd->b[12] =3D msa_nlzc_df(DF_BYTE, pws->b[12]); + pwd->b[13] =3D msa_nlzc_df(DF_BYTE, pws->b[13]); + pwd->b[14] =3D msa_nlzc_df(DF_BYTE, pws->b[14]); + pwd->b[15] =3D msa_nlzc_df(DF_BYTE, pws->b[15]); +} + +void helper_msa_nlzc_h(CPUMIPSState *env, uint32_t wd, uint32_t ws) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + + pwd->h[0] =3D msa_nlzc_df(DF_HALF, pws->h[0]); + pwd->h[1] =3D msa_nlzc_df(DF_HALF, pws->h[1]); + pwd->h[2] =3D msa_nlzc_df(DF_HALF, pws->h[2]); + pwd->h[3] =3D msa_nlzc_df(DF_HALF, pws->h[3]); + pwd->h[4] =3D msa_nlzc_df(DF_HALF, pws->h[4]); + pwd->h[5] =3D msa_nlzc_df(DF_HALF, pws->h[5]); + pwd->h[6] =3D msa_nlzc_df(DF_HALF, pws->h[6]); + pwd->h[7] =3D msa_nlzc_df(DF_HALF, pws->h[7]); +} + +void helper_msa_nlzc_w(CPUMIPSState *env, uint32_t wd, uint32_t ws) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + + pwd->w[0] =3D msa_nlzc_df(DF_WORD, pws->w[0]); + pwd->w[1] =3D msa_nlzc_df(DF_WORD, pws->w[1]); + pwd->w[2] =3D msa_nlzc_df(DF_WORD, pws->w[2]); + pwd->w[3] =3D msa_nlzc_df(DF_WORD, pws->w[3]); +} + +void helper_msa_nlzc_d(CPUMIPSState *env, uint32_t wd, uint32_t ws) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + + pwd->d[0] =3D msa_nlzc_df(DF_DOUBLE, pws->d[0]); + pwd->d[1] =3D msa_nlzc_df(DF_DOUBLE, pws->d[1]); +} =20 =20 /* @@ -2524,32 +2664,6 @@ static inline int64_t msa_pcnt_df(uint32_t df, int64= _t arg) return x; } =20 -static inline int64_t msa_nlzc_df(uint32_t df, int64_t arg) -{ - uint64_t x, y; - int n, c; - - x =3D UNSIGNED(arg, df); - n =3D DF_BITS(df); - c =3D DF_BITS(df) / 2; - - do { - y =3D x >> c; - if (y !=3D 0) { - n =3D n - c; - x =3D y; - } - c =3D c >> 1; - } while (c !=3D 0); - - return n - x; -} - -static inline int64_t msa_nloc_df(uint32_t df, int64_t arg) -{ - return msa_nlzc_df(df, UNSIGNED((~arg), df)); -} - void helper_msa_fill_df(CPUMIPSState *env, uint32_t df, uint32_t wd, uint32_t rs) { @@ -2633,8 +2747,6 @@ void helper_msa_ ## func ## _df(CPUMIPSState *env, ui= nt32_t df, \ } \ } =20 -MSA_UNOP_DF(nlzc) -MSA_UNOP_DF(nloc) MSA_UNOP_DF(pcnt) #undef MSA_UNOP_DF =20 diff --git a/target/mips/translate.c b/target/mips/translate.c index cc5af2a..6de4609 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -28962,10 +28962,36 @@ static void gen_msa_2r(CPUMIPSState *env, DisasCo= ntext *ctx) gen_helper_msa_pcnt_df(cpu_env, tdf, twd, tws); break; case OPC_NLOC_df: - gen_helper_msa_nloc_df(cpu_env, tdf, twd, tws); + switch (df) { + case DF_BYTE: + gen_helper_msa_nloc_b(cpu_env, twd, tws); + break; + case DF_HALF: + gen_helper_msa_nloc_h(cpu_env, twd, tws); + break; + case DF_WORD: + gen_helper_msa_nloc_w(cpu_env, twd, tws); + break; + case DF_DOUBLE: + gen_helper_msa_nloc_d(cpu_env, twd, tws); + break; + } break; case OPC_NLZC_df: - gen_helper_msa_nlzc_df(cpu_env, tdf, twd, tws); + switch (df) { + case DF_BYTE: + gen_helper_msa_nlzc_b(cpu_env, twd, tws); + break; + case DF_HALF: + gen_helper_msa_nlzc_h(cpu_env, twd, tws); + break; + case DF_WORD: + gen_helper_msa_nlzc_w(cpu_env, twd, tws); + break; + case DF_DOUBLE: + gen_helper_msa_nlzc_d(cpu_env, twd, tws); + break; + } break; default: MIPS_INVAL("MSA instruction"); --=20 2.7.4 From nobody Sat May 4 18:23:24 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1569943497; cv=none; d=zoho.com; s=zohoarc; b=Xeiu07V6NSSTkejoa/jYUjLgLorx7BSubWRA9KBuhkfwptL2+U9g7Nc/qP4E0GSP8E59530ioAoFEFeq7gwL+s7Ks3r5nW5P++bWKa6wI1GnaF0yf3aj17fDn9/Vo8AqpEiNTAWYGc8rFF0HQAZ5QK235XICEphkcubI7hJeEYQ= ARC-Message-Signature: i=1; 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Tue, 01 Oct 2019 11:17:06 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iFJte-0001uO-0K for qemu-devel@nongnu.org; Tue, 01 Oct 2019 11:17:04 -0400 Received: from mx2.rt-rk.com ([89.216.37.149]:59920 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1iFJtd-0001si-Jh for qemu-devel@nongnu.org; Tue, 01 Oct 2019 11:17:01 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id EDBF11A23BC; Tue, 1 Oct 2019 17:15:54 +0200 (CEST) Received: from rtrkw774-lin.domain.local (rtrkw774-lin.domain.local [10.10.13.55]) by mail.rt-rk.com (Postfix) with ESMTPSA id 83D6A1A239D; Tue, 1 Oct 2019 17:15:54 +0200 (CEST) X-Virus-Scanned: amavisd-new at rt-rk.com From: Aleksandar Markovic To: qemu-devel@nongnu.org Subject: [PULL 06/18] target/mips: msa: Split helpers for PCNT. Date: Tue, 1 Oct 2019 17:15:32 +0200 Message-Id: <1569942944-10381-7-git-send-email-aleksandar.markovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1569942944-10381-1-git-send-email-aleksandar.markovic@rt-rk.com> References: <1569942944-10381-1-git-send-email-aleksandar.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 89.216.37.149 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, amarkovic@wavecomp.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Aleksandar Markovic Achieves clearer code and slightly better performance. Signed-off-by: Aleksandar Markovic Reviewed-by: Aleksandar Rikalo Message-Id: <1569415572-19635-9-git-send-email-aleksandar.markovic@rt-rk.co= m> --- target/mips/helper.h | 6 +- target/mips/msa_helper.c | 143 ++++++++++++++++++++++++-------------------= ---- target/mips/translate.c | 19 ++++++- 3 files changed, 95 insertions(+), 73 deletions(-) diff --git a/target/mips/helper.h b/target/mips/helper.h index d709083..18e4c7a 100644 --- a/target/mips/helper.h +++ b/target/mips/helper.h @@ -788,6 +788,11 @@ DEF_HELPER_3(msa_nlzc_h, void, env, i32, i32) DEF_HELPER_3(msa_nlzc_w, void, env, i32, i32) DEF_HELPER_3(msa_nlzc_d, void, env, i32, i32) =20 +DEF_HELPER_3(msa_pcnt_b, void, env, i32, i32) +DEF_HELPER_3(msa_pcnt_h, void, env, i32, i32) +DEF_HELPER_3(msa_pcnt_w, void, env, i32, i32) +DEF_HELPER_3(msa_pcnt_d, void, env, i32, i32) + =20 DEF_HELPER_4(msa_andi_b, void, env, i32, i32, i32) DEF_HELPER_4(msa_ori_b, void, env, i32, i32, i32) @@ -946,7 +951,6 @@ DEF_HELPER_4(msa_bmnz_v, void, env, i32, i32, i32) DEF_HELPER_4(msa_bmz_v, void, env, i32, i32, i32) DEF_HELPER_4(msa_bsel_v, void, env, i32, i32, i32) DEF_HELPER_4(msa_fill_df, void, env, i32, i32, i32) -DEF_HELPER_4(msa_pcnt_df, void, env, i32, i32, i32) =20 DEF_HELPER_4(msa_copy_s_b, void, env, i32, i32, i32) DEF_HELPER_4(msa_copy_s_h, void, env, i32, i32, i32) diff --git a/target/mips/msa_helper.c b/target/mips/msa_helper.c index 8c27c1b..fe27efc 100644 --- a/target/mips/msa_helper.c +++ b/target/mips/msa_helper.c @@ -207,6 +207,80 @@ void helper_msa_nlzc_d(CPUMIPSState *env, uint32_t wd,= uint32_t ws) pwd->d[1] =3D msa_nlzc_df(DF_DOUBLE, pws->d[1]); } =20 +static inline int64_t msa_pcnt_df(uint32_t df, int64_t arg) +{ + uint64_t x; + + x =3D UNSIGNED(arg, df); + + x =3D (x & 0x5555555555555555ULL) + ((x >> 1) & 0x5555555555555555ULL= ); + x =3D (x & 0x3333333333333333ULL) + ((x >> 2) & 0x3333333333333333ULL= ); + x =3D (x & 0x0F0F0F0F0F0F0F0FULL) + ((x >> 4) & 0x0F0F0F0F0F0F0F0FULL= ); + x =3D (x & 0x00FF00FF00FF00FFULL) + ((x >> 8) & 0x00FF00FF00FF00FFULL= ); + x =3D (x & 0x0000FFFF0000FFFFULL) + ((x >> 16) & 0x0000FFFF0000FFFFULL= ); + x =3D (x & 0x00000000FFFFFFFFULL) + ((x >> 32)); + + return x; +} + +void helper_msa_pcnt_b(CPUMIPSState *env, uint32_t wd, uint32_t ws) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + + pwd->b[0] =3D msa_pcnt_df(DF_BYTE, pws->b[0]); + pwd->b[1] =3D msa_pcnt_df(DF_BYTE, pws->b[1]); + pwd->b[2] =3D msa_pcnt_df(DF_BYTE, pws->b[2]); + pwd->b[3] =3D msa_pcnt_df(DF_BYTE, pws->b[3]); + pwd->b[4] =3D msa_pcnt_df(DF_BYTE, pws->b[4]); + pwd->b[5] =3D msa_pcnt_df(DF_BYTE, pws->b[5]); + pwd->b[6] =3D msa_pcnt_df(DF_BYTE, pws->b[6]); + pwd->b[7] =3D msa_pcnt_df(DF_BYTE, pws->b[7]); + pwd->b[8] =3D msa_pcnt_df(DF_BYTE, pws->b[8]); + pwd->b[9] =3D msa_pcnt_df(DF_BYTE, pws->b[9]); + pwd->b[10] =3D msa_pcnt_df(DF_BYTE, pws->b[10]); + pwd->b[11] =3D msa_pcnt_df(DF_BYTE, pws->b[11]); + pwd->b[12] =3D msa_pcnt_df(DF_BYTE, pws->b[12]); + pwd->b[13] =3D msa_pcnt_df(DF_BYTE, pws->b[13]); + pwd->b[14] =3D msa_pcnt_df(DF_BYTE, pws->b[14]); + pwd->b[15] =3D msa_pcnt_df(DF_BYTE, pws->b[15]); +} + +void helper_msa_pcnt_h(CPUMIPSState *env, uint32_t wd, uint32_t ws) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + + pwd->h[0] =3D msa_pcnt_df(DF_HALF, pws->h[0]); + pwd->h[1] =3D msa_pcnt_df(DF_HALF, pws->h[1]); + pwd->h[2] =3D msa_pcnt_df(DF_HALF, pws->h[2]); + pwd->h[3] =3D msa_pcnt_df(DF_HALF, pws->h[3]); + pwd->h[4] =3D msa_pcnt_df(DF_HALF, pws->h[4]); + pwd->h[5] =3D msa_pcnt_df(DF_HALF, pws->h[5]); + pwd->h[6] =3D msa_pcnt_df(DF_HALF, pws->h[6]); + pwd->h[7] =3D msa_pcnt_df(DF_HALF, pws->h[7]); +} + +void helper_msa_pcnt_w(CPUMIPSState *env, uint32_t wd, uint32_t ws) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + + pwd->w[0] =3D msa_pcnt_df(DF_WORD, pws->w[0]); + pwd->w[1] =3D msa_pcnt_df(DF_WORD, pws->w[1]); + pwd->w[2] =3D msa_pcnt_df(DF_WORD, pws->w[2]); + pwd->w[3] =3D msa_pcnt_df(DF_WORD, pws->w[3]); +} + +void helper_msa_pcnt_d(CPUMIPSState *env, uint32_t wd, uint32_t ws) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + + pwd->d[0] =3D msa_pcnt_df(DF_DOUBLE, pws->d[0]); + pwd->d[1] =3D msa_pcnt_df(DF_DOUBLE, pws->d[1]); +} + =20 /* * Bit Move @@ -2648,22 +2722,6 @@ void helper_msa_move_v(CPUMIPSState *env, uint32_t w= d, uint32_t ws) msa_move_v(pwd, pws); } =20 -static inline int64_t msa_pcnt_df(uint32_t df, int64_t arg) -{ - uint64_t x; - - x =3D UNSIGNED(arg, df); - - x =3D (x & 0x5555555555555555ULL) + ((x >> 1) & 0x5555555555555555ULL= ); - x =3D (x & 0x3333333333333333ULL) + ((x >> 2) & 0x3333333333333333ULL= ); - x =3D (x & 0x0F0F0F0F0F0F0F0FULL) + ((x >> 4) & 0x0F0F0F0F0F0F0F0FULL= ); - x =3D (x & 0x00FF00FF00FF00FFULL) + ((x >> 8) & 0x00FF00FF00FF00FFULL= ); - x =3D (x & 0x0000FFFF0000FFFFULL) + ((x >> 16) & 0x0000FFFF0000FFFFULL= ); - x =3D (x & 0x00000000FFFFFFFFULL) + ((x >> 32)); - - return x; -} - void helper_msa_fill_df(CPUMIPSState *env, uint32_t df, uint32_t wd, uint32_t rs) { @@ -2696,59 +2754,6 @@ void helper_msa_fill_df(CPUMIPSState *env, uint32_t = df, uint32_t wd, } } =20 -#define MSA_UNOP_DF(func) \ -void helper_msa_ ## func ## _df(CPUMIPSState *env, uint32_t df, \ - uint32_t wd, uint32_t ws) \ -{ \ - wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); \ - wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); \ - \ - switch (df) { \ - case DF_BYTE: \ - pwd->b[0] =3D msa_ ## func ## _df(df, pws->b[0]); \ - pwd->b[1] =3D msa_ ## func ## _df(df, pws->b[1]); \ - pwd->b[2] =3D msa_ ## func ## _df(df, pws->b[2]); \ - pwd->b[3] =3D msa_ ## func ## _df(df, pws->b[3]); \ - pwd->b[4] =3D msa_ ## func ## _df(df, pws->b[4]); \ - pwd->b[5] =3D msa_ ## func ## _df(df, pws->b[5]); \ - pwd->b[6] =3D msa_ ## func ## _df(df, pws->b[6]); \ - pwd->b[7] =3D msa_ ## func ## _df(df, pws->b[7]); \ - pwd->b[8] =3D msa_ ## func ## _df(df, pws->b[8]); \ - pwd->b[9] =3D msa_ ## func ## _df(df, pws->b[9]); \ - pwd->b[10] =3D msa_ ## func ## _df(df, pws->b[10]); \ - pwd->b[11] =3D msa_ ## func ## _df(df, pws->b[11]); \ - pwd->b[12] =3D msa_ ## func ## _df(df, pws->b[12]); \ - pwd->b[13] =3D msa_ ## func ## _df(df, pws->b[13]); \ - pwd->b[14] =3D msa_ ## func ## _df(df, pws->b[14]); \ - pwd->b[15] =3D msa_ ## func ## _df(df, pws->b[15]); \ - break; \ - case DF_HALF: \ - pwd->h[0] =3D msa_ ## func ## _df(df, pws->h[0]); \ - pwd->h[1] =3D msa_ ## func ## _df(df, pws->h[1]); \ - pwd->h[2] =3D msa_ ## func ## _df(df, pws->h[2]); \ - pwd->h[3] =3D msa_ ## func ## _df(df, pws->h[3]); \ - pwd->h[4] =3D msa_ ## func ## _df(df, pws->h[4]); \ - pwd->h[5] =3D msa_ ## func ## _df(df, pws->h[5]); \ - pwd->h[6] =3D msa_ ## func ## _df(df, pws->h[6]); \ - pwd->h[7] =3D msa_ ## func ## _df(df, pws->h[7]); \ - break; \ - case DF_WORD: \ - pwd->w[0] =3D msa_ ## func ## _df(df, pws->w[0]); \ - pwd->w[1] =3D msa_ ## func ## _df(df, pws->w[1]); \ - pwd->w[2] =3D msa_ ## func ## _df(df, pws->w[2]); \ - pwd->w[3] =3D msa_ ## func ## _df(df, pws->w[3]); \ - break; \ - case DF_DOUBLE: \ - pwd->d[0] =3D msa_ ## func ## _df(df, pws->d[0]); \ - pwd->d[1] =3D msa_ ## func ## _df(df, pws->d[1]); \ - break; \ - default: \ - assert(0); \ - } \ -} - -MSA_UNOP_DF(pcnt) -#undef MSA_UNOP_DF =20 #define FLOAT_ONE32 make_float32(0x3f8 << 20) #define FLOAT_ONE64 make_float64(0x3ffULL << 52) diff --git a/target/mips/translate.c b/target/mips/translate.c index 6de4609..0d06ba9 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -28958,9 +28958,6 @@ static void gen_msa_2r(CPUMIPSState *env, DisasCont= ext *ctx) #endif gen_helper_msa_fill_df(cpu_env, tdf, twd, tws); /* trs */ break; - case OPC_PCNT_df: - gen_helper_msa_pcnt_df(cpu_env, tdf, twd, tws); - break; case OPC_NLOC_df: switch (df) { case DF_BYTE: @@ -28993,6 +28990,22 @@ static void gen_msa_2r(CPUMIPSState *env, DisasCon= text *ctx) break; } break; + case OPC_PCNT_df: + switch (df) { + case DF_BYTE: + gen_helper_msa_pcnt_b(cpu_env, twd, tws); + break; + case DF_HALF: + gen_helper_msa_pcnt_h(cpu_env, twd, tws); + break; + case DF_WORD: + gen_helper_msa_pcnt_w(cpu_env, twd, tws); + break; + case DF_DOUBLE: + gen_helper_msa_pcnt_d(cpu_env, twd, tws); + break; + } + break; default: MIPS_INVAL("MSA instruction"); generate_exception_end(ctx, EXCP_RI); --=20 2.7.4 From nobody Sat May 4 18:23:24 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; 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Tue, 1 Oct 2019 17:15:54 +0200 (CEST) X-Virus-Scanned: amavisd-new at rt-rk.com From: Aleksandar Markovic To: qemu-devel@nongnu.org Subject: [PULL 07/18] target/mips: msa: Split helpers for BINS. Date: Tue, 1 Oct 2019 17:15:33 +0200 Message-Id: <1569942944-10381-8-git-send-email-aleksandar.markovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1569942944-10381-1-git-send-email-aleksandar.markovic@rt-rk.com> References: <1569942944-10381-1-git-send-email-aleksandar.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 89.216.37.149 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, amarkovic@wavecomp.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Aleksandar Markovic Achieves clearer code and slightly better performance. Signed-off-by: Aleksandar Markovic Reviewed-by: Aleksandar Rikalo Message-Id: <1569415572-19635-10-git-send-email-aleksandar.markovic@rt-rk.c= om> --- target/mips/helper.h | 10 +++ target/mips/msa_helper.c | 198 +++++++++++++++++++++++++++++++++++++++----= ---- target/mips/translate.c | 38 +++++++-- 3 files changed, 206 insertions(+), 40 deletions(-) diff --git a/target/mips/helper.h b/target/mips/helper.h index 18e4c7a..9349482 100644 --- a/target/mips/helper.h +++ b/target/mips/helper.h @@ -793,6 +793,16 @@ DEF_HELPER_3(msa_pcnt_h, void, env, i32, i32) DEF_HELPER_3(msa_pcnt_w, void, env, i32, i32) DEF_HELPER_3(msa_pcnt_d, void, env, i32, i32) =20 +DEF_HELPER_4(msa_binsl_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_binsl_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_binsl_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_binsl_d, void, env, i32, i32, i32) + +DEF_HELPER_4(msa_binsr_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_binsr_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_binsr_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_binsr_d, void, env, i32, i32, i32) + =20 DEF_HELPER_4(msa_andi_b, void, env, i32, i32, i32) DEF_HELPER_4(msa_ori_b, void, env, i32, i32, i32) diff --git a/target/mips/msa_helper.c b/target/mips/msa_helper.c index fe27efc..c9b0583 100644 --- a/target/mips/msa_helper.c +++ b/target/mips/msa_helper.c @@ -301,7 +301,170 @@ void helper_msa_pcnt_d(CPUMIPSState *env, uint32_t wd= , uint32_t ws) * +---------------+------------------------------------------------------= ----+ */ =20 -/* TODO: insert Bit Move group helpers here */ +/* Data format bit position and unsigned values */ +#define BIT_POSITION(x, df) ((uint64_t)(x) % DF_BITS(df)) + +static inline int64_t msa_binsl_df(uint32_t df, + int64_t dest, int64_t arg1, int64_t arg= 2) +{ + uint64_t u_arg1 =3D UNSIGNED(arg1, df); + uint64_t u_dest =3D UNSIGNED(dest, df); + int32_t sh_d =3D BIT_POSITION(arg2, df) + 1; + int32_t sh_a =3D DF_BITS(df) - sh_d; + if (sh_d =3D=3D DF_BITS(df)) { + return u_arg1; + } else { + return UNSIGNED(UNSIGNED(u_dest << sh_d, df) >> sh_d, df) | + UNSIGNED(UNSIGNED(u_arg1 >> sh_a, df) << sh_a, df); + } +} + +void helper_msa_binsl_b(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); + + pwd->b[0] =3D msa_binsl_df(DF_BYTE, pwd->b[0], pws->b[0], pwt->b[0]= ); + pwd->b[1] =3D msa_binsl_df(DF_BYTE, pwd->b[1], pws->b[1], pwt->b[1]= ); + pwd->b[2] =3D msa_binsl_df(DF_BYTE, pwd->b[2], pws->b[2], pwt->b[2]= ); + pwd->b[3] =3D msa_binsl_df(DF_BYTE, pwd->b[3], pws->b[3], pwt->b[3]= ); + pwd->b[4] =3D msa_binsl_df(DF_BYTE, pwd->b[4], pws->b[4], pwt->b[4]= ); + pwd->b[5] =3D msa_binsl_df(DF_BYTE, pwd->b[5], pws->b[5], pwt->b[5]= ); + pwd->b[6] =3D msa_binsl_df(DF_BYTE, pwd->b[6], pws->b[6], pwt->b[6]= ); + pwd->b[7] =3D msa_binsl_df(DF_BYTE, pwd->b[7], pws->b[7], pwt->b[7]= ); + pwd->b[8] =3D msa_binsl_df(DF_BYTE, pwd->b[8], pws->b[8], pwt->b[8]= ); + pwd->b[9] =3D msa_binsl_df(DF_BYTE, pwd->b[9], pws->b[9], pwt->b[9]= ); + pwd->b[10] =3D msa_binsl_df(DF_BYTE, pwd->b[10], pws->b[10], pwt->b[10= ]); + pwd->b[11] =3D msa_binsl_df(DF_BYTE, pwd->b[11], pws->b[11], pwt->b[11= ]); + pwd->b[12] =3D msa_binsl_df(DF_BYTE, pwd->b[12], pws->b[12], pwt->b[12= ]); + pwd->b[13] =3D msa_binsl_df(DF_BYTE, pwd->b[13], pws->b[13], pwt->b[13= ]); + pwd->b[14] =3D msa_binsl_df(DF_BYTE, pwd->b[14], pws->b[14], pwt->b[14= ]); + pwd->b[15] =3D msa_binsl_df(DF_BYTE, pwd->b[15], pws->b[15], pwt->b[15= ]); +} + +void helper_msa_binsl_h(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); + + pwd->h[0] =3D msa_binsl_df(DF_HALF, pwd->h[0], pws->h[0], pwt->h[0]= ); + pwd->h[1] =3D msa_binsl_df(DF_HALF, pwd->h[1], pws->h[1], pwt->h[1]= ); + pwd->h[2] =3D msa_binsl_df(DF_HALF, pwd->h[2], pws->h[2], pwt->h[2]= ); + pwd->h[3] =3D msa_binsl_df(DF_HALF, pwd->h[3], pws->h[3], pwt->h[3]= ); + pwd->h[4] =3D msa_binsl_df(DF_HALF, pwd->h[4], pws->h[4], pwt->h[4]= ); + pwd->h[5] =3D msa_binsl_df(DF_HALF, pwd->h[5], pws->h[5], pwt->h[5]= ); + pwd->h[6] =3D msa_binsl_df(DF_HALF, pwd->h[6], pws->h[6], pwt->h[6]= ); + pwd->h[7] =3D msa_binsl_df(DF_HALF, pwd->h[7], pws->h[7], pwt->h[7]= ); +} + +void helper_msa_binsl_w(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); + + pwd->w[0] =3D msa_binsl_df(DF_WORD, pwd->w[0], pws->w[0], pwt->w[0]= ); + pwd->w[1] =3D msa_binsl_df(DF_WORD, pwd->w[1], pws->w[1], pwt->w[1]= ); + pwd->w[2] =3D msa_binsl_df(DF_WORD, pwd->w[2], pws->w[2], pwt->w[2]= ); + pwd->w[3] =3D msa_binsl_df(DF_WORD, pwd->w[3], pws->w[3], pwt->w[3]= ); +} + +void helper_msa_binsl_d(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); + + pwd->d[0] =3D msa_binsl_df(DF_DOUBLE, pwd->d[0], pws->d[0], pwt->d[= 0]); + pwd->d[1] =3D msa_binsl_df(DF_DOUBLE, pwd->d[1], pws->d[1], pwt->d[= 1]); +} + +static inline int64_t msa_binsr_df(uint32_t df, + int64_t dest, int64_t arg1, int64_t arg= 2) +{ + uint64_t u_arg1 =3D UNSIGNED(arg1, df); + uint64_t u_dest =3D UNSIGNED(dest, df); + int32_t sh_d =3D BIT_POSITION(arg2, df) + 1; + int32_t sh_a =3D DF_BITS(df) - sh_d; + if (sh_d =3D=3D DF_BITS(df)) { + return u_arg1; + } else { + return UNSIGNED(UNSIGNED(u_dest >> sh_d, df) << sh_d, df) | + UNSIGNED(UNSIGNED(u_arg1 << sh_a, df) >> sh_a, df); + } +} + +void helper_msa_binsr_b(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); + + pwd->b[0] =3D msa_binsr_df(DF_BYTE, pwd->b[0], pws->b[0], pwt->b[0]= ); + pwd->b[1] =3D msa_binsr_df(DF_BYTE, pwd->b[1], pws->b[1], pwt->b[1]= ); + pwd->b[2] =3D msa_binsr_df(DF_BYTE, pwd->b[2], pws->b[2], pwt->b[2]= ); + pwd->b[3] =3D msa_binsr_df(DF_BYTE, pwd->b[3], pws->b[3], pwt->b[3]= ); + pwd->b[4] =3D msa_binsr_df(DF_BYTE, pwd->b[4], pws->b[4], pwt->b[4]= ); + pwd->b[5] =3D msa_binsr_df(DF_BYTE, pwd->b[5], pws->b[5], pwt->b[5]= ); + pwd->b[6] =3D msa_binsr_df(DF_BYTE, pwd->b[6], pws->b[6], pwt->b[6]= ); + pwd->b[7] =3D msa_binsr_df(DF_BYTE, pwd->b[7], pws->b[7], pwt->b[7]= ); + pwd->b[8] =3D msa_binsr_df(DF_BYTE, pwd->b[8], pws->b[8], pwt->b[8]= ); + pwd->b[9] =3D msa_binsr_df(DF_BYTE, pwd->b[9], pws->b[9], pwt->b[9]= ); + pwd->b[10] =3D msa_binsr_df(DF_BYTE, pwd->b[10], pws->b[10], pwt->b[10= ]); + pwd->b[11] =3D msa_binsr_df(DF_BYTE, pwd->b[11], pws->b[11], pwt->b[11= ]); + pwd->b[12] =3D msa_binsr_df(DF_BYTE, pwd->b[12], pws->b[12], pwt->b[12= ]); + pwd->b[13] =3D msa_binsr_df(DF_BYTE, pwd->b[13], pws->b[13], pwt->b[13= ]); + pwd->b[14] =3D msa_binsr_df(DF_BYTE, pwd->b[14], pws->b[14], pwt->b[14= ]); + pwd->b[15] =3D msa_binsr_df(DF_BYTE, pwd->b[15], pws->b[15], pwt->b[15= ]); +} + +void helper_msa_binsr_h(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); + + pwd->h[0] =3D msa_binsr_df(DF_HALF, pwd->h[0], pws->h[0], pwt->h[0]= ); + pwd->h[1] =3D msa_binsr_df(DF_HALF, pwd->h[1], pws->h[1], pwt->h[1]= ); + pwd->h[2] =3D msa_binsr_df(DF_HALF, pwd->h[2], pws->h[2], pwt->h[2]= ); + pwd->h[3] =3D msa_binsr_df(DF_HALF, pwd->h[3], pws->h[3], pwt->h[3]= ); + pwd->h[4] =3D msa_binsr_df(DF_HALF, pwd->h[4], pws->h[4], pwt->h[4]= ); + pwd->h[5] =3D msa_binsr_df(DF_HALF, pwd->h[5], pws->h[5], pwt->h[5]= ); + pwd->h[6] =3D msa_binsr_df(DF_HALF, pwd->h[6], pws->h[6], pwt->h[6]= ); + pwd->h[7] =3D msa_binsr_df(DF_HALF, pwd->h[7], pws->h[7], pwt->h[7]= ); +} + +void helper_msa_binsr_w(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); + + pwd->w[0] =3D msa_binsr_df(DF_WORD, pwd->w[0], pws->w[0], pwt->w[0]= ); + pwd->w[1] =3D msa_binsr_df(DF_WORD, pwd->w[1], pws->w[1], pwt->w[1]= ); + pwd->w[2] =3D msa_binsr_df(DF_WORD, pwd->w[2], pws->w[2], pwt->w[2]= ); + pwd->w[3] =3D msa_binsr_df(DF_WORD, pwd->w[3], pws->w[3], pwt->w[3]= ); +} + +void helper_msa_binsr_d(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); + + pwd->d[0] =3D msa_binsr_df(DF_DOUBLE, pwd->d[0], pws->d[0], pwt->d[= 0]); + pwd->d[1] =3D msa_binsr_df(DF_DOUBLE, pwd->d[1], pws->d[1], pwt->d[= 1]); +} =20 =20 /* @@ -1023,9 +1186,6 @@ void helper_msa_ldi_df(CPUMIPSState *env, uint32_t df= , uint32_t wd, } } =20 -/* Data format bit position and unsigned values */ -#define BIT_POSITION(x, df) ((uint64_t)(x) % DF_BITS(df)) - static inline int64_t msa_sll_df(uint32_t df, int64_t arg1, int64_t arg2) { int32_t b_arg2 =3D BIT_POSITION(arg2, df); @@ -1064,36 +1224,6 @@ static inline int64_t msa_bneg_df(uint32_t df, int64= _t arg1, int64_t arg2) return UNSIGNED(arg1 ^ (1LL << b_arg2), df); } =20 -static inline int64_t msa_binsl_df(uint32_t df, int64_t dest, int64_t arg1, - int64_t arg2) -{ - uint64_t u_arg1 =3D UNSIGNED(arg1, df); - uint64_t u_dest =3D UNSIGNED(dest, df); - int32_t sh_d =3D BIT_POSITION(arg2, df) + 1; - int32_t sh_a =3D DF_BITS(df) - sh_d; - if (sh_d =3D=3D DF_BITS(df)) { - return u_arg1; - } else { - return UNSIGNED(UNSIGNED(u_dest << sh_d, df) >> sh_d, df) | - UNSIGNED(UNSIGNED(u_arg1 >> sh_a, df) << sh_a, df); - } -} - -static inline int64_t msa_binsr_df(uint32_t df, int64_t dest, int64_t arg1, - int64_t arg2) -{ - uint64_t u_arg1 =3D UNSIGNED(arg1, df); - uint64_t u_dest =3D UNSIGNED(dest, df); - int32_t sh_d =3D BIT_POSITION(arg2, df) + 1; - int32_t sh_a =3D DF_BITS(df) - sh_d; - if (sh_d =3D=3D DF_BITS(df)) { - return u_arg1; - } else { - return UNSIGNED(UNSIGNED(u_dest >> sh_d, df) << sh_d, df) | - UNSIGNED(UNSIGNED(u_arg1 << sh_a, df) >> sh_a, df); - } -} - static inline int64_t msa_sat_s_df(uint32_t df, int64_t arg, uint32_t m) { return arg < M_MIN_INT(m + 1) ? M_MIN_INT(m + 1) : diff --git a/target/mips/translate.c b/target/mips/translate.c index 0d06ba9..6080c72 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -28386,6 +28386,38 @@ static void gen_msa_3r(CPUMIPSState *env, DisasCon= text *ctx) TCGv_i32 twt =3D tcg_const_i32(wt); =20 switch (MASK_MSA_3R(ctx->opcode)) { + case OPC_BINSL_df: + switch (df) { + case DF_BYTE: + gen_helper_msa_binsl_b(cpu_env, twd, tws, twt); + break; + case DF_HALF: + gen_helper_msa_binsl_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_binsl_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_binsl_d(cpu_env, twd, tws, twt); + break; + } + break; + case OPC_BINSR_df: + switch (df) { + case DF_BYTE: + gen_helper_msa_binsr_b(cpu_env, twd, tws, twt); + break; + case DF_HALF: + gen_helper_msa_binsr_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_binsr_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_binsr_d(cpu_env, twd, tws, twt); + break; + } + break; case OPC_SLL_df: gen_helper_msa_sll_df(cpu_env, tdf, twd, tws, twt); break; @@ -28515,9 +28547,6 @@ static void gen_msa_3r(CPUMIPSState *env, DisasCont= ext *ctx) case OPC_ILVR_df: gen_helper_msa_ilvr_df(cpu_env, tdf, twd, tws, twt); break; - case OPC_BINSL_df: - gen_helper_msa_binsl_df(cpu_env, tdf, twd, tws, twt); - break; case OPC_MAX_A_df: gen_helper_msa_max_a_df(cpu_env, tdf, twd, tws, twt); break; @@ -28530,9 +28559,6 @@ static void gen_msa_3r(CPUMIPSState *env, DisasCont= ext *ctx) case OPC_ILVEV_df: gen_helper_msa_ilvev_df(cpu_env, tdf, twd, tws, twt); break; - case OPC_BINSR_df: - gen_helper_msa_binsr_df(cpu_env, tdf, twd, tws, twt); - break; case OPC_MIN_A_df: gen_helper_msa_min_a_df(cpu_env, tdf, twd, tws, twt); break; --=20 2.7.4 From nobody Sat May 4 18:23:24 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Tue, 1 Oct 2019 17:15:54 +0200 (CEST) X-Virus-Scanned: amavisd-new at rt-rk.com From: Aleksandar Markovic To: qemu-devel@nongnu.org Subject: [PULL 08/18] target/mips: msa: Unroll loops and demacro .V Date: Tue, 1 Oct 2019 17:15:34 +0200 Message-Id: <1569942944-10381-9-git-send-email-aleksandar.markovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1569942944-10381-1-git-send-email-aleksandar.markovic@rt-rk.com> References: <1569942944-10381-1-git-send-email-aleksandar.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 89.216.37.149 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, amarkovic@wavecomp.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Aleksandar Markovic Achieves clearer code and slightly better performance. Signed-off-by: Aleksandar Markovic Reviewed-by: Aleksandar Rikalo Message-Id: <1569415572-19635-11-git-send-email-aleksandar.markovic@rt-rk.c= om> --- target/mips/helper.h | 7 +++--- target/mips/msa_helper.c | 63 ++++++++++++++++++++++++++++++--------------= ---- 2 files changed, 43 insertions(+), 27 deletions(-) diff --git a/target/mips/helper.h b/target/mips/helper.h index 9349482..27544a1 100644 --- a/target/mips/helper.h +++ b/target/mips/helper.h @@ -803,6 +803,10 @@ DEF_HELPER_4(msa_binsr_h, void, env, i32, i32, i32) DEF_HELPER_4(msa_binsr_w, void, env, i32, i32, i32) DEF_HELPER_4(msa_binsr_d, void, env, i32, i32, i32) =20 +DEF_HELPER_4(msa_bmnz_v, void, env, i32, i32, i32) +DEF_HELPER_4(msa_bmz_v, void, env, i32, i32, i32) +DEF_HELPER_4(msa_bsel_v, void, env, i32, i32, i32) + =20 DEF_HELPER_4(msa_andi_b, void, env, i32, i32, i32) DEF_HELPER_4(msa_ori_b, void, env, i32, i32, i32) @@ -957,9 +961,6 @@ DEF_HELPER_4(msa_and_v, void, env, i32, i32, i32) DEF_HELPER_4(msa_or_v, void, env, i32, i32, i32) DEF_HELPER_4(msa_nor_v, void, env, i32, i32, i32) DEF_HELPER_4(msa_xor_v, void, env, i32, i32, i32) -DEF_HELPER_4(msa_bmnz_v, void, env, i32, i32, i32) -DEF_HELPER_4(msa_bmz_v, void, env, i32, i32, i32) -DEF_HELPER_4(msa_bsel_v, void, env, i32, i32, i32) DEF_HELPER_4(msa_fill_df, void, env, i32, i32, i32) =20 DEF_HELPER_4(msa_copy_s_b, void, env, i32, i32, i32) diff --git a/target/mips/msa_helper.c b/target/mips/msa_helper.c index c9b0583..82c8871 100644 --- a/target/mips/msa_helper.c +++ b/target/mips/msa_helper.c @@ -466,6 +466,42 @@ void helper_msa_binsr_d(CPUMIPSState *env, pwd->d[1] =3D msa_binsr_df(DF_DOUBLE, pwd->d[1], pws->d[1], pwt->d[= 1]); } =20 +void helper_msa_bmnz_v(CPUMIPSState *env, uint32_t wd, uint32_t ws, uint32= _t wt) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); + + pwd->d[0] =3D UNSIGNED( = \ + ((pwd->d[0] & (~pwt->d[0])) | (pws->d[0] & pwt->d[0])), DF_DOUBLE); + pwd->d[1] =3D UNSIGNED( = \ + ((pwd->d[1] & (~pwt->d[1])) | (pws->d[1] & pwt->d[1])), DF_DOUBLE); +} + +void helper_msa_bmz_v(CPUMIPSState *env, uint32_t wd, uint32_t ws, uint32_= t wt) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); + + pwd->d[0] =3D UNSIGNED( = \ + ((pwd->d[0] & pwt->d[0]) | (pws->d[0] & (~pwt->d[0]))), DF_DOUBLE); + pwd->d[1] =3D UNSIGNED( = \ + ((pwd->d[1] & pwt->d[1]) | (pws->d[1] & (~pwt->d[1]))), DF_DOUBLE); +} + +void helper_msa_bsel_v(CPUMIPSState *env, uint32_t wd, uint32_t ws, uint32= _t wt) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); + + pwd->d[0] =3D UNSIGNED( = \ + (pws->d[0] & (~pwd->d[0])) | (pwt->d[0] & pwd->d[0]), DF_DOUBLE); + pwd->d[1] =3D UNSIGNED( = \ + (pws->d[1] & (~pwd->d[1])) | (pwt->d[1] & pwd->d[1]), DF_DOUBLE); +} + =20 /* * Bit Set @@ -946,6 +982,9 @@ MSA_FN_IMM8(bmzi_b, pwd->b[i], MSA_FN_IMM8(bseli_b, pwd->b[i], BIT_SELECT(pwd->b[i], pws->b[i], i8, DF_BYTE)) =20 +#undef BIT_SELECT +#undef BIT_MOVE_IF_ZERO +#undef BIT_MOVE_IF_NOT_ZERO #undef MSA_FN_IMM8 =20 #define SHF_POS(i, imm) (((i) & 0xfc) + (((imm) >> (2 * ((i) & 0x03))) & 0= x03)) @@ -980,30 +1019,6 @@ void helper_msa_shf_df(CPUMIPSState *env, uint32_t df= , uint32_t wd, msa_move_v(pwd, pwx); } =20 -#define MSA_FN_VECTOR(FUNC, DEST, OPERATION) \ -void helper_msa_ ## FUNC(CPUMIPSState *env, uint32_t wd, uint32_t ws, \ - uint32_t wt) \ -{ \ - wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); \ - wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); \ - wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); \ - uint32_t i; \ - for (i =3D 0; i < DF_ELEMENTS(DF_DOUBLE); i++) { \ - DEST =3D OPERATION; \ - } \ -} - -MSA_FN_VECTOR(bmnz_v, pwd->d[i], - BIT_MOVE_IF_NOT_ZERO(pwd->d[i], pws->d[i], pwt->d[i], DF_DOUBLE)) -MSA_FN_VECTOR(bmz_v, pwd->d[i], - BIT_MOVE_IF_ZERO(pwd->d[i], pws->d[i], pwt->d[i], DF_DOUBLE)) -MSA_FN_VECTOR(bsel_v, pwd->d[i], - BIT_SELECT(pwd->d[i], pws->d[i], pwt->d[i], DF_DOUBLE)) -#undef BIT_MOVE_IF_NOT_ZERO -#undef BIT_MOVE_IF_ZERO -#undef BIT_SELECT -#undef MSA_FN_VECTOR - void helper_msa_and_v(CPUMIPSState *env, uint32_t wd, uint32_t ws, uint32_= t wt) { wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); --=20 2.7.4 From nobody Sat May 4 18:23:24 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; 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Tue, 1 Oct 2019 17:15:54 +0200 (CEST) X-Virus-Scanned: amavisd-new at rt-rk.com From: Aleksandar Markovic To: qemu-devel@nongnu.org Subject: [PULL 09/18] target/mips: msa: Split helpers for B. Date: Tue, 1 Oct 2019 17:15:35 +0200 Message-Id: <1569942944-10381-10-git-send-email-aleksandar.markovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1569942944-10381-1-git-send-email-aleksandar.markovic@rt-rk.com> References: <1569942944-10381-1-git-send-email-aleksandar.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 89.216.37.149 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, amarkovic@wavecomp.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Aleksandar Markovic Achieves clearer code and slightly better performance. Signed-off-by: Aleksandar Markovic Reviewed-by: Aleksandar Rikalo Message-Id: <1569415572-19635-12-git-send-email-aleksandar.markovic@rt-rk.c= om> --- target/mips/helper.h | 18 +++- target/mips/msa_helper.c | 227 ++++++++++++++++++++++++++++++++++++++++++-= ---- target/mips/translate.c | 57 ++++++++++-- 3 files changed, 267 insertions(+), 35 deletions(-) diff --git a/target/mips/helper.h b/target/mips/helper.h index 27544a1..1411e0e 100644 --- a/target/mips/helper.h +++ b/target/mips/helper.h @@ -807,6 +807,21 @@ DEF_HELPER_4(msa_bmnz_v, void, env, i32, i32, i32) DEF_HELPER_4(msa_bmz_v, void, env, i32, i32, i32) DEF_HELPER_4(msa_bsel_v, void, env, i32, i32, i32) =20 +DEF_HELPER_4(msa_bclr_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_bclr_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_bclr_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_bclr_d, void, env, i32, i32, i32) + +DEF_HELPER_4(msa_bneg_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_bneg_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_bneg_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_bneg_d, void, env, i32, i32, i32) + +DEF_HELPER_4(msa_bset_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_bset_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_bset_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_bset_d, void, env, i32, i32, i32) + =20 DEF_HELPER_4(msa_andi_b, void, env, i32, i32, i32) DEF_HELPER_4(msa_ori_b, void, env, i32, i32, i32) @@ -846,9 +861,6 @@ DEF_HELPER_5(msa_srlri_df, void, env, i32, i32, i32, i3= 2) DEF_HELPER_5(msa_sll_df, void, env, i32, i32, i32, i32) DEF_HELPER_5(msa_sra_df, void, env, i32, i32, i32, i32) DEF_HELPER_5(msa_srl_df, void, env, i32, i32, i32, i32) -DEF_HELPER_5(msa_bclr_df, void, env, i32, i32, i32, i32) -DEF_HELPER_5(msa_bset_df, void, env, i32, i32, i32, i32) -DEF_HELPER_5(msa_bneg_df, void, env, i32, i32, i32, i32) DEF_HELPER_5(msa_binsl_df, void, env, i32, i32, i32, i32) DEF_HELPER_5(msa_binsr_df, void, env, i32, i32, i32, i32) DEF_HELPER_5(msa_addv_df, void, env, i32, i32, i32, i32) diff --git a/target/mips/msa_helper.c b/target/mips/msa_helper.c index 82c8871..5177e41 100644 --- a/target/mips/msa_helper.c +++ b/target/mips/msa_helper.c @@ -523,7 +523,210 @@ void helper_msa_bsel_v(CPUMIPSState *env, uint32_t wd= , uint32_t ws, uint32_t wt) * +---------------+------------------------------------------------------= ----+ */ =20 -/* TODO: insert Bit Set group helpers here */ +static inline int64_t msa_bclr_df(uint32_t df, int64_t arg1, int64_t arg2) +{ + int32_t b_arg2 =3D BIT_POSITION(arg2, df); + return UNSIGNED(arg1 & (~(1LL << b_arg2)), df); +} + +void helper_msa_bclr_b(CPUMIPSState *env, uint32_t wd, uint32_t ws, uint32= _t wt) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); + + pwd->b[0] =3D msa_bclr_df(DF_BYTE, pws->b[0], pwt->b[0]); + pwd->b[1] =3D msa_bclr_df(DF_BYTE, pws->b[1], pwt->b[1]); + pwd->b[2] =3D msa_bclr_df(DF_BYTE, pws->b[2], pwt->b[2]); + pwd->b[3] =3D msa_bclr_df(DF_BYTE, pws->b[3], pwt->b[3]); + pwd->b[4] =3D msa_bclr_df(DF_BYTE, pws->b[4], pwt->b[4]); + pwd->b[5] =3D msa_bclr_df(DF_BYTE, pws->b[5], pwt->b[5]); + pwd->b[6] =3D msa_bclr_df(DF_BYTE, pws->b[6], pwt->b[6]); + pwd->b[7] =3D msa_bclr_df(DF_BYTE, pws->b[7], pwt->b[7]); + pwd->b[8] =3D msa_bclr_df(DF_BYTE, pws->b[8], pwt->b[8]); + pwd->b[9] =3D msa_bclr_df(DF_BYTE, pws->b[9], pwt->b[9]); + pwd->b[10] =3D msa_bclr_df(DF_BYTE, pws->b[10], pwt->b[10]); + pwd->b[11] =3D msa_bclr_df(DF_BYTE, pws->b[11], pwt->b[11]); + pwd->b[12] =3D msa_bclr_df(DF_BYTE, pws->b[12], pwt->b[12]); + pwd->b[13] =3D msa_bclr_df(DF_BYTE, pws->b[13], pwt->b[13]); + pwd->b[14] =3D msa_bclr_df(DF_BYTE, pws->b[14], pwt->b[14]); + pwd->b[15] =3D msa_bclr_df(DF_BYTE, pws->b[15], pwt->b[15]); +} + +void helper_msa_bclr_h(CPUMIPSState *env, uint32_t wd, uint32_t ws, uint32= _t wt) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); + + pwd->h[0] =3D msa_bclr_df(DF_HALF, pws->h[0], pwt->h[0]); + pwd->h[1] =3D msa_bclr_df(DF_HALF, pws->h[1], pwt->h[1]); + pwd->h[2] =3D msa_bclr_df(DF_HALF, pws->h[2], pwt->h[2]); + pwd->h[3] =3D msa_bclr_df(DF_HALF, pws->h[3], pwt->h[3]); + pwd->h[4] =3D msa_bclr_df(DF_HALF, pws->h[4], pwt->h[4]); + pwd->h[5] =3D msa_bclr_df(DF_HALF, pws->h[5], pwt->h[5]); + pwd->h[6] =3D msa_bclr_df(DF_HALF, pws->h[6], pwt->h[6]); + pwd->h[7] =3D msa_bclr_df(DF_HALF, pws->h[7], pwt->h[7]); +} + +void helper_msa_bclr_w(CPUMIPSState *env, uint32_t wd, uint32_t ws, uint32= _t wt) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); + + pwd->w[0] =3D msa_bclr_df(DF_WORD, pws->w[0], pwt->w[0]); + pwd->w[1] =3D msa_bclr_df(DF_WORD, pws->w[1], pwt->w[1]); + pwd->w[2] =3D msa_bclr_df(DF_WORD, pws->w[2], pwt->w[2]); + pwd->w[3] =3D msa_bclr_df(DF_WORD, pws->w[3], pwt->w[3]); +} + +void helper_msa_bclr_d(CPUMIPSState *env, uint32_t wd, uint32_t ws, uint32= _t wt) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); + + pwd->d[0] =3D msa_bclr_df(DF_DOUBLE, pws->d[0], pwt->d[0]); + pwd->d[1] =3D msa_bclr_df(DF_DOUBLE, pws->d[1], pwt->d[1]); +} + +static inline int64_t msa_bneg_df(uint32_t df, int64_t arg1, int64_t arg2) +{ + int32_t b_arg2 =3D BIT_POSITION(arg2, df); + return UNSIGNED(arg1 ^ (1LL << b_arg2), df); +} + +void helper_msa_bneg_b(CPUMIPSState *env, uint32_t wd, uint32_t ws, uint32= _t wt) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); + + pwd->b[0] =3D msa_bneg_df(DF_BYTE, pws->b[0], pwt->b[0]); + pwd->b[1] =3D msa_bneg_df(DF_BYTE, pws->b[1], pwt->b[1]); + pwd->b[2] =3D msa_bneg_df(DF_BYTE, pws->b[2], pwt->b[2]); + pwd->b[3] =3D msa_bneg_df(DF_BYTE, pws->b[3], pwt->b[3]); + pwd->b[4] =3D msa_bneg_df(DF_BYTE, pws->b[4], pwt->b[4]); + pwd->b[5] =3D msa_bneg_df(DF_BYTE, pws->b[5], pwt->b[5]); + pwd->b[6] =3D msa_bneg_df(DF_BYTE, pws->b[6], pwt->b[6]); + pwd->b[7] =3D msa_bneg_df(DF_BYTE, pws->b[7], pwt->b[7]); + pwd->b[8] =3D msa_bneg_df(DF_BYTE, pws->b[8], pwt->b[8]); + pwd->b[9] =3D msa_bneg_df(DF_BYTE, pws->b[9], pwt->b[9]); + pwd->b[10] =3D msa_bneg_df(DF_BYTE, pws->b[10], pwt->b[10]); + pwd->b[11] =3D msa_bneg_df(DF_BYTE, pws->b[11], pwt->b[11]); + pwd->b[12] =3D msa_bneg_df(DF_BYTE, pws->b[12], pwt->b[12]); + pwd->b[13] =3D msa_bneg_df(DF_BYTE, pws->b[13], pwt->b[13]); + pwd->b[14] =3D msa_bneg_df(DF_BYTE, pws->b[14], pwt->b[14]); + pwd->b[15] =3D msa_bneg_df(DF_BYTE, pws->b[15], pwt->b[15]); +} + +void helper_msa_bneg_h(CPUMIPSState *env, uint32_t wd, uint32_t ws, uint32= _t wt) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); + + pwd->h[0] =3D msa_bneg_df(DF_HALF, pws->h[0], pwt->h[0]); + pwd->h[1] =3D msa_bneg_df(DF_HALF, pws->h[1], pwt->h[1]); + pwd->h[2] =3D msa_bneg_df(DF_HALF, pws->h[2], pwt->h[2]); + pwd->h[3] =3D msa_bneg_df(DF_HALF, pws->h[3], pwt->h[3]); + pwd->h[4] =3D msa_bneg_df(DF_HALF, pws->h[4], pwt->h[4]); + pwd->h[5] =3D msa_bneg_df(DF_HALF, pws->h[5], pwt->h[5]); + pwd->h[6] =3D msa_bneg_df(DF_HALF, pws->h[6], pwt->h[6]); + pwd->h[7] =3D msa_bneg_df(DF_HALF, pws->h[7], pwt->h[7]); +} + +void helper_msa_bneg_w(CPUMIPSState *env, uint32_t wd, uint32_t ws, uint32= _t wt) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); + + pwd->w[0] =3D msa_bneg_df(DF_WORD, pws->w[0], pwt->w[0]); + pwd->w[1] =3D msa_bneg_df(DF_WORD, pws->w[1], pwt->w[1]); + pwd->w[2] =3D msa_bneg_df(DF_WORD, pws->w[2], pwt->w[2]); + pwd->w[3] =3D msa_bneg_df(DF_WORD, pws->w[3], pwt->w[3]); +} + +void helper_msa_bneg_d(CPUMIPSState *env, uint32_t wd, uint32_t ws, uint32= _t wt) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); + + pwd->d[0] =3D msa_bneg_df(DF_DOUBLE, pws->d[0], pwt->d[0]); + pwd->d[1] =3D msa_bneg_df(DF_DOUBLE, pws->d[1], pwt->d[1]); +} + +static inline int64_t msa_bset_df(uint32_t df, int64_t arg1, + int64_t arg2) +{ + int32_t b_arg2 =3D BIT_POSITION(arg2, df); + return UNSIGNED(arg1 | (1LL << b_arg2), df); +} + +void helper_msa_bset_b(CPUMIPSState *env, uint32_t wd, uint32_t ws, uint32= _t wt) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); + + pwd->b[0] =3D msa_bset_df(DF_BYTE, pws->b[0], pwt->b[0]); + pwd->b[1] =3D msa_bset_df(DF_BYTE, pws->b[1], pwt->b[1]); + pwd->b[2] =3D msa_bset_df(DF_BYTE, pws->b[2], pwt->b[2]); + pwd->b[3] =3D msa_bset_df(DF_BYTE, pws->b[3], pwt->b[3]); + pwd->b[4] =3D msa_bset_df(DF_BYTE, pws->b[4], pwt->b[4]); + pwd->b[5] =3D msa_bset_df(DF_BYTE, pws->b[5], pwt->b[5]); + pwd->b[6] =3D msa_bset_df(DF_BYTE, pws->b[6], pwt->b[6]); + pwd->b[7] =3D msa_bset_df(DF_BYTE, pws->b[7], pwt->b[7]); + pwd->b[8] =3D msa_bset_df(DF_BYTE, pws->b[8], pwt->b[8]); + pwd->b[9] =3D msa_bset_df(DF_BYTE, pws->b[9], pwt->b[9]); + pwd->b[10] =3D msa_bset_df(DF_BYTE, pws->b[10], pwt->b[10]); + pwd->b[11] =3D msa_bset_df(DF_BYTE, pws->b[11], pwt->b[11]); + pwd->b[12] =3D msa_bset_df(DF_BYTE, pws->b[12], pwt->b[12]); + pwd->b[13] =3D msa_bset_df(DF_BYTE, pws->b[13], pwt->b[13]); + pwd->b[14] =3D msa_bset_df(DF_BYTE, pws->b[14], pwt->b[14]); + pwd->b[15] =3D msa_bset_df(DF_BYTE, pws->b[15], pwt->b[15]); +} + +void helper_msa_bset_h(CPUMIPSState *env, uint32_t wd, uint32_t ws, uint32= _t wt) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); + + pwd->h[0] =3D msa_bset_df(DF_HALF, pws->h[0], pwt->h[0]); + pwd->h[1] =3D msa_bset_df(DF_HALF, pws->h[1], pwt->h[1]); + pwd->h[2] =3D msa_bset_df(DF_HALF, pws->h[2], pwt->h[2]); + pwd->h[3] =3D msa_bset_df(DF_HALF, pws->h[3], pwt->h[3]); + pwd->h[4] =3D msa_bset_df(DF_HALF, pws->h[4], pwt->h[4]); + pwd->h[5] =3D msa_bset_df(DF_HALF, pws->h[5], pwt->h[5]); + pwd->h[6] =3D msa_bset_df(DF_HALF, pws->h[6], pwt->h[6]); + pwd->h[7] =3D msa_bset_df(DF_HALF, pws->h[7], pwt->h[7]); +} + +void helper_msa_bset_w(CPUMIPSState *env, uint32_t wd, uint32_t ws, uint32= _t wt) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); + + pwd->w[0] =3D msa_bset_df(DF_WORD, pws->w[0], pwt->w[0]); + pwd->w[1] =3D msa_bset_df(DF_WORD, pws->w[1], pwt->w[1]); + pwd->w[2] =3D msa_bset_df(DF_WORD, pws->w[2], pwt->w[2]); + pwd->w[3] =3D msa_bset_df(DF_WORD, pws->w[3], pwt->w[3]); +} + +void helper_msa_bset_d(CPUMIPSState *env, uint32_t wd, uint32_t ws, uint32= _t wt) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); + + pwd->d[0] =3D msa_bset_df(DF_DOUBLE, pws->d[0], pwt->d[0]); + pwd->d[1] =3D msa_bset_df(DF_DOUBLE, pws->d[1], pwt->d[1]); +} =20 =20 /* @@ -1220,25 +1423,6 @@ static inline int64_t msa_srl_df(uint32_t df, int64_= t arg1, int64_t arg2) return u_arg1 >> b_arg2; } =20 -static inline int64_t msa_bclr_df(uint32_t df, int64_t arg1, int64_t arg2) -{ - int32_t b_arg2 =3D BIT_POSITION(arg2, df); - return UNSIGNED(arg1 & (~(1LL << b_arg2)), df); -} - -static inline int64_t msa_bset_df(uint32_t df, int64_t arg1, - int64_t arg2) -{ - int32_t b_arg2 =3D BIT_POSITION(arg2, df); - return UNSIGNED(arg1 | (1LL << b_arg2), df); -} - -static inline int64_t msa_bneg_df(uint32_t df, int64_t arg1, int64_t arg2) -{ - int32_t b_arg2 =3D BIT_POSITION(arg2, df); - return UNSIGNED(arg1 ^ (1LL << b_arg2), df); -} - static inline int64_t msa_sat_s_df(uint32_t df, int64_t arg, uint32_t m) { return arg < M_MIN_INT(m + 1) ? M_MIN_INT(m + 1) : @@ -1734,9 +1918,6 @@ void helper_msa_ ## func ## _df(CPUMIPSState *env, ui= nt32_t df, \ MSA_BINOP_DF(sll) MSA_BINOP_DF(sra) MSA_BINOP_DF(srl) -MSA_BINOP_DF(bclr) -MSA_BINOP_DF(bset) -MSA_BINOP_DF(bneg) MSA_BINOP_DF(addv) MSA_BINOP_DF(subv) MSA_BINOP_DF(max_s) diff --git a/target/mips/translate.c b/target/mips/translate.c index 6080c72..1a87f79 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -28418,6 +28418,54 @@ static void gen_msa_3r(CPUMIPSState *env, DisasCon= text *ctx) break; } break; + case OPC_BCLR_df: + switch (df) { + case DF_BYTE: + gen_helper_msa_bclr_b(cpu_env, twd, tws, twt); + break; + case DF_HALF: + gen_helper_msa_bclr_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_bclr_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_bclr_d(cpu_env, twd, tws, twt); + break; + } + break; + case OPC_BNEG_df: + switch (df) { + case DF_BYTE: + gen_helper_msa_bneg_b(cpu_env, twd, tws, twt); + break; + case DF_HALF: + gen_helper_msa_bneg_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_bneg_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_bneg_d(cpu_env, twd, tws, twt); + break; + } + break; + case OPC_BSET_df: + switch (df) { + case DF_BYTE: + gen_helper_msa_bset_b(cpu_env, twd, tws, twt); + break; + case DF_HALF: + gen_helper_msa_bset_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_bset_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_bset_d(cpu_env, twd, tws, twt); + break; + } + break; case OPC_SLL_df: gen_helper_msa_sll_df(cpu_env, tdf, twd, tws, twt); break; @@ -28487,9 +28535,6 @@ static void gen_msa_3r(CPUMIPSState *env, DisasCont= ext *ctx) case OPC_SRLR_df: gen_helper_msa_srlr_df(cpu_env, tdf, twd, tws, twt); break; - case OPC_BCLR_df: - gen_helper_msa_bclr_df(cpu_env, tdf, twd, tws, twt); - break; case OPC_MAX_U_df: gen_helper_msa_max_u_df(cpu_env, tdf, twd, tws, twt); break; @@ -28505,9 +28550,6 @@ static void gen_msa_3r(CPUMIPSState *env, DisasCont= ext *ctx) case OPC_PCKOD_df: gen_helper_msa_pckod_df(cpu_env, tdf, twd, tws, twt); break; - case OPC_BSET_df: - gen_helper_msa_bset_df(cpu_env, tdf, twd, tws, twt); - break; case OPC_MIN_S_df: gen_helper_msa_min_s_df(cpu_env, tdf, twd, tws, twt); break; @@ -28526,9 +28568,6 @@ static void gen_msa_3r(CPUMIPSState *env, DisasCont= ext *ctx) case OPC_ILVL_df: gen_helper_msa_ilvl_df(cpu_env, tdf, twd, tws, twt); break; - case OPC_BNEG_df: - gen_helper_msa_bneg_df(cpu_env, tdf, twd, tws, twt); - break; case OPC_MIN_U_df: gen_helper_msa_min_u_df(cpu_env, tdf, twd, tws, twt); break; --=20 2.7.4 From nobody Sat May 4 18:23:24 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; 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Tue, 1 Oct 2019 17:15:54 +0200 (CEST) X-Virus-Scanned: amavisd-new at rt-rk.com From: Aleksandar Markovic To: qemu-devel@nongnu.org Subject: [PULL 10/18] target/mips: msa: Split helpers for AVE_. Date: Tue, 1 Oct 2019 17:15:36 +0200 Message-Id: <1569942944-10381-11-git-send-email-aleksandar.markovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1569942944-10381-1-git-send-email-aleksandar.markovic@rt-rk.com> References: <1569942944-10381-1-git-send-email-aleksandar.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 89.216.37.149 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, amarkovic@wavecomp.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Aleksandar Markovic Achieves clearer code and slightly better performance. Signed-off-by: Aleksandar Markovic Reviewed-by: Aleksandar Rikalo Message-Id: <1569415572-19635-13-git-send-email-aleksandar.markovic@rt-rk.c= om> --- target/mips/helper.h | 12 +++- target/mips/msa_helper.c | 162 ++++++++++++++++++++++++++++++++++++++++++-= ---- target/mips/translate.c | 38 +++++++++-- 3 files changed, 187 insertions(+), 25 deletions(-) diff --git a/target/mips/helper.h b/target/mips/helper.h index 1411e0e..455dd25 100644 --- a/target/mips/helper.h +++ b/target/mips/helper.h @@ -822,6 +822,16 @@ DEF_HELPER_4(msa_bset_h, void, env, i32, i32, i32) DEF_HELPER_4(msa_bset_w, void, env, i32, i32, i32) DEF_HELPER_4(msa_bset_d, void, env, i32, i32, i32) =20 +DEF_HELPER_4(msa_ave_s_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_ave_s_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_ave_s_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_ave_s_d, void, env, i32, i32, i32) + +DEF_HELPER_4(msa_ave_u_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_ave_u_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_ave_u_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_ave_u_d, void, env, i32, i32, i32) + =20 DEF_HELPER_4(msa_andi_b, void, env, i32, i32, i32) DEF_HELPER_4(msa_ori_b, void, env, i32, i32, i32) @@ -880,8 +890,6 @@ DEF_HELPER_5(msa_add_a_df, void, env, i32, i32, i32, i3= 2) DEF_HELPER_5(msa_adds_a_df, void, env, i32, i32, i32, i32) DEF_HELPER_5(msa_adds_s_df, void, env, i32, i32, i32, i32) DEF_HELPER_5(msa_adds_u_df, void, env, i32, i32, i32, i32) -DEF_HELPER_5(msa_ave_s_df, void, env, i32, i32, i32, i32) -DEF_HELPER_5(msa_ave_u_df, void, env, i32, i32, i32, i32) DEF_HELPER_5(msa_aver_s_df, void, env, i32, i32, i32, i32) DEF_HELPER_5(msa_aver_u_df, void, env, i32, i32, i32, i32) DEF_HELPER_5(msa_subs_s_df, void, env, i32, i32, i32, i32) diff --git a/target/mips/msa_helper.c b/target/mips/msa_helper.c index 5177e41..1a7f90c 100644 --- a/target/mips/msa_helper.c +++ b/target/mips/msa_helper.c @@ -832,7 +832,151 @@ void helper_msa_bset_d(CPUMIPSState *env, uint32_t wd= , uint32_t ws, uint32_t wt) * +---------------+------------------------------------------------------= ----+ */ =20 -/* TODO: insert Int Average group helpers here */ +static inline int64_t msa_ave_s_df(uint32_t df, int64_t arg1, int64_t arg2) +{ + /* signed shift */ + return (arg1 >> 1) + (arg2 >> 1) + (arg1 & arg2 & 1); +} + +void helper_msa_ave_s_b(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); + + pwd->b[0] =3D msa_ave_s_df(DF_BYTE, pws->b[0], pwt->b[0]); + pwd->b[1] =3D msa_ave_s_df(DF_BYTE, pws->b[1], pwt->b[1]); + pwd->b[2] =3D msa_ave_s_df(DF_BYTE, pws->b[2], pwt->b[2]); + pwd->b[3] =3D msa_ave_s_df(DF_BYTE, pws->b[3], pwt->b[3]); + pwd->b[4] =3D msa_ave_s_df(DF_BYTE, pws->b[4], pwt->b[4]); + pwd->b[5] =3D msa_ave_s_df(DF_BYTE, pws->b[5], pwt->b[5]); + pwd->b[6] =3D msa_ave_s_df(DF_BYTE, pws->b[6], pwt->b[6]); + pwd->b[7] =3D msa_ave_s_df(DF_BYTE, pws->b[7], pwt->b[7]); + pwd->b[8] =3D msa_ave_s_df(DF_BYTE, pws->b[8], pwt->b[8]); + pwd->b[9] =3D msa_ave_s_df(DF_BYTE, pws->b[9], pwt->b[9]); + pwd->b[10] =3D msa_ave_s_df(DF_BYTE, pws->b[10], pwt->b[10]); + pwd->b[11] =3D msa_ave_s_df(DF_BYTE, pws->b[11], pwt->b[11]); + pwd->b[12] =3D msa_ave_s_df(DF_BYTE, pws->b[12], pwt->b[12]); + pwd->b[13] =3D msa_ave_s_df(DF_BYTE, pws->b[13], pwt->b[13]); + pwd->b[14] =3D msa_ave_s_df(DF_BYTE, pws->b[14], pwt->b[14]); + pwd->b[15] =3D msa_ave_s_df(DF_BYTE, pws->b[15], pwt->b[15]); +} + +void helper_msa_ave_s_h(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); + + pwd->h[0] =3D msa_ave_s_df(DF_HALF, pws->h[0], pwt->h[0]); + pwd->h[1] =3D msa_ave_s_df(DF_HALF, pws->h[1], pwt->h[1]); + pwd->h[2] =3D msa_ave_s_df(DF_HALF, pws->h[2], pwt->h[2]); + pwd->h[3] =3D msa_ave_s_df(DF_HALF, pws->h[3], pwt->h[3]); + pwd->h[4] =3D msa_ave_s_df(DF_HALF, pws->h[4], pwt->h[4]); + pwd->h[5] =3D msa_ave_s_df(DF_HALF, pws->h[5], pwt->h[5]); + pwd->h[6] =3D msa_ave_s_df(DF_HALF, pws->h[6], pwt->h[6]); + pwd->h[7] =3D msa_ave_s_df(DF_HALF, pws->h[7], pwt->h[7]); +} + +void helper_msa_ave_s_w(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); + + pwd->w[0] =3D msa_ave_s_df(DF_WORD, pws->w[0], pwt->w[0]); + pwd->w[1] =3D msa_ave_s_df(DF_WORD, pws->w[1], pwt->w[1]); + pwd->w[2] =3D msa_ave_s_df(DF_WORD, pws->w[2], pwt->w[2]); + pwd->w[3] =3D msa_ave_s_df(DF_WORD, pws->w[3], pwt->w[3]); +} + +void helper_msa_ave_s_d(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); + + pwd->d[0] =3D msa_ave_s_df(DF_DOUBLE, pws->d[0], pwt->d[0]); + pwd->d[1] =3D msa_ave_s_df(DF_DOUBLE, pws->d[1], pwt->d[1]); +} + +static inline uint64_t msa_ave_u_df(uint32_t df, uint64_t arg1, uint64_t a= rg2) +{ + uint64_t u_arg1 =3D UNSIGNED(arg1, df); + uint64_t u_arg2 =3D UNSIGNED(arg2, df); + /* unsigned shift */ + return (u_arg1 >> 1) + (u_arg2 >> 1) + (u_arg1 & u_arg2 & 1); +} + +void helper_msa_ave_u_b(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); + + pwd->b[0] =3D msa_ave_u_df(DF_BYTE, pws->b[0], pwt->b[0]); + pwd->b[1] =3D msa_ave_u_df(DF_BYTE, pws->b[1], pwt->b[1]); + pwd->b[2] =3D msa_ave_u_df(DF_BYTE, pws->b[2], pwt->b[2]); + pwd->b[3] =3D msa_ave_u_df(DF_BYTE, pws->b[3], pwt->b[3]); + pwd->b[4] =3D msa_ave_u_df(DF_BYTE, pws->b[4], pwt->b[4]); + pwd->b[5] =3D msa_ave_u_df(DF_BYTE, pws->b[5], pwt->b[5]); + pwd->b[6] =3D msa_ave_u_df(DF_BYTE, pws->b[6], pwt->b[6]); + pwd->b[7] =3D msa_ave_u_df(DF_BYTE, pws->b[7], pwt->b[7]); + pwd->b[8] =3D msa_ave_u_df(DF_BYTE, pws->b[8], pwt->b[8]); + pwd->b[9] =3D msa_ave_u_df(DF_BYTE, pws->b[9], pwt->b[9]); + pwd->b[10] =3D msa_ave_u_df(DF_BYTE, pws->b[10], pwt->b[10]); + pwd->b[11] =3D msa_ave_u_df(DF_BYTE, pws->b[11], pwt->b[11]); + pwd->b[12] =3D msa_ave_u_df(DF_BYTE, pws->b[12], pwt->b[12]); + pwd->b[13] =3D msa_ave_u_df(DF_BYTE, pws->b[13], pwt->b[13]); + pwd->b[14] =3D msa_ave_u_df(DF_BYTE, pws->b[14], pwt->b[14]); + pwd->b[15] =3D msa_ave_u_df(DF_BYTE, pws->b[15], pwt->b[15]); +} + +void helper_msa_ave_u_h(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); + + pwd->h[0] =3D msa_ave_u_df(DF_HALF, pws->h[0], pwt->h[0]); + pwd->h[1] =3D msa_ave_u_df(DF_HALF, pws->h[1], pwt->h[1]); + pwd->h[2] =3D msa_ave_u_df(DF_HALF, pws->h[2], pwt->h[2]); + pwd->h[3] =3D msa_ave_u_df(DF_HALF, pws->h[3], pwt->h[3]); + pwd->h[4] =3D msa_ave_u_df(DF_HALF, pws->h[4], pwt->h[4]); + pwd->h[5] =3D msa_ave_u_df(DF_HALF, pws->h[5], pwt->h[5]); + pwd->h[6] =3D msa_ave_u_df(DF_HALF, pws->h[6], pwt->h[6]); + pwd->h[7] =3D msa_ave_u_df(DF_HALF, pws->h[7], pwt->h[7]); +} + +void helper_msa_ave_u_w(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); + + pwd->w[0] =3D msa_ave_u_df(DF_WORD, pws->w[0], pwt->w[0]); + pwd->w[1] =3D msa_ave_u_df(DF_WORD, pws->w[1], pwt->w[1]); + pwd->w[2] =3D msa_ave_u_df(DF_WORD, pws->w[2], pwt->w[2]); + pwd->w[3] =3D msa_ave_u_df(DF_WORD, pws->w[3], pwt->w[3]); +} + +void helper_msa_ave_u_d(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); + + pwd->d[0] =3D msa_ave_u_df(DF_DOUBLE, pws->d[0], pwt->d[0]); + pwd->d[1] =3D msa_ave_u_df(DF_DOUBLE, pws->d[1], pwt->d[1]); +} =20 =20 /* @@ -1600,20 +1744,6 @@ static inline uint64_t msa_adds_u_df(uint32_t df, ui= nt64_t arg1, uint64_t arg2) return (u_arg1 < max_uint - u_arg2) ? u_arg1 + u_arg2 : max_uint; } =20 -static inline int64_t msa_ave_s_df(uint32_t df, int64_t arg1, int64_t arg2) -{ - /* signed shift */ - return (arg1 >> 1) + (arg2 >> 1) + (arg1 & arg2 & 1); -} - -static inline uint64_t msa_ave_u_df(uint32_t df, uint64_t arg1, uint64_t a= rg2) -{ - uint64_t u_arg1 =3D UNSIGNED(arg1, df); - uint64_t u_arg2 =3D UNSIGNED(arg2, df); - /* unsigned shift */ - return (u_arg1 >> 1) + (u_arg2 >> 1) + (u_arg1 & u_arg2 & 1); -} - static inline int64_t msa_aver_s_df(uint32_t df, int64_t arg1, int64_t arg= 2) { /* signed shift */ @@ -1935,8 +2065,6 @@ MSA_BINOP_DF(add_a) MSA_BINOP_DF(adds_a) MSA_BINOP_DF(adds_s) MSA_BINOP_DF(adds_u) -MSA_BINOP_DF(ave_s) -MSA_BINOP_DF(ave_u) MSA_BINOP_DF(aver_s) MSA_BINOP_DF(aver_u) MSA_BINOP_DF(subs_s) diff --git a/target/mips/translate.c b/target/mips/translate.c index 1a87f79..2b0abbb 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -28466,6 +28466,38 @@ static void gen_msa_3r(CPUMIPSState *env, DisasCon= text *ctx) break; } break; + case OPC_AVE_S_df: + switch (df) { + case DF_BYTE: + gen_helper_msa_ave_s_b(cpu_env, twd, tws, twt); + break; + case DF_HALF: + gen_helper_msa_ave_s_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_ave_s_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_ave_s_d(cpu_env, twd, tws, twt); + break; + } + break; + case OPC_AVE_U_df: + switch (df) { + case DF_BYTE: + gen_helper_msa_ave_u_b(cpu_env, twd, tws, twt); + break; + case DF_HALF: + gen_helper_msa_ave_u_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_ave_u_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_ave_u_d(cpu_env, twd, tws, twt); + break; + } + break; case OPC_SLL_df: gen_helper_msa_sll_df(cpu_env, tdf, twd, tws, twt); break; @@ -28556,9 +28588,6 @@ static void gen_msa_3r(CPUMIPSState *env, DisasCont= ext *ctx) case OPC_CLE_S_df: gen_helper_msa_cle_s_df(cpu_env, tdf, twd, tws, twt); break; - case OPC_AVE_S_df: - gen_helper_msa_ave_s_df(cpu_env, tdf, twd, tws, twt); - break; case OPC_ASUB_S_df: gen_helper_msa_asub_s_df(cpu_env, tdf, twd, tws, twt); break; @@ -28574,9 +28603,6 @@ static void gen_msa_3r(CPUMIPSState *env, DisasCont= ext *ctx) case OPC_CLE_U_df: gen_helper_msa_cle_u_df(cpu_env, tdf, twd, tws, twt); break; - case OPC_AVE_U_df: - gen_helper_msa_ave_u_df(cpu_env, tdf, twd, tws, twt); - break; case OPC_ASUB_U_df: gen_helper_msa_asub_u_df(cpu_env, tdf, twd, tws, twt); break; --=20 2.7.4 From nobody Sat May 4 18:23:24 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1569944059; cv=none; d=zoho.com; s=zohoarc; b=U4r2OSsSz+VF71WZvz6q/LXiB6TbXFe+wKN3JuTq+nN5PAAiyXgJhqtH/XznbNc+GdG14cETWsu/hFWraowdcqDCVemYTTRCi3kC9PGD/rcYVA0M5ABaQtjNr2vV2MpqyxPMcSu1lGlYCdOf5QxNBwgrnPdA0HA/dJGjmVYDy84= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1569944059; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; 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Tue, 01 Oct 2019 11:17:06 -0400 Received: from mx2.rt-rk.com ([89.216.37.149]:59941 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1iFJtd-0001tE-Ui for qemu-devel@nongnu.org; Tue, 01 Oct 2019 11:17:02 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id 3EC6B1A23C4; Tue, 1 Oct 2019 17:15:55 +0200 (CEST) Received: from rtrkw774-lin.domain.local (rtrkw774-lin.domain.local [10.10.13.55]) by mail.rt-rk.com (Postfix) with ESMTPSA id AE9431A23AD; Tue, 1 Oct 2019 17:15:54 +0200 (CEST) X-Virus-Scanned: amavisd-new at rt-rk.com From: Aleksandar Markovic To: qemu-devel@nongnu.org Subject: [PULL 11/18] target/mips: msa: Split helpers for AVER_. Date: Tue, 1 Oct 2019 17:15:37 +0200 Message-Id: <1569942944-10381-12-git-send-email-aleksandar.markovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1569942944-10381-1-git-send-email-aleksandar.markovic@rt-rk.com> References: <1569942944-10381-1-git-send-email-aleksandar.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 89.216.37.149 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, amarkovic@wavecomp.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Aleksandar Markovic Achieves clearer code and slightly better performance. Signed-off-by: Aleksandar Markovic Reviewed-by: Aleksandar Rikalo Message-Id: <1569415572-19635-14-git-send-email-aleksandar.markovic@rt-rk.c= om> --- target/mips/helper.h | 12 +++- target/mips/msa_helper.c | 162 ++++++++++++++++++++++++++++++++++++++++++-= ---- target/mips/translate.c | 38 +++++++++-- 3 files changed, 188 insertions(+), 24 deletions(-) diff --git a/target/mips/helper.h b/target/mips/helper.h index 455dd25..9d4c9f1 100644 --- a/target/mips/helper.h +++ b/target/mips/helper.h @@ -832,6 +832,16 @@ DEF_HELPER_4(msa_ave_u_h, void, env, i32, i32, i32) DEF_HELPER_4(msa_ave_u_w, void, env, i32, i32, i32) DEF_HELPER_4(msa_ave_u_d, void, env, i32, i32, i32) =20 +DEF_HELPER_4(msa_aver_s_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_aver_s_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_aver_s_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_aver_s_d, void, env, i32, i32, i32) + +DEF_HELPER_4(msa_aver_u_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_aver_u_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_aver_u_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_aver_u_d, void, env, i32, i32, i32) + =20 DEF_HELPER_4(msa_andi_b, void, env, i32, i32, i32) DEF_HELPER_4(msa_ori_b, void, env, i32, i32, i32) @@ -890,8 +900,6 @@ DEF_HELPER_5(msa_add_a_df, void, env, i32, i32, i32, i3= 2) DEF_HELPER_5(msa_adds_a_df, void, env, i32, i32, i32, i32) DEF_HELPER_5(msa_adds_s_df, void, env, i32, i32, i32, i32) DEF_HELPER_5(msa_adds_u_df, void, env, i32, i32, i32, i32) -DEF_HELPER_5(msa_aver_s_df, void, env, i32, i32, i32, i32) -DEF_HELPER_5(msa_aver_u_df, void, env, i32, i32, i32, i32) DEF_HELPER_5(msa_subs_s_df, void, env, i32, i32, i32, i32) DEF_HELPER_5(msa_subs_u_df, void, env, i32, i32, i32, i32) DEF_HELPER_5(msa_subsus_u_df, void, env, i32, i32, i32, i32) diff --git a/target/mips/msa_helper.c b/target/mips/msa_helper.c index 1a7f90c..17443b9 100644 --- a/target/mips/msa_helper.c +++ b/target/mips/msa_helper.c @@ -978,6 +978,152 @@ void helper_msa_ave_u_d(CPUMIPSState *env, pwd->d[1] =3D msa_ave_u_df(DF_DOUBLE, pws->d[1], pwt->d[1]); } =20 +static inline int64_t msa_aver_s_df(uint32_t df, int64_t arg1, int64_t arg= 2) +{ + /* signed shift */ + return (arg1 >> 1) + (arg2 >> 1) + ((arg1 | arg2) & 1); +} + +void helper_msa_aver_s_b(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); + + pwd->b[0] =3D msa_aver_s_df(DF_BYTE, pws->b[0], pwt->b[0]); + pwd->b[1] =3D msa_aver_s_df(DF_BYTE, pws->b[1], pwt->b[1]); + pwd->b[2] =3D msa_aver_s_df(DF_BYTE, pws->b[2], pwt->b[2]); + pwd->b[3] =3D msa_aver_s_df(DF_BYTE, pws->b[3], pwt->b[3]); + pwd->b[4] =3D msa_aver_s_df(DF_BYTE, pws->b[4], pwt->b[4]); + pwd->b[5] =3D msa_aver_s_df(DF_BYTE, pws->b[5], pwt->b[5]); + pwd->b[6] =3D msa_aver_s_df(DF_BYTE, pws->b[6], pwt->b[6]); + pwd->b[7] =3D msa_aver_s_df(DF_BYTE, pws->b[7], pwt->b[7]); + pwd->b[8] =3D msa_aver_s_df(DF_BYTE, pws->b[8], pwt->b[8]); + pwd->b[9] =3D msa_aver_s_df(DF_BYTE, pws->b[9], pwt->b[9]); + pwd->b[10] =3D msa_aver_s_df(DF_BYTE, pws->b[10], pwt->b[10]); + pwd->b[11] =3D msa_aver_s_df(DF_BYTE, pws->b[11], pwt->b[11]); + pwd->b[12] =3D msa_aver_s_df(DF_BYTE, pws->b[12], pwt->b[12]); + pwd->b[13] =3D msa_aver_s_df(DF_BYTE, pws->b[13], pwt->b[13]); + pwd->b[14] =3D msa_aver_s_df(DF_BYTE, pws->b[14], pwt->b[14]); + pwd->b[15] =3D msa_aver_s_df(DF_BYTE, pws->b[15], pwt->b[15]); +} + +void helper_msa_aver_s_h(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); + + pwd->h[0] =3D msa_aver_s_df(DF_HALF, pws->h[0], pwt->h[0]); + pwd->h[1] =3D msa_aver_s_df(DF_HALF, pws->h[1], pwt->h[1]); + pwd->h[2] =3D msa_aver_s_df(DF_HALF, pws->h[2], pwt->h[2]); + pwd->h[3] =3D msa_aver_s_df(DF_HALF, pws->h[3], pwt->h[3]); + pwd->h[4] =3D msa_aver_s_df(DF_HALF, pws->h[4], pwt->h[4]); + pwd->h[5] =3D msa_aver_s_df(DF_HALF, pws->h[5], pwt->h[5]); + pwd->h[6] =3D msa_aver_s_df(DF_HALF, pws->h[6], pwt->h[6]); + pwd->h[7] =3D msa_aver_s_df(DF_HALF, pws->h[7], pwt->h[7]); +} + +void helper_msa_aver_s_w(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); + + pwd->w[0] =3D msa_aver_s_df(DF_WORD, pws->w[0], pwt->w[0]); + pwd->w[1] =3D msa_aver_s_df(DF_WORD, pws->w[1], pwt->w[1]); + pwd->w[2] =3D msa_aver_s_df(DF_WORD, pws->w[2], pwt->w[2]); + pwd->w[3] =3D msa_aver_s_df(DF_WORD, pws->w[3], pwt->w[3]); +} + +void helper_msa_aver_s_d(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); + + pwd->d[0] =3D msa_aver_s_df(DF_DOUBLE, pws->d[0], pwt->d[0]); + pwd->d[1] =3D msa_aver_s_df(DF_DOUBLE, pws->d[1], pwt->d[1]); +} + +static inline uint64_t msa_aver_u_df(uint32_t df, uint64_t arg1, uint64_t = arg2) +{ + uint64_t u_arg1 =3D UNSIGNED(arg1, df); + uint64_t u_arg2 =3D UNSIGNED(arg2, df); + /* unsigned shift */ + return (u_arg1 >> 1) + (u_arg2 >> 1) + ((u_arg1 | u_arg2) & 1); +} + +void helper_msa_aver_u_b(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); + + pwd->b[0] =3D msa_aver_u_df(DF_BYTE, pws->b[0], pwt->b[0]); + pwd->b[1] =3D msa_aver_u_df(DF_BYTE, pws->b[1], pwt->b[1]); + pwd->b[2] =3D msa_aver_u_df(DF_BYTE, pws->b[2], pwt->b[2]); + pwd->b[3] =3D msa_aver_u_df(DF_BYTE, pws->b[3], pwt->b[3]); + pwd->b[4] =3D msa_aver_u_df(DF_BYTE, pws->b[4], pwt->b[4]); + pwd->b[5] =3D msa_aver_u_df(DF_BYTE, pws->b[5], pwt->b[5]); + pwd->b[6] =3D msa_aver_u_df(DF_BYTE, pws->b[6], pwt->b[6]); + pwd->b[7] =3D msa_aver_u_df(DF_BYTE, pws->b[7], pwt->b[7]); + pwd->b[8] =3D msa_aver_u_df(DF_BYTE, pws->b[8], pwt->b[8]); + pwd->b[9] =3D msa_aver_u_df(DF_BYTE, pws->b[9], pwt->b[9]); + pwd->b[10] =3D msa_aver_u_df(DF_BYTE, pws->b[10], pwt->b[10]); + pwd->b[11] =3D msa_aver_u_df(DF_BYTE, pws->b[11], pwt->b[11]); + pwd->b[12] =3D msa_aver_u_df(DF_BYTE, pws->b[12], pwt->b[12]); + pwd->b[13] =3D msa_aver_u_df(DF_BYTE, pws->b[13], pwt->b[13]); + pwd->b[14] =3D msa_aver_u_df(DF_BYTE, pws->b[14], pwt->b[14]); + pwd->b[15] =3D msa_aver_u_df(DF_BYTE, pws->b[15], pwt->b[15]); +} + +void helper_msa_aver_u_h(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); + + pwd->h[0] =3D msa_aver_u_df(DF_HALF, pws->h[0], pwt->h[0]); + pwd->h[1] =3D msa_aver_u_df(DF_HALF, pws->h[1], pwt->h[1]); + pwd->h[2] =3D msa_aver_u_df(DF_HALF, pws->h[2], pwt->h[2]); + pwd->h[3] =3D msa_aver_u_df(DF_HALF, pws->h[3], pwt->h[3]); + pwd->h[4] =3D msa_aver_u_df(DF_HALF, pws->h[4], pwt->h[4]); + pwd->h[5] =3D msa_aver_u_df(DF_HALF, pws->h[5], pwt->h[5]); + pwd->h[6] =3D msa_aver_u_df(DF_HALF, pws->h[6], pwt->h[6]); + pwd->h[7] =3D msa_aver_u_df(DF_HALF, pws->h[7], pwt->h[7]); +} + +void helper_msa_aver_u_w(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); + + pwd->w[0] =3D msa_aver_u_df(DF_WORD, pws->w[0], pwt->w[0]); + pwd->w[1] =3D msa_aver_u_df(DF_WORD, pws->w[1], pwt->w[1]); + pwd->w[2] =3D msa_aver_u_df(DF_WORD, pws->w[2], pwt->w[2]); + pwd->w[3] =3D msa_aver_u_df(DF_WORD, pws->w[3], pwt->w[3]); +} + +void helper_msa_aver_u_d(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); + + pwd->d[0] =3D msa_aver_u_df(DF_DOUBLE, pws->d[0], pwt->d[0]); + pwd->d[1] =3D msa_aver_u_df(DF_DOUBLE, pws->d[1], pwt->d[1]); +} + =20 /* * Int Compare @@ -1744,20 +1890,6 @@ static inline uint64_t msa_adds_u_df(uint32_t df, ui= nt64_t arg1, uint64_t arg2) return (u_arg1 < max_uint - u_arg2) ? u_arg1 + u_arg2 : max_uint; } =20 -static inline int64_t msa_aver_s_df(uint32_t df, int64_t arg1, int64_t arg= 2) -{ - /* signed shift */ - return (arg1 >> 1) + (arg2 >> 1) + ((arg1 | arg2) & 1); -} - -static inline uint64_t msa_aver_u_df(uint32_t df, uint64_t arg1, uint64_t = arg2) -{ - uint64_t u_arg1 =3D UNSIGNED(arg1, df); - uint64_t u_arg2 =3D UNSIGNED(arg2, df); - /* unsigned shift */ - return (u_arg1 >> 1) + (u_arg2 >> 1) + ((u_arg1 | u_arg2) & 1); -} - static inline int64_t msa_subs_s_df(uint32_t df, int64_t arg1, int64_t arg= 2) { int64_t max_int =3D DF_MAX_INT(df); @@ -2065,8 +2197,6 @@ MSA_BINOP_DF(add_a) MSA_BINOP_DF(adds_a) MSA_BINOP_DF(adds_s) MSA_BINOP_DF(adds_u) -MSA_BINOP_DF(aver_s) -MSA_BINOP_DF(aver_u) MSA_BINOP_DF(subs_s) MSA_BINOP_DF(subs_u) MSA_BINOP_DF(subsus_u) diff --git a/target/mips/translate.c b/target/mips/translate.c index 2b0abbb..9b186d3 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -28498,6 +28498,38 @@ static void gen_msa_3r(CPUMIPSState *env, DisasCon= text *ctx) break; } break; + case OPC_AVER_S_df: + switch (df) { + case DF_BYTE: + gen_helper_msa_aver_s_b(cpu_env, twd, tws, twt); + break; + case DF_HALF: + gen_helper_msa_aver_s_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_aver_s_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_aver_s_d(cpu_env, twd, tws, twt); + break; + } + break; + case OPC_AVER_U_df: + switch (df) { + case DF_BYTE: + gen_helper_msa_aver_u_b(cpu_env, twd, tws, twt); + break; + case DF_HALF: + gen_helper_msa_aver_u_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_aver_u_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_aver_u_d(cpu_env, twd, tws, twt); + break; + } + break; case OPC_SLL_df: gen_helper_msa_sll_df(cpu_env, tdf, twd, tws, twt); break; @@ -28615,9 +28647,6 @@ static void gen_msa_3r(CPUMIPSState *env, DisasCont= ext *ctx) case OPC_MAX_A_df: gen_helper_msa_max_a_df(cpu_env, tdf, twd, tws, twt); break; - case OPC_AVER_S_df: - gen_helper_msa_aver_s_df(cpu_env, tdf, twd, tws, twt); - break; case OPC_MOD_S_df: gen_helper_msa_mod_s_df(cpu_env, tdf, twd, tws, twt); break; @@ -28627,9 +28656,6 @@ static void gen_msa_3r(CPUMIPSState *env, DisasCont= ext *ctx) case OPC_MIN_A_df: gen_helper_msa_min_a_df(cpu_env, tdf, twd, tws, twt); break; - case OPC_AVER_U_df: - gen_helper_msa_aver_u_df(cpu_env, tdf, twd, tws, twt); - break; case OPC_MOD_U_df: gen_helper_msa_mod_u_df(cpu_env, tdf, twd, tws, twt); break; --=20 2.7.4 From nobody Sat May 4 18:23:24 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1569943687; cv=none; d=zoho.com; s=zohoarc; b=NlTeaAPdyUlzP5G00d0ctDdQn41XKg8D2t1C5ea+9n1JnIRaaT8Ct8VjfTIdi7y6Vkx88DmoLDw+ou5p0POjpm3lZe2XCp7ilE3vT0YyghNoADLKz/ueedAGxj3JlEGdBbDcYbzHjQI0GLSC/KBWvFtQ0eBdDYVgv1NX3GSNXFI= ARC-Message-Signature: i=1; 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Tue, 01 Oct 2019 11:17:06 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iFJte-0001vD-As for qemu-devel@nongnu.org; Tue, 01 Oct 2019 11:17:05 -0400 Received: from mx2.rt-rk.com ([89.216.37.149]:59932 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1iFJtd-0001sz-O9 for qemu-devel@nongnu.org; Tue, 01 Oct 2019 11:17:02 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id 392D11A23B5; Tue, 1 Oct 2019 17:15:55 +0200 (CEST) Received: from rtrkw774-lin.domain.local (rtrkw774-lin.domain.local [10.10.13.55]) by mail.rt-rk.com (Postfix) with ESMTPSA id BCD781A22D5; Tue, 1 Oct 2019 17:15:54 +0200 (CEST) X-Virus-Scanned: amavisd-new at rt-rk.com From: Aleksandar Markovic To: qemu-devel@nongnu.org Subject: [PULL 12/18] target/mips: msa: Split helpers for CEQ. Date: Tue, 1 Oct 2019 17:15:38 +0200 Message-Id: <1569942944-10381-13-git-send-email-aleksandar.markovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1569942944-10381-1-git-send-email-aleksandar.markovic@rt-rk.com> References: <1569942944-10381-1-git-send-email-aleksandar.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 89.216.37.149 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, amarkovic@wavecomp.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Aleksandar Markovic Achieves clearer code and slightly better performance. Signed-off-by: Aleksandar Markovic Reviewed-by: Aleksandar Rikalo Message-Id: <1569415572-19635-15-git-send-email-aleksandar.markovic@rt-rk.c= om> --- target/mips/helper.h | 6 +++- target/mips/msa_helper.c | 73 +++++++++++++++++++++++++++++++++++++++++++-= ---- target/mips/translate.c | 19 +++++++++++-- 3 files changed, 87 insertions(+), 11 deletions(-) diff --git a/target/mips/helper.h b/target/mips/helper.h index 9d4c9f1..95eb065 100644 --- a/target/mips/helper.h +++ b/target/mips/helper.h @@ -842,6 +842,11 @@ DEF_HELPER_4(msa_aver_u_h, void, env, i32, i32, i32) DEF_HELPER_4(msa_aver_u_w, void, env, i32, i32, i32) DEF_HELPER_4(msa_aver_u_d, void, env, i32, i32, i32) =20 +DEF_HELPER_4(msa_ceq_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_ceq_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_ceq_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_ceq_d, void, env, i32, i32, i32) + =20 DEF_HELPER_4(msa_andi_b, void, env, i32, i32, i32) DEF_HELPER_4(msa_ori_b, void, env, i32, i32, i32) @@ -891,7 +896,6 @@ DEF_HELPER_5(msa_min_s_df, void, env, i32, i32, i32, i3= 2) DEF_HELPER_5(msa_min_u_df, void, env, i32, i32, i32, i32) DEF_HELPER_5(msa_max_a_df, void, env, i32, i32, i32, i32) DEF_HELPER_5(msa_min_a_df, void, env, i32, i32, i32, i32) -DEF_HELPER_5(msa_ceq_df, void, env, i32, i32, i32, i32) DEF_HELPER_5(msa_clt_s_df, void, env, i32, i32, i32, i32) DEF_HELPER_5(msa_clt_u_df, void, env, i32, i32, i32, i32) DEF_HELPER_5(msa_cle_s_df, void, env, i32, i32, i32, i32) diff --git a/target/mips/msa_helper.c b/target/mips/msa_helper.c index 17443b9..c8c6cdb 100644 --- a/target/mips/msa_helper.c +++ b/target/mips/msa_helper.c @@ -1153,7 +1153,72 @@ void helper_msa_aver_u_d(CPUMIPSState *env, * +---------------+------------------------------------------------------= ----+ */ =20 -/* TODO: insert Int Compare group helpers here */ +static inline int64_t msa_ceq_df(uint32_t df, int64_t arg1, int64_t arg2) +{ + return arg1 =3D=3D arg2 ? -1 : 0; +} + +void helper_msa_ceq_b(CPUMIPSState *env, uint32_t wd, uint32_t ws, uint32_= t wt) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); + + pwd->b[0] =3D msa_ceq_df(DF_BYTE, pws->b[0], pwt->b[0]); + pwd->b[1] =3D msa_ceq_df(DF_BYTE, pws->b[1], pwt->b[1]); + pwd->b[2] =3D msa_ceq_df(DF_BYTE, pws->b[2], pwt->b[2]); + pwd->b[3] =3D msa_ceq_df(DF_BYTE, pws->b[3], pwt->b[3]); + pwd->b[4] =3D msa_ceq_df(DF_BYTE, pws->b[4], pwt->b[4]); + pwd->b[5] =3D msa_ceq_df(DF_BYTE, pws->b[5], pwt->b[5]); + pwd->b[6] =3D msa_ceq_df(DF_BYTE, pws->b[6], pwt->b[6]); + pwd->b[7] =3D msa_ceq_df(DF_BYTE, pws->b[7], pwt->b[7]); + pwd->b[8] =3D msa_ceq_df(DF_BYTE, pws->b[8], pwt->b[8]); + pwd->b[9] =3D msa_ceq_df(DF_BYTE, pws->b[9], pwt->b[9]); + pwd->b[10] =3D msa_ceq_df(DF_BYTE, pws->b[10], pwt->b[10]); + pwd->b[11] =3D msa_ceq_df(DF_BYTE, pws->b[11], pwt->b[11]); + pwd->b[12] =3D msa_ceq_df(DF_BYTE, pws->b[12], pwt->b[12]); + pwd->b[13] =3D msa_ceq_df(DF_BYTE, pws->b[13], pwt->b[13]); + pwd->b[14] =3D msa_ceq_df(DF_BYTE, pws->b[14], pwt->b[14]); + pwd->b[15] =3D msa_ceq_df(DF_BYTE, pws->b[15], pwt->b[15]); +} + +void helper_msa_ceq_h(CPUMIPSState *env, uint32_t wd, uint32_t ws, uint32_= t wt) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); + + pwd->h[0] =3D msa_ceq_df(DF_HALF, pws->h[0], pwt->h[0]); + pwd->h[1] =3D msa_ceq_df(DF_HALF, pws->h[1], pwt->h[1]); + pwd->h[2] =3D msa_ceq_df(DF_HALF, pws->h[2], pwt->h[2]); + pwd->h[3] =3D msa_ceq_df(DF_HALF, pws->h[3], pwt->h[3]); + pwd->h[4] =3D msa_ceq_df(DF_HALF, pws->h[4], pwt->h[4]); + pwd->h[5] =3D msa_ceq_df(DF_HALF, pws->h[5], pwt->h[5]); + pwd->h[6] =3D msa_ceq_df(DF_HALF, pws->h[6], pwt->h[6]); + pwd->h[7] =3D msa_ceq_df(DF_HALF, pws->h[7], pwt->h[7]); +} + +void helper_msa_ceq_w(CPUMIPSState *env, uint32_t wd, uint32_t ws, uint32_= t wt) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); + + pwd->w[0] =3D msa_ceq_df(DF_WORD, pws->w[0], pwt->w[0]); + pwd->w[1] =3D msa_ceq_df(DF_WORD, pws->w[1], pwt->w[1]); + pwd->w[2] =3D msa_ceq_df(DF_WORD, pws->w[2], pwt->w[2]); + pwd->w[3] =3D msa_ceq_df(DF_WORD, pws->w[3], pwt->w[3]); +} + +void helper_msa_ceq_d(CPUMIPSState *env, uint32_t wd, uint32_t ws, uint32_= t wt) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); + + pwd->d[0] =3D msa_ceq_df(DF_DOUBLE, pws->d[0], pwt->d[0]); + pwd->d[1] =3D msa_ceq_df(DF_DOUBLE, pws->d[1], pwt->d[1]); +} =20 =20 /* @@ -1562,11 +1627,6 @@ static inline int64_t msa_subv_df(uint32_t df, int64= _t arg1, int64_t arg2) return arg1 - arg2; } =20 -static inline int64_t msa_ceq_df(uint32_t df, int64_t arg1, int64_t arg2) -{ - return arg1 =3D=3D arg2 ? -1 : 0; -} - static inline int64_t msa_cle_s_df(uint32_t df, int64_t arg1, int64_t arg2) { return arg1 <=3D arg2 ? -1 : 0; @@ -2188,7 +2248,6 @@ MSA_BINOP_DF(min_s) MSA_BINOP_DF(min_u) MSA_BINOP_DF(max_a) MSA_BINOP_DF(min_a) -MSA_BINOP_DF(ceq) MSA_BINOP_DF(clt_s) MSA_BINOP_DF(clt_u) MSA_BINOP_DF(cle_s) diff --git a/target/mips/translate.c b/target/mips/translate.c index 9b186d3..ad1572e 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -28530,15 +28530,28 @@ static void gen_msa_3r(CPUMIPSState *env, DisasCo= ntext *ctx) break; } break; + case OPC_CEQ_df: + switch (df) { + case DF_BYTE: + gen_helper_msa_ceq_b(cpu_env, twd, tws, twt); + break; + case DF_HALF: + gen_helper_msa_ceq_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_ceq_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_ceq_d(cpu_env, twd, tws, twt); + break; + } + break; case OPC_SLL_df: gen_helper_msa_sll_df(cpu_env, tdf, twd, tws, twt); break; case OPC_ADDV_df: gen_helper_msa_addv_df(cpu_env, tdf, twd, tws, twt); break; - case OPC_CEQ_df: - gen_helper_msa_ceq_df(cpu_env, tdf, twd, tws, twt); - break; case OPC_ADD_A_df: gen_helper_msa_add_a_df(cpu_env, tdf, twd, tws, twt); break; --=20 2.7.4 From nobody Sat May 4 18:23:24 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1569943496; cv=none; d=zoho.com; s=zohoarc; b=Fu9hu8WM6mdfk+2AEkrpnfYfVQ0BQI0FJKpgYiqUc/L8930PBa29eGJzNze/DQses7ME5eAL6uiopyGQsItUxZHSV9pLvxXv2E1hFb35j7eYpEp5FXGoKFTTVjxc+jn0USQYVMVjrGK0w1HCsgPlNnmVOaE1l2YHhTH7XosI24Y= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1569943496; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=Jtq2FsvNir0l1h54IEDGMg777TnQbYDgpFxM0ouvRo8=; b=AEC8XWX6KkjzRNcNjwTJDKP+tVsgQ8qQtmMH+wt+txQpK5ZLuh8utHzgypx8LFcTRyggF7EPFSb6zPB4O9oRfk5fQsUcH1qvAtpxwG8dZkJ046El81yQZHizRs0WKakv//KCpzR3d5N++xYKs7Ptp5lGQIEAmOCprxlZ11MM1ec= ARC-Authentication-Results: i=1; mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 156994349644294.893329689202; Tue, 1 Oct 2019 08:24:56 -0700 (PDT) Received: from localhost ([::1]:43384 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iFK1G-0002zr-OQ for importer@patchew.org; Tue, 01 Oct 2019 11:24:54 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:45370) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iFJth-0004hO-DQ for qemu-devel@nongnu.org; Tue, 01 Oct 2019 11:17:07 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iFJte-0001v4-Aj for qemu-devel@nongnu.org; Tue, 01 Oct 2019 11:17:05 -0400 Received: from mx2.rt-rk.com ([89.216.37.149]:59927 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1iFJtd-0001sr-M1 for qemu-devel@nongnu.org; Tue, 01 Oct 2019 11:17:02 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id 394411A23C3; Tue, 1 Oct 2019 17:15:55 +0200 (CEST) Received: from rtrkw774-lin.domain.local (rtrkw774-lin.domain.local [10.10.13.55]) by mail.rt-rk.com (Postfix) with ESMTPSA id C31721A239B; Tue, 1 Oct 2019 17:15:54 +0200 (CEST) X-Virus-Scanned: amavisd-new at rt-rk.com From: Aleksandar Markovic To: qemu-devel@nongnu.org Subject: [PULL 13/18] target/mips: msa: Split helpers for CLE_. Date: Tue, 1 Oct 2019 17:15:39 +0200 Message-Id: <1569942944-10381-14-git-send-email-aleksandar.markovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1569942944-10381-1-git-send-email-aleksandar.markovic@rt-rk.com> References: <1569942944-10381-1-git-send-email-aleksandar.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 89.216.37.149 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, amarkovic@wavecomp.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Aleksandar Markovic Achieves clearer code and slightly better performance. Signed-off-by: Aleksandar Markovic Reviewed-by: Aleksandar Rikalo Message-Id: <1569415572-19635-16-git-send-email-aleksandar.markovic@rt-rk.c= om> --- target/mips/helper.h | 12 +++- target/mips/msa_helper.c | 158 ++++++++++++++++++++++++++++++++++++++++++-= ---- target/mips/translate.c | 38 ++++++++++-- 3 files changed, 186 insertions(+), 22 deletions(-) diff --git a/target/mips/helper.h b/target/mips/helper.h index 95eb065..32ff24b 100644 --- a/target/mips/helper.h +++ b/target/mips/helper.h @@ -847,6 +847,16 @@ DEF_HELPER_4(msa_ceq_h, void, env, i32, i32, i32) DEF_HELPER_4(msa_ceq_w, void, env, i32, i32, i32) DEF_HELPER_4(msa_ceq_d, void, env, i32, i32, i32) =20 +DEF_HELPER_4(msa_cle_s_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_cle_s_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_cle_s_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_cle_s_d, void, env, i32, i32, i32) + +DEF_HELPER_4(msa_cle_u_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_cle_u_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_cle_u_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_cle_u_d, void, env, i32, i32, i32) + =20 DEF_HELPER_4(msa_andi_b, void, env, i32, i32, i32) DEF_HELPER_4(msa_ori_b, void, env, i32, i32, i32) @@ -898,8 +908,6 @@ DEF_HELPER_5(msa_max_a_df, void, env, i32, i32, i32, i3= 2) DEF_HELPER_5(msa_min_a_df, void, env, i32, i32, i32, i32) DEF_HELPER_5(msa_clt_s_df, void, env, i32, i32, i32, i32) DEF_HELPER_5(msa_clt_u_df, void, env, i32, i32, i32, i32) -DEF_HELPER_5(msa_cle_s_df, void, env, i32, i32, i32, i32) -DEF_HELPER_5(msa_cle_u_df, void, env, i32, i32, i32, i32) DEF_HELPER_5(msa_add_a_df, void, env, i32, i32, i32, i32) DEF_HELPER_5(msa_adds_a_df, void, env, i32, i32, i32, i32) DEF_HELPER_5(msa_adds_s_df, void, env, i32, i32, i32, i32) diff --git a/target/mips/msa_helper.c b/target/mips/msa_helper.c index c8c6cdb..d696791 100644 --- a/target/mips/msa_helper.c +++ b/target/mips/msa_helper.c @@ -1220,6 +1220,150 @@ void helper_msa_ceq_d(CPUMIPSState *env, uint32_t w= d, uint32_t ws, uint32_t wt) pwd->d[1] =3D msa_ceq_df(DF_DOUBLE, pws->d[1], pwt->d[1]); } =20 +static inline int64_t msa_cle_s_df(uint32_t df, int64_t arg1, int64_t arg2) +{ + return arg1 <=3D arg2 ? -1 : 0; +} + +void helper_msa_cle_s_b(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); + + pwd->b[0] =3D msa_cle_s_df(DF_BYTE, pws->b[0], pwt->b[0]); + pwd->b[1] =3D msa_cle_s_df(DF_BYTE, pws->b[1], pwt->b[1]); + pwd->b[2] =3D msa_cle_s_df(DF_BYTE, pws->b[2], pwt->b[2]); + pwd->b[3] =3D msa_cle_s_df(DF_BYTE, pws->b[3], pwt->b[3]); + pwd->b[4] =3D msa_cle_s_df(DF_BYTE, pws->b[4], pwt->b[4]); + pwd->b[5] =3D msa_cle_s_df(DF_BYTE, pws->b[5], pwt->b[5]); + pwd->b[6] =3D msa_cle_s_df(DF_BYTE, pws->b[6], pwt->b[6]); + pwd->b[7] =3D msa_cle_s_df(DF_BYTE, pws->b[7], pwt->b[7]); + pwd->b[8] =3D msa_cle_s_df(DF_BYTE, pws->b[8], pwt->b[8]); + pwd->b[9] =3D msa_cle_s_df(DF_BYTE, pws->b[9], pwt->b[9]); + pwd->b[10] =3D msa_cle_s_df(DF_BYTE, pws->b[10], pwt->b[10]); + pwd->b[11] =3D msa_cle_s_df(DF_BYTE, pws->b[11], pwt->b[11]); + pwd->b[12] =3D msa_cle_s_df(DF_BYTE, pws->b[12], pwt->b[12]); + pwd->b[13] =3D msa_cle_s_df(DF_BYTE, pws->b[13], pwt->b[13]); + pwd->b[14] =3D msa_cle_s_df(DF_BYTE, pws->b[14], pwt->b[14]); + pwd->b[15] =3D msa_cle_s_df(DF_BYTE, pws->b[15], pwt->b[15]); +} + +void helper_msa_cle_s_h(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); + + pwd->h[0] =3D msa_cle_s_df(DF_HALF, pws->h[0], pwt->h[0]); + pwd->h[1] =3D msa_cle_s_df(DF_HALF, pws->h[1], pwt->h[1]); + pwd->h[2] =3D msa_cle_s_df(DF_HALF, pws->h[2], pwt->h[2]); + pwd->h[3] =3D msa_cle_s_df(DF_HALF, pws->h[3], pwt->h[3]); + pwd->h[4] =3D msa_cle_s_df(DF_HALF, pws->h[4], pwt->h[4]); + pwd->h[5] =3D msa_cle_s_df(DF_HALF, pws->h[5], pwt->h[5]); + pwd->h[6] =3D msa_cle_s_df(DF_HALF, pws->h[6], pwt->h[6]); + pwd->h[7] =3D msa_cle_s_df(DF_HALF, pws->h[7], pwt->h[7]); +} + +void helper_msa_cle_s_w(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); + + pwd->w[0] =3D msa_cle_s_df(DF_WORD, pws->w[0], pwt->w[0]); + pwd->w[1] =3D msa_cle_s_df(DF_WORD, pws->w[1], pwt->w[1]); + pwd->w[2] =3D msa_cle_s_df(DF_WORD, pws->w[2], pwt->w[2]); + pwd->w[3] =3D msa_cle_s_df(DF_WORD, pws->w[3], pwt->w[3]); +} + +void helper_msa_cle_s_d(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); + + pwd->d[0] =3D msa_cle_s_df(DF_DOUBLE, pws->d[0], pwt->d[0]); + pwd->d[1] =3D msa_cle_s_df(DF_DOUBLE, pws->d[1], pwt->d[1]); +} + +static inline int64_t msa_cle_u_df(uint32_t df, int64_t arg1, int64_t arg2) +{ + uint64_t u_arg1 =3D UNSIGNED(arg1, df); + uint64_t u_arg2 =3D UNSIGNED(arg2, df); + return u_arg1 <=3D u_arg2 ? -1 : 0; +} + +void helper_msa_cle_u_b(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); + + pwd->b[0] =3D msa_cle_u_df(DF_BYTE, pws->b[0], pwt->b[0]); + pwd->b[1] =3D msa_cle_u_df(DF_BYTE, pws->b[1], pwt->b[1]); + pwd->b[2] =3D msa_cle_u_df(DF_BYTE, pws->b[2], pwt->b[2]); + pwd->b[3] =3D msa_cle_u_df(DF_BYTE, pws->b[3], pwt->b[3]); + pwd->b[4] =3D msa_cle_u_df(DF_BYTE, pws->b[4], pwt->b[4]); + pwd->b[5] =3D msa_cle_u_df(DF_BYTE, pws->b[5], pwt->b[5]); + pwd->b[6] =3D msa_cle_u_df(DF_BYTE, pws->b[6], pwt->b[6]); + pwd->b[7] =3D msa_cle_u_df(DF_BYTE, pws->b[7], pwt->b[7]); + pwd->b[8] =3D msa_cle_u_df(DF_BYTE, pws->b[8], pwt->b[8]); + pwd->b[9] =3D msa_cle_u_df(DF_BYTE, pws->b[9], pwt->b[9]); + pwd->b[10] =3D msa_cle_u_df(DF_BYTE, pws->b[10], pwt->b[10]); + pwd->b[11] =3D msa_cle_u_df(DF_BYTE, pws->b[11], pwt->b[11]); + pwd->b[12] =3D msa_cle_u_df(DF_BYTE, pws->b[12], pwt->b[12]); + pwd->b[13] =3D msa_cle_u_df(DF_BYTE, pws->b[13], pwt->b[13]); + pwd->b[14] =3D msa_cle_u_df(DF_BYTE, pws->b[14], pwt->b[14]); + pwd->b[15] =3D msa_cle_u_df(DF_BYTE, pws->b[15], pwt->b[15]); +} + +void helper_msa_cle_u_h(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); + + pwd->h[0] =3D msa_cle_u_df(DF_HALF, pws->h[0], pwt->h[0]); + pwd->h[1] =3D msa_cle_u_df(DF_HALF, pws->h[1], pwt->h[1]); + pwd->h[2] =3D msa_cle_u_df(DF_HALF, pws->h[2], pwt->h[2]); + pwd->h[3] =3D msa_cle_u_df(DF_HALF, pws->h[3], pwt->h[3]); + pwd->h[4] =3D msa_cle_u_df(DF_HALF, pws->h[4], pwt->h[4]); + pwd->h[5] =3D msa_cle_u_df(DF_HALF, pws->h[5], pwt->h[5]); + pwd->h[6] =3D msa_cle_u_df(DF_HALF, pws->h[6], pwt->h[6]); + pwd->h[7] =3D msa_cle_u_df(DF_HALF, pws->h[7], pwt->h[7]); +} + +void helper_msa_cle_u_w(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); + + pwd->w[0] =3D msa_cle_u_df(DF_WORD, pws->w[0], pwt->w[0]); + pwd->w[1] =3D msa_cle_u_df(DF_WORD, pws->w[1], pwt->w[1]); + pwd->w[2] =3D msa_cle_u_df(DF_WORD, pws->w[2], pwt->w[2]); + pwd->w[3] =3D msa_cle_u_df(DF_WORD, pws->w[3], pwt->w[3]); +} + +void helper_msa_cle_u_d(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); + + pwd->d[0] =3D msa_cle_u_df(DF_DOUBLE, pws->d[0], pwt->d[0]); + pwd->d[1] =3D msa_cle_u_df(DF_DOUBLE, pws->d[1], pwt->d[1]); +} + =20 /* * Int Divide @@ -1627,18 +1771,6 @@ static inline int64_t msa_subv_df(uint32_t df, int64= _t arg1, int64_t arg2) return arg1 - arg2; } =20 -static inline int64_t msa_cle_s_df(uint32_t df, int64_t arg1, int64_t arg2) -{ - return arg1 <=3D arg2 ? -1 : 0; -} - -static inline int64_t msa_cle_u_df(uint32_t df, int64_t arg1, int64_t arg2) -{ - uint64_t u_arg1 =3D UNSIGNED(arg1, df); - uint64_t u_arg2 =3D UNSIGNED(arg2, df); - return u_arg1 <=3D u_arg2 ? -1 : 0; -} - static inline int64_t msa_clt_s_df(uint32_t df, int64_t arg1, int64_t arg2) { return arg1 < arg2 ? -1 : 0; @@ -2250,8 +2382,6 @@ MSA_BINOP_DF(max_a) MSA_BINOP_DF(min_a) MSA_BINOP_DF(clt_s) MSA_BINOP_DF(clt_u) -MSA_BINOP_DF(cle_s) -MSA_BINOP_DF(cle_u) MSA_BINOP_DF(add_a) MSA_BINOP_DF(adds_a) MSA_BINOP_DF(adds_s) diff --git a/target/mips/translate.c b/target/mips/translate.c index ad1572e..614b9e7 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -28546,6 +28546,38 @@ static void gen_msa_3r(CPUMIPSState *env, DisasCon= text *ctx) break; } break; + case OPC_CLE_S_df: + switch (df) { + case DF_BYTE: + gen_helper_msa_cle_s_b(cpu_env, twd, tws, twt); + break; + case DF_HALF: + gen_helper_msa_cle_s_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_cle_s_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_cle_s_d(cpu_env, twd, tws, twt); + break; + } + break; + case OPC_CLE_U_df: + switch (df) { + case DF_BYTE: + gen_helper_msa_cle_u_b(cpu_env, twd, tws, twt); + break; + case DF_HALF: + gen_helper_msa_cle_u_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_cle_u_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_cle_u_d(cpu_env, twd, tws, twt); + break; + } + break; case OPC_SLL_df: gen_helper_msa_sll_df(cpu_env, tdf, twd, tws, twt); break; @@ -28630,9 +28662,6 @@ static void gen_msa_3r(CPUMIPSState *env, DisasCont= ext *ctx) case OPC_MIN_S_df: gen_helper_msa_min_s_df(cpu_env, tdf, twd, tws, twt); break; - case OPC_CLE_S_df: - gen_helper_msa_cle_s_df(cpu_env, tdf, twd, tws, twt); - break; case OPC_ASUB_S_df: gen_helper_msa_asub_s_df(cpu_env, tdf, twd, tws, twt); break; @@ -28645,9 +28674,6 @@ static void gen_msa_3r(CPUMIPSState *env, DisasCont= ext *ctx) case OPC_MIN_U_df: gen_helper_msa_min_u_df(cpu_env, tdf, twd, tws, twt); break; - case OPC_CLE_U_df: - gen_helper_msa_cle_u_df(cpu_env, tdf, twd, tws, twt); - break; case OPC_ASUB_U_df: gen_helper_msa_asub_u_df(cpu_env, tdf, twd, tws, twt); break; --=20 2.7.4 From nobody Sat May 4 18:23:24 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1569944374; cv=none; d=zoho.com; s=zohoarc; b=iaW9Xm9gDkQWGCo7NgQVQVmPcOOVnRhKEp35eRzoA2Ghd1Klc5uKR5IyOK84vs3e3r2QPRV3BJTSejP+nZ1S5ZTszzUeAVdddoA8Ss5jAQ6FM4p+pcmpvPek6liGGv6/pWHnyN8hqc9uecZ3YYpN0arblWfNTEfGUOmUVjBmWSo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1569944374; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; 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Tue, 01 Oct 2019 11:17:14 -0400 Received: from mx2.rt-rk.com ([89.216.37.149]:59937 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1iFJtn-0001tB-TZ for qemu-devel@nongnu.org; Tue, 01 Oct 2019 11:17:12 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id 3D80C1A23A8; Tue, 1 Oct 2019 17:15:55 +0200 (CEST) Received: from rtrkw774-lin.domain.local (rtrkw774-lin.domain.local [10.10.13.55]) by mail.rt-rk.com (Postfix) with ESMTPSA id D04221A22D4; Tue, 1 Oct 2019 17:15:54 +0200 (CEST) X-Virus-Scanned: amavisd-new at rt-rk.com From: Aleksandar Markovic To: qemu-devel@nongnu.org Subject: [PULL 14/18] target/mips: msa: Split helpers for CLT_. Date: Tue, 1 Oct 2019 17:15:40 +0200 Message-Id: <1569942944-10381-15-git-send-email-aleksandar.markovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1569942944-10381-1-git-send-email-aleksandar.markovic@rt-rk.com> References: <1569942944-10381-1-git-send-email-aleksandar.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 89.216.37.149 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, amarkovic@wavecomp.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Aleksandar Markovic Achieves clearer code and slightly better performance. Signed-off-by: Aleksandar Markovic Reviewed-by: Aleksandar Rikalo Message-Id: <1569415572-19635-17-git-send-email-aleksandar.markovic@rt-rk.c= om> --- target/mips/helper.h | 12 +++- target/mips/msa_helper.c | 158 ++++++++++++++++++++++++++++++++++++++++++-= ---- target/mips/translate.c | 38 ++++++++++-- 3 files changed, 186 insertions(+), 22 deletions(-) diff --git a/target/mips/helper.h b/target/mips/helper.h index 32ff24b..29dfcf0 100644 --- a/target/mips/helper.h +++ b/target/mips/helper.h @@ -857,6 +857,16 @@ DEF_HELPER_4(msa_cle_u_h, void, env, i32, i32, i32) DEF_HELPER_4(msa_cle_u_w, void, env, i32, i32, i32) DEF_HELPER_4(msa_cle_u_d, void, env, i32, i32, i32) =20 +DEF_HELPER_4(msa_clt_s_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_clt_s_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_clt_s_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_clt_s_d, void, env, i32, i32, i32) + +DEF_HELPER_4(msa_clt_u_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_clt_u_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_clt_u_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_clt_u_d, void, env, i32, i32, i32) + =20 DEF_HELPER_4(msa_andi_b, void, env, i32, i32, i32) DEF_HELPER_4(msa_ori_b, void, env, i32, i32, i32) @@ -906,8 +916,6 @@ DEF_HELPER_5(msa_min_s_df, void, env, i32, i32, i32, i3= 2) DEF_HELPER_5(msa_min_u_df, void, env, i32, i32, i32, i32) DEF_HELPER_5(msa_max_a_df, void, env, i32, i32, i32, i32) DEF_HELPER_5(msa_min_a_df, void, env, i32, i32, i32, i32) -DEF_HELPER_5(msa_clt_s_df, void, env, i32, i32, i32, i32) -DEF_HELPER_5(msa_clt_u_df, void, env, i32, i32, i32, i32) DEF_HELPER_5(msa_add_a_df, void, env, i32, i32, i32, i32) DEF_HELPER_5(msa_adds_a_df, void, env, i32, i32, i32, i32) DEF_HELPER_5(msa_adds_s_df, void, env, i32, i32, i32, i32) diff --git a/target/mips/msa_helper.c b/target/mips/msa_helper.c index d696791..b658f48 100644 --- a/target/mips/msa_helper.c +++ b/target/mips/msa_helper.c @@ -1364,6 +1364,150 @@ void helper_msa_cle_u_d(CPUMIPSState *env, pwd->d[1] =3D msa_cle_u_df(DF_DOUBLE, pws->d[1], pwt->d[1]); } =20 +static inline int64_t msa_clt_s_df(uint32_t df, int64_t arg1, int64_t arg2) +{ + return arg1 < arg2 ? -1 : 0; +} + +void helper_msa_clt_s_b(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); + + pwd->b[0] =3D msa_clt_s_df(DF_BYTE, pws->b[0], pwt->b[0]); + pwd->b[1] =3D msa_clt_s_df(DF_BYTE, pws->b[1], pwt->b[1]); + pwd->b[2] =3D msa_clt_s_df(DF_BYTE, pws->b[2], pwt->b[2]); + pwd->b[3] =3D msa_clt_s_df(DF_BYTE, pws->b[3], pwt->b[3]); + pwd->b[4] =3D msa_clt_s_df(DF_BYTE, pws->b[4], pwt->b[4]); + pwd->b[5] =3D msa_clt_s_df(DF_BYTE, pws->b[5], pwt->b[5]); + pwd->b[6] =3D msa_clt_s_df(DF_BYTE, pws->b[6], pwt->b[6]); + pwd->b[7] =3D msa_clt_s_df(DF_BYTE, pws->b[7], pwt->b[7]); + pwd->b[8] =3D msa_clt_s_df(DF_BYTE, pws->b[8], pwt->b[8]); + pwd->b[9] =3D msa_clt_s_df(DF_BYTE, pws->b[9], pwt->b[9]); + pwd->b[10] =3D msa_clt_s_df(DF_BYTE, pws->b[10], pwt->b[10]); + pwd->b[11] =3D msa_clt_s_df(DF_BYTE, pws->b[11], pwt->b[11]); + pwd->b[12] =3D msa_clt_s_df(DF_BYTE, pws->b[12], pwt->b[12]); + pwd->b[13] =3D msa_clt_s_df(DF_BYTE, pws->b[13], pwt->b[13]); + pwd->b[14] =3D msa_clt_s_df(DF_BYTE, pws->b[14], pwt->b[14]); + pwd->b[15] =3D msa_clt_s_df(DF_BYTE, pws->b[15], pwt->b[15]); +} + +void helper_msa_clt_s_h(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); + + pwd->h[0] =3D msa_clt_s_df(DF_HALF, pws->h[0], pwt->h[0]); + pwd->h[1] =3D msa_clt_s_df(DF_HALF, pws->h[1], pwt->h[1]); + pwd->h[2] =3D msa_clt_s_df(DF_HALF, pws->h[2], pwt->h[2]); + pwd->h[3] =3D msa_clt_s_df(DF_HALF, pws->h[3], pwt->h[3]); + pwd->h[4] =3D msa_clt_s_df(DF_HALF, pws->h[4], pwt->h[4]); + pwd->h[5] =3D msa_clt_s_df(DF_HALF, pws->h[5], pwt->h[5]); + pwd->h[6] =3D msa_clt_s_df(DF_HALF, pws->h[6], pwt->h[6]); + pwd->h[7] =3D msa_clt_s_df(DF_HALF, pws->h[7], pwt->h[7]); +} + +void helper_msa_clt_s_w(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); + + pwd->w[0] =3D msa_clt_s_df(DF_WORD, pws->w[0], pwt->w[0]); + pwd->w[1] =3D msa_clt_s_df(DF_WORD, pws->w[1], pwt->w[1]); + pwd->w[2] =3D msa_clt_s_df(DF_WORD, pws->w[2], pwt->w[2]); + pwd->w[3] =3D msa_clt_s_df(DF_WORD, pws->w[3], pwt->w[3]); +} + +void helper_msa_clt_s_d(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); + + pwd->d[0] =3D msa_clt_s_df(DF_DOUBLE, pws->d[0], pwt->d[0]); + pwd->d[1] =3D msa_clt_s_df(DF_DOUBLE, pws->d[1], pwt->d[1]); +} + +static inline int64_t msa_clt_u_df(uint32_t df, int64_t arg1, int64_t arg2) +{ + uint64_t u_arg1 =3D UNSIGNED(arg1, df); + uint64_t u_arg2 =3D UNSIGNED(arg2, df); + return u_arg1 < u_arg2 ? -1 : 0; +} + +void helper_msa_clt_u_b(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); + + pwd->b[0] =3D msa_clt_u_df(DF_BYTE, pws->b[0], pwt->b[0]); + pwd->b[1] =3D msa_clt_u_df(DF_BYTE, pws->b[1], pwt->b[1]); + pwd->b[2] =3D msa_clt_u_df(DF_BYTE, pws->b[2], pwt->b[2]); + pwd->b[3] =3D msa_clt_u_df(DF_BYTE, pws->b[3], pwt->b[3]); + pwd->b[4] =3D msa_clt_u_df(DF_BYTE, pws->b[4], pwt->b[4]); + pwd->b[5] =3D msa_clt_u_df(DF_BYTE, pws->b[5], pwt->b[5]); + pwd->b[6] =3D msa_clt_u_df(DF_BYTE, pws->b[6], pwt->b[6]); + pwd->b[7] =3D msa_clt_u_df(DF_BYTE, pws->b[7], pwt->b[7]); + pwd->b[8] =3D msa_clt_u_df(DF_BYTE, pws->b[8], pwt->b[8]); + pwd->b[9] =3D msa_clt_u_df(DF_BYTE, pws->b[9], pwt->b[9]); + pwd->b[10] =3D msa_clt_u_df(DF_BYTE, pws->b[10], pwt->b[10]); + pwd->b[11] =3D msa_clt_u_df(DF_BYTE, pws->b[11], pwt->b[11]); + pwd->b[12] =3D msa_clt_u_df(DF_BYTE, pws->b[12], pwt->b[12]); + pwd->b[13] =3D msa_clt_u_df(DF_BYTE, pws->b[13], pwt->b[13]); + pwd->b[14] =3D msa_clt_u_df(DF_BYTE, pws->b[14], pwt->b[14]); + pwd->b[15] =3D msa_clt_u_df(DF_BYTE, pws->b[15], pwt->b[15]); +} + +void helper_msa_clt_u_h(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); + + pwd->h[0] =3D msa_clt_u_df(DF_HALF, pws->h[0], pwt->h[0]); + pwd->h[1] =3D msa_clt_u_df(DF_HALF, pws->h[1], pwt->h[1]); + pwd->h[2] =3D msa_clt_u_df(DF_HALF, pws->h[2], pwt->h[2]); + pwd->h[3] =3D msa_clt_u_df(DF_HALF, pws->h[3], pwt->h[3]); + pwd->h[4] =3D msa_clt_u_df(DF_HALF, pws->h[4], pwt->h[4]); + pwd->h[5] =3D msa_clt_u_df(DF_HALF, pws->h[5], pwt->h[5]); + pwd->h[6] =3D msa_clt_u_df(DF_HALF, pws->h[6], pwt->h[6]); + pwd->h[7] =3D msa_clt_u_df(DF_HALF, pws->h[7], pwt->h[7]); +} + +void helper_msa_clt_u_w(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); + + pwd->w[0] =3D msa_clt_u_df(DF_WORD, pws->w[0], pwt->w[0]); + pwd->w[1] =3D msa_clt_u_df(DF_WORD, pws->w[1], pwt->w[1]); + pwd->w[2] =3D msa_clt_u_df(DF_WORD, pws->w[2], pwt->w[2]); + pwd->w[3] =3D msa_clt_u_df(DF_WORD, pws->w[3], pwt->w[3]); +} + +void helper_msa_clt_u_d(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); + + pwd->d[0] =3D msa_clt_u_df(DF_DOUBLE, pws->d[0], pwt->d[0]); + pwd->d[1] =3D msa_clt_u_df(DF_DOUBLE, pws->d[1], pwt->d[1]); +} + =20 /* * Int Divide @@ -1771,18 +1915,6 @@ static inline int64_t msa_subv_df(uint32_t df, int64= _t arg1, int64_t arg2) return arg1 - arg2; } =20 -static inline int64_t msa_clt_s_df(uint32_t df, int64_t arg1, int64_t arg2) -{ - return arg1 < arg2 ? -1 : 0; -} - -static inline int64_t msa_clt_u_df(uint32_t df, int64_t arg1, int64_t arg2) -{ - uint64_t u_arg1 =3D UNSIGNED(arg1, df); - uint64_t u_arg2 =3D UNSIGNED(arg2, df); - return u_arg1 < u_arg2 ? -1 : 0; -} - static inline int64_t msa_max_s_df(uint32_t df, int64_t arg1, int64_t arg2) { return arg1 > arg2 ? arg1 : arg2; @@ -2380,8 +2512,6 @@ MSA_BINOP_DF(min_s) MSA_BINOP_DF(min_u) MSA_BINOP_DF(max_a) MSA_BINOP_DF(min_a) -MSA_BINOP_DF(clt_s) -MSA_BINOP_DF(clt_u) MSA_BINOP_DF(add_a) MSA_BINOP_DF(adds_a) MSA_BINOP_DF(adds_s) diff --git a/target/mips/translate.c b/target/mips/translate.c index 614b9e7..4db87d6 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -28578,6 +28578,38 @@ static void gen_msa_3r(CPUMIPSState *env, DisasCon= text *ctx) break; } break; + case OPC_CLT_S_df: + switch (df) { + case DF_BYTE: + gen_helper_msa_clt_s_b(cpu_env, twd, tws, twt); + break; + case DF_HALF: + gen_helper_msa_clt_s_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_clt_s_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_clt_s_d(cpu_env, twd, tws, twt); + break; + } + break; + case OPC_CLT_U_df: + switch (df) { + case DF_BYTE: + gen_helper_msa_clt_u_b(cpu_env, twd, tws, twt); + break; + case DF_HALF: + gen_helper_msa_clt_u_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_clt_u_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_clt_u_d(cpu_env, twd, tws, twt); + break; + } + break; case OPC_SLL_df: gen_helper_msa_sll_df(cpu_env, tdf, twd, tws, twt); break; @@ -28626,9 +28658,6 @@ static void gen_msa_3r(CPUMIPSState *env, DisasCont= ext *ctx) case OPC_MAX_S_df: gen_helper_msa_max_s_df(cpu_env, tdf, twd, tws, twt); break; - case OPC_CLT_S_df: - gen_helper_msa_clt_s_df(cpu_env, tdf, twd, tws, twt); - break; case OPC_ADDS_S_df: gen_helper_msa_adds_s_df(cpu_env, tdf, twd, tws, twt); break; @@ -28647,9 +28676,6 @@ static void gen_msa_3r(CPUMIPSState *env, DisasCont= ext *ctx) case OPC_MAX_U_df: gen_helper_msa_max_u_df(cpu_env, tdf, twd, tws, twt); break; - case OPC_CLT_U_df: - gen_helper_msa_clt_u_df(cpu_env, tdf, twd, tws, twt); - break; case OPC_ADDS_U_df: gen_helper_msa_adds_u_df(cpu_env, tdf, twd, tws, twt); break; --=20 2.7.4 From nobody Sat May 4 18:23:24 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1569944307; cv=none; d=zoho.com; s=zohoarc; b=EmyOnW43NdU/kCRgwYA9m5fkN7KiEkoQ5vcjBHUoDp+Glx486cczSMLCT2+qJGXO6ka2TQafzl5MEm8UYRb8IAQK+T2TDbRy5pWEBEWhaqdRGBJd8M0cBAJtatFq+Nf9HFq/nIZShUlR4gssmyOJxGKKGShYYXtnTLNyOig+xUc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1569944307; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; 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Tue, 01 Oct 2019 11:17:15 -0400 Received: from mx2.rt-rk.com ([89.216.37.149]:59986 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1iFJtp-0001uv-62 for qemu-devel@nongnu.org; Tue, 01 Oct 2019 11:17:13 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id 6BE8D1A22D5; Tue, 1 Oct 2019 17:15:55 +0200 (CEST) Received: from rtrkw774-lin.domain.local (rtrkw774-lin.domain.local [10.10.13.55]) by mail.rt-rk.com (Postfix) with ESMTPSA id E65501A23A0; Tue, 1 Oct 2019 17:15:54 +0200 (CEST) X-Virus-Scanned: amavisd-new at rt-rk.com From: Aleksandar Markovic To: qemu-devel@nongnu.org Subject: [PULL 15/18] target/mips: msa: Split helpers for DIV_. Date: Tue, 1 Oct 2019 17:15:41 +0200 Message-Id: <1569942944-10381-16-git-send-email-aleksandar.markovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1569942944-10381-1-git-send-email-aleksandar.markovic@rt-rk.com> References: <1569942944-10381-1-git-send-email-aleksandar.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 89.216.37.149 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, amarkovic@wavecomp.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Aleksandar Markovic Achieves clearer code and slightly better performance. Signed-off-by: Aleksandar Markovic Reviewed-by: Aleksandar Rikalo Message-Id: <1569415572-19635-18-git-send-email-aleksandar.markovic@rt-rk.c= om> --- target/mips/helper.h | 12 +++- target/mips/msa_helper.c | 167 +++++++++++++++++++++++++++++++++++++++++--= ---- target/mips/translate.c | 38 +++++++++-- 3 files changed, 190 insertions(+), 27 deletions(-) diff --git a/target/mips/helper.h b/target/mips/helper.h index 29dfcf0..ec4982f 100644 --- a/target/mips/helper.h +++ b/target/mips/helper.h @@ -867,6 +867,16 @@ DEF_HELPER_4(msa_clt_u_h, void, env, i32, i32, i32) DEF_HELPER_4(msa_clt_u_w, void, env, i32, i32, i32) DEF_HELPER_4(msa_clt_u_d, void, env, i32, i32, i32) =20 +DEF_HELPER_4(msa_div_s_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_div_s_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_div_s_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_div_s_d, void, env, i32, i32, i32) + +DEF_HELPER_4(msa_div_u_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_div_u_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_div_u_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_div_u_d, void, env, i32, i32, i32) + =20 DEF_HELPER_4(msa_andi_b, void, env, i32, i32, i32) DEF_HELPER_4(msa_ori_b, void, env, i32, i32, i32) @@ -929,8 +939,6 @@ DEF_HELPER_5(msa_asub_u_df, void, env, i32, i32, i32, i= 32) DEF_HELPER_5(msa_mulv_df, void, env, i32, i32, i32, i32) DEF_HELPER_5(msa_maddv_df, void, env, i32, i32, i32, i32) DEF_HELPER_5(msa_msubv_df, void, env, i32, i32, i32, i32) -DEF_HELPER_5(msa_div_s_df, void, env, i32, i32, i32, i32) -DEF_HELPER_5(msa_div_u_df, void, env, i32, i32, i32, i32) DEF_HELPER_5(msa_mod_s_df, void, env, i32, i32, i32, i32) DEF_HELPER_5(msa_mod_u_df, void, env, i32, i32, i32, i32) DEF_HELPER_5(msa_dotp_s_df, void, env, i32, i32, i32, i32) diff --git a/target/mips/msa_helper.c b/target/mips/msa_helper.c index b658f48..ceccd8f 100644 --- a/target/mips/msa_helper.c +++ b/target/mips/msa_helper.c @@ -1525,7 +1525,154 @@ void helper_msa_clt_u_d(CPUMIPSState *env, * +---------------+------------------------------------------------------= ----+ */ =20 -/* TODO: insert Int Divide group helpers here */ + +static inline int64_t msa_div_s_df(uint32_t df, int64_t arg1, int64_t arg2) +{ + if (arg1 =3D=3D DF_MIN_INT(df) && arg2 =3D=3D -1) { + return DF_MIN_INT(df); + } + return arg2 ? arg1 / arg2 + : arg1 >=3D 0 ? -1 : 1; +} + +void helper_msa_div_s_b(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); + + pwd->b[0] =3D msa_div_s_df(DF_BYTE, pws->b[0], pwt->b[0]); + pwd->b[1] =3D msa_div_s_df(DF_BYTE, pws->b[1], pwt->b[1]); + pwd->b[2] =3D msa_div_s_df(DF_BYTE, pws->b[2], pwt->b[2]); + pwd->b[3] =3D msa_div_s_df(DF_BYTE, pws->b[3], pwt->b[3]); + pwd->b[4] =3D msa_div_s_df(DF_BYTE, pws->b[4], pwt->b[4]); + pwd->b[5] =3D msa_div_s_df(DF_BYTE, pws->b[5], pwt->b[5]); + pwd->b[6] =3D msa_div_s_df(DF_BYTE, pws->b[6], pwt->b[6]); + pwd->b[7] =3D msa_div_s_df(DF_BYTE, pws->b[7], pwt->b[7]); + pwd->b[8] =3D msa_div_s_df(DF_BYTE, pws->b[8], pwt->b[8]); + pwd->b[9] =3D msa_div_s_df(DF_BYTE, pws->b[9], pwt->b[9]); + pwd->b[10] =3D msa_div_s_df(DF_BYTE, pws->b[10], pwt->b[10]); + pwd->b[11] =3D msa_div_s_df(DF_BYTE, pws->b[11], pwt->b[11]); + pwd->b[12] =3D msa_div_s_df(DF_BYTE, pws->b[12], pwt->b[12]); + pwd->b[13] =3D msa_div_s_df(DF_BYTE, pws->b[13], pwt->b[13]); + pwd->b[14] =3D msa_div_s_df(DF_BYTE, pws->b[14], pwt->b[14]); + pwd->b[15] =3D msa_div_s_df(DF_BYTE, pws->b[15], pwt->b[15]); +} + +void helper_msa_div_s_h(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); + + pwd->h[0] =3D msa_div_s_df(DF_HALF, pws->h[0], pwt->h[0]); + pwd->h[1] =3D msa_div_s_df(DF_HALF, pws->h[1], pwt->h[1]); + pwd->h[2] =3D msa_div_s_df(DF_HALF, pws->h[2], pwt->h[2]); + pwd->h[3] =3D msa_div_s_df(DF_HALF, pws->h[3], pwt->h[3]); + pwd->h[4] =3D msa_div_s_df(DF_HALF, pws->h[4], pwt->h[4]); + pwd->h[5] =3D msa_div_s_df(DF_HALF, pws->h[5], pwt->h[5]); + pwd->h[6] =3D msa_div_s_df(DF_HALF, pws->h[6], pwt->h[6]); + pwd->h[7] =3D msa_div_s_df(DF_HALF, pws->h[7], pwt->h[7]); +} + +void helper_msa_div_s_w(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); + + pwd->w[0] =3D msa_div_s_df(DF_WORD, pws->w[0], pwt->w[0]); + pwd->w[1] =3D msa_div_s_df(DF_WORD, pws->w[1], pwt->w[1]); + pwd->w[2] =3D msa_div_s_df(DF_WORD, pws->w[2], pwt->w[2]); + pwd->w[3] =3D msa_div_s_df(DF_WORD, pws->w[3], pwt->w[3]); +} + +void helper_msa_div_s_d(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); + + pwd->d[0] =3D msa_div_s_df(DF_DOUBLE, pws->d[0], pwt->d[0]); + pwd->d[1] =3D msa_div_s_df(DF_DOUBLE, pws->d[1], pwt->d[1]); +} + +static inline int64_t msa_div_u_df(uint32_t df, int64_t arg1, int64_t arg2) +{ + uint64_t u_arg1 =3D UNSIGNED(arg1, df); + uint64_t u_arg2 =3D UNSIGNED(arg2, df); + return arg2 ? u_arg1 / u_arg2 : -1; +} + +void helper_msa_div_u_b(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); + + pwd->b[0] =3D msa_div_u_df(DF_BYTE, pws->b[0], pwt->b[0]); + pwd->b[1] =3D msa_div_u_df(DF_BYTE, pws->b[1], pwt->b[1]); + pwd->b[2] =3D msa_div_u_df(DF_BYTE, pws->b[2], pwt->b[2]); + pwd->b[3] =3D msa_div_u_df(DF_BYTE, pws->b[3], pwt->b[3]); + pwd->b[4] =3D msa_div_u_df(DF_BYTE, pws->b[4], pwt->b[4]); + pwd->b[5] =3D msa_div_u_df(DF_BYTE, pws->b[5], pwt->b[5]); + pwd->b[6] =3D msa_div_u_df(DF_BYTE, pws->b[6], pwt->b[6]); + pwd->b[7] =3D msa_div_u_df(DF_BYTE, pws->b[7], pwt->b[7]); + pwd->b[8] =3D msa_div_u_df(DF_BYTE, pws->b[8], pwt->b[8]); + pwd->b[9] =3D msa_div_u_df(DF_BYTE, pws->b[9], pwt->b[9]); + pwd->b[10] =3D msa_div_u_df(DF_BYTE, pws->b[10], pwt->b[10]); + pwd->b[11] =3D msa_div_u_df(DF_BYTE, pws->b[11], pwt->b[11]); + pwd->b[12] =3D msa_div_u_df(DF_BYTE, pws->b[12], pwt->b[12]); + pwd->b[13] =3D msa_div_u_df(DF_BYTE, pws->b[13], pwt->b[13]); + pwd->b[14] =3D msa_div_u_df(DF_BYTE, pws->b[14], pwt->b[14]); + pwd->b[15] =3D msa_div_u_df(DF_BYTE, pws->b[15], pwt->b[15]); +} + +void helper_msa_div_u_h(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); + + pwd->h[0] =3D msa_div_u_df(DF_HALF, pws->h[0], pwt->h[0]); + pwd->h[1] =3D msa_div_u_df(DF_HALF, pws->h[1], pwt->h[1]); + pwd->h[2] =3D msa_div_u_df(DF_HALF, pws->h[2], pwt->h[2]); + pwd->h[3] =3D msa_div_u_df(DF_HALF, pws->h[3], pwt->h[3]); + pwd->h[4] =3D msa_div_u_df(DF_HALF, pws->h[4], pwt->h[4]); + pwd->h[5] =3D msa_div_u_df(DF_HALF, pws->h[5], pwt->h[5]); + pwd->h[6] =3D msa_div_u_df(DF_HALF, pws->h[6], pwt->h[6]); + pwd->h[7] =3D msa_div_u_df(DF_HALF, pws->h[7], pwt->h[7]); +} + +void helper_msa_div_u_w(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); + + pwd->w[0] =3D msa_div_u_df(DF_WORD, pws->w[0], pwt->w[0]); + pwd->w[1] =3D msa_div_u_df(DF_WORD, pws->w[1], pwt->w[1]); + pwd->w[2] =3D msa_div_u_df(DF_WORD, pws->w[2], pwt->w[2]); + pwd->w[3] =3D msa_div_u_df(DF_WORD, pws->w[3], pwt->w[3]); +} + +void helper_msa_div_u_d(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); + + pwd->d[0] =3D msa_div_u_df(DF_DOUBLE, pws->d[0], pwt->d[0]); + pwd->d[1] =3D msa_div_u_df(DF_DOUBLE, pws->d[1], pwt->d[1]); +} =20 =20 /* @@ -2287,22 +2434,6 @@ static inline int64_t msa_mulv_df(uint32_t df, int64= _t arg1, int64_t arg2) return arg1 * arg2; } =20 -static inline int64_t msa_div_s_df(uint32_t df, int64_t arg1, int64_t arg2) -{ - if (arg1 =3D=3D DF_MIN_INT(df) && arg2 =3D=3D -1) { - return DF_MIN_INT(df); - } - return arg2 ? arg1 / arg2 - : arg1 >=3D 0 ? -1 : 1; -} - -static inline int64_t msa_div_u_df(uint32_t df, int64_t arg1, int64_t arg2) -{ - uint64_t u_arg1 =3D UNSIGNED(arg1, df); - uint64_t u_arg2 =3D UNSIGNED(arg2, df); - return arg2 ? u_arg1 / u_arg2 : -1; -} - static inline int64_t msa_mod_s_df(uint32_t df, int64_t arg1, int64_t arg2) { if (arg1 =3D=3D DF_MIN_INT(df) && arg2 =3D=3D -1) { @@ -2523,8 +2654,6 @@ MSA_BINOP_DF(subsuu_s) MSA_BINOP_DF(asub_s) MSA_BINOP_DF(asub_u) MSA_BINOP_DF(mulv) -MSA_BINOP_DF(div_s) -MSA_BINOP_DF(div_u) MSA_BINOP_DF(mod_s) MSA_BINOP_DF(mod_u) MSA_BINOP_DF(dotp_s) diff --git a/target/mips/translate.c b/target/mips/translate.c index 4db87d6..27eca0a 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -28610,6 +28610,38 @@ static void gen_msa_3r(CPUMIPSState *env, DisasCon= text *ctx) break; } break; + case OPC_DIV_S_df: + switch (df) { + case DF_BYTE: + gen_helper_msa_div_s_b(cpu_env, twd, tws, twt); + break; + case DF_HALF: + gen_helper_msa_div_s_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_div_s_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_div_s_d(cpu_env, twd, tws, twt); + break; + } + break; + case OPC_DIV_U_df: + switch (df) { + case DF_BYTE: + gen_helper_msa_div_u_b(cpu_env, twd, tws, twt); + break; + case DF_HALF: + gen_helper_msa_div_u_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_div_u_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_div_u_d(cpu_env, twd, tws, twt); + break; + } + break; case OPC_SLL_df: gen_helper_msa_sll_df(cpu_env, tdf, twd, tws, twt); break; @@ -28691,9 +28723,6 @@ static void gen_msa_3r(CPUMIPSState *env, DisasCont= ext *ctx) case OPC_ASUB_S_df: gen_helper_msa_asub_s_df(cpu_env, tdf, twd, tws, twt); break; - case OPC_DIV_S_df: - gen_helper_msa_div_s_df(cpu_env, tdf, twd, tws, twt); - break; case OPC_ILVL_df: gen_helper_msa_ilvl_df(cpu_env, tdf, twd, tws, twt); break; @@ -28703,9 +28732,6 @@ static void gen_msa_3r(CPUMIPSState *env, DisasCont= ext *ctx) case OPC_ASUB_U_df: gen_helper_msa_asub_u_df(cpu_env, tdf, twd, tws, twt); break; - case OPC_DIV_U_df: - gen_helper_msa_div_u_df(cpu_env, tdf, twd, tws, twt); - break; case OPC_ILVR_df: gen_helper_msa_ilvr_df(cpu_env, tdf, twd, tws, twt); break; --=20 2.7.4 From nobody Sat May 4 18:23:24 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1569944573; cv=none; d=zoho.com; s=zohoarc; b=TdJd1NNd6WPtVn/tIGRkwI5UvcMor0/DALamGi7cRK5vaxiXbmitm4+UVLHNle1nnVx+DB8+39N2pOHyvWTbvdMqucZrD9lKbYrmX+KFNvBACTiUCSurL2yHT7GbBj7AJEdPS/Svp936KJIL4BdXwmWiXElJj8WEv0lZPb+/Rvc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1569944573; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; 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Tue, 01 Oct 2019 11:17:15 -0400 Received: from mx2.rt-rk.com ([89.216.37.149]:59983 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1iFJtp-0001ug-5g for qemu-devel@nongnu.org; Tue, 01 Oct 2019 11:17:13 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id 4D4231A23C5; Tue, 1 Oct 2019 17:15:55 +0200 (CEST) Received: from rtrkw774-lin.domain.local (rtrkw774-lin.domain.local [10.10.13.55]) by mail.rt-rk.com (Postfix) with ESMTPSA id 0A0E81A23C0; Tue, 1 Oct 2019 17:15:55 +0200 (CEST) X-Virus-Scanned: amavisd-new at rt-rk.com From: Aleksandar Markovic To: qemu-devel@nongnu.org Subject: [PULL 16/18] target/mips: msa: Split helpers for MOD_. Date: Tue, 1 Oct 2019 17:15:42 +0200 Message-Id: <1569942944-10381-17-git-send-email-aleksandar.markovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1569942944-10381-1-git-send-email-aleksandar.markovic@rt-rk.com> References: <1569942944-10381-1-git-send-email-aleksandar.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 89.216.37.149 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, amarkovic@wavecomp.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Aleksandar Markovic Achieves clearer code and slightly better performance. Signed-off-by: Aleksandar Markovic Reviewed-by: Aleksandar Rikalo Message-Id: <1569415572-19635-19-git-send-email-aleksandar.markovic@rt-rk.c= om> --- target/mips/helper.h | 12 +++- target/mips/msa_helper.c | 164 +++++++++++++++++++++++++++++++++++++++++--= ---- target/mips/translate.c | 38 +++++++++-- 3 files changed, 188 insertions(+), 26 deletions(-) diff --git a/target/mips/helper.h b/target/mips/helper.h index ec4982f..cc216f7 100644 --- a/target/mips/helper.h +++ b/target/mips/helper.h @@ -877,6 +877,16 @@ DEF_HELPER_4(msa_div_u_h, void, env, i32, i32, i32) DEF_HELPER_4(msa_div_u_w, void, env, i32, i32, i32) DEF_HELPER_4(msa_div_u_d, void, env, i32, i32, i32) =20 +DEF_HELPER_4(msa_mod_u_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_mod_u_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_mod_u_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_mod_u_d, void, env, i32, i32, i32) + +DEF_HELPER_4(msa_mod_s_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_mod_s_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_mod_s_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_mod_s_d, void, env, i32, i32, i32) + =20 DEF_HELPER_4(msa_andi_b, void, env, i32, i32, i32) DEF_HELPER_4(msa_ori_b, void, env, i32, i32, i32) @@ -939,8 +949,6 @@ DEF_HELPER_5(msa_asub_u_df, void, env, i32, i32, i32, i= 32) DEF_HELPER_5(msa_mulv_df, void, env, i32, i32, i32, i32) DEF_HELPER_5(msa_maddv_df, void, env, i32, i32, i32, i32) DEF_HELPER_5(msa_msubv_df, void, env, i32, i32, i32, i32) -DEF_HELPER_5(msa_mod_s_df, void, env, i32, i32, i32, i32) -DEF_HELPER_5(msa_mod_u_df, void, env, i32, i32, i32, i32) DEF_HELPER_5(msa_dotp_s_df, void, env, i32, i32, i32, i32) DEF_HELPER_5(msa_dotp_u_df, void, env, i32, i32, i32, i32) DEF_HELPER_5(msa_dpadd_s_df, void, env, i32, i32, i32, i32) diff --git a/target/mips/msa_helper.c b/target/mips/msa_helper.c index ceccd8f..04fee66 100644 --- a/target/mips/msa_helper.c +++ b/target/mips/msa_helper.c @@ -1755,7 +1755,152 @@ void helper_msa_div_u_d(CPUMIPSState *env, * +---------------+------------------------------------------------------= ----+ */ =20 -/* TODO: insert Int Modulo group helpers here */ +static inline int64_t msa_mod_s_df(uint32_t df, int64_t arg1, int64_t arg2) +{ + if (arg1 =3D=3D DF_MIN_INT(df) && arg2 =3D=3D -1) { + return 0; + } + return arg2 ? arg1 % arg2 : arg1; +} + +void helper_msa_mod_s_b(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); + + pwd->b[0] =3D msa_mod_s_df(DF_BYTE, pws->b[0], pwt->b[0]); + pwd->b[1] =3D msa_mod_s_df(DF_BYTE, pws->b[1], pwt->b[1]); + pwd->b[2] =3D msa_mod_s_df(DF_BYTE, pws->b[2], pwt->b[2]); + pwd->b[3] =3D msa_mod_s_df(DF_BYTE, pws->b[3], pwt->b[3]); + pwd->b[4] =3D msa_mod_s_df(DF_BYTE, pws->b[4], pwt->b[4]); + pwd->b[5] =3D msa_mod_s_df(DF_BYTE, pws->b[5], pwt->b[5]); + pwd->b[6] =3D msa_mod_s_df(DF_BYTE, pws->b[6], pwt->b[6]); + pwd->b[7] =3D msa_mod_s_df(DF_BYTE, pws->b[7], pwt->b[7]); + pwd->b[8] =3D msa_mod_s_df(DF_BYTE, pws->b[8], pwt->b[8]); + pwd->b[9] =3D msa_mod_s_df(DF_BYTE, pws->b[9], pwt->b[9]); + pwd->b[10] =3D msa_mod_s_df(DF_BYTE, pws->b[10], pwt->b[10]); + pwd->b[11] =3D msa_mod_s_df(DF_BYTE, pws->b[11], pwt->b[11]); + pwd->b[12] =3D msa_mod_s_df(DF_BYTE, pws->b[12], pwt->b[12]); + pwd->b[13] =3D msa_mod_s_df(DF_BYTE, pws->b[13], pwt->b[13]); + pwd->b[14] =3D msa_mod_s_df(DF_BYTE, pws->b[14], pwt->b[14]); + pwd->b[15] =3D msa_mod_s_df(DF_BYTE, pws->b[15], pwt->b[15]); +} + +void helper_msa_mod_s_h(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); + + pwd->h[0] =3D msa_mod_s_df(DF_HALF, pws->h[0], pwt->h[0]); + pwd->h[1] =3D msa_mod_s_df(DF_HALF, pws->h[1], pwt->h[1]); + pwd->h[2] =3D msa_mod_s_df(DF_HALF, pws->h[2], pwt->h[2]); + pwd->h[3] =3D msa_mod_s_df(DF_HALF, pws->h[3], pwt->h[3]); + pwd->h[4] =3D msa_mod_s_df(DF_HALF, pws->h[4], pwt->h[4]); + pwd->h[5] =3D msa_mod_s_df(DF_HALF, pws->h[5], pwt->h[5]); + pwd->h[6] =3D msa_mod_s_df(DF_HALF, pws->h[6], pwt->h[6]); + pwd->h[7] =3D msa_mod_s_df(DF_HALF, pws->h[7], pwt->h[7]); +} + +void helper_msa_mod_s_w(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); + + pwd->w[0] =3D msa_mod_s_df(DF_WORD, pws->w[0], pwt->w[0]); + pwd->w[1] =3D msa_mod_s_df(DF_WORD, pws->w[1], pwt->w[1]); + pwd->w[2] =3D msa_mod_s_df(DF_WORD, pws->w[2], pwt->w[2]); + pwd->w[3] =3D msa_mod_s_df(DF_WORD, pws->w[3], pwt->w[3]); +} + +void helper_msa_mod_s_d(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); + + pwd->d[0] =3D msa_mod_s_df(DF_DOUBLE, pws->d[0], pwt->d[0]); + pwd->d[1] =3D msa_mod_s_df(DF_DOUBLE, pws->d[1], pwt->d[1]); +} + +static inline int64_t msa_mod_u_df(uint32_t df, int64_t arg1, int64_t arg2) +{ + uint64_t u_arg1 =3D UNSIGNED(arg1, df); + uint64_t u_arg2 =3D UNSIGNED(arg2, df); + return u_arg2 ? u_arg1 % u_arg2 : u_arg1; +} + +void helper_msa_mod_u_b(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); + + pwd->b[0] =3D msa_mod_u_df(DF_BYTE, pws->b[0], pwt->b[0]); + pwd->b[1] =3D msa_mod_u_df(DF_BYTE, pws->b[1], pwt->b[1]); + pwd->b[2] =3D msa_mod_u_df(DF_BYTE, pws->b[2], pwt->b[2]); + pwd->b[3] =3D msa_mod_u_df(DF_BYTE, pws->b[3], pwt->b[3]); + pwd->b[4] =3D msa_mod_u_df(DF_BYTE, pws->b[4], pwt->b[4]); + pwd->b[5] =3D msa_mod_u_df(DF_BYTE, pws->b[5], pwt->b[5]); + pwd->b[6] =3D msa_mod_u_df(DF_BYTE, pws->b[6], pwt->b[6]); + pwd->b[7] =3D msa_mod_u_df(DF_BYTE, pws->b[7], pwt->b[7]); + pwd->b[8] =3D msa_mod_u_df(DF_BYTE, pws->b[8], pwt->b[8]); + pwd->b[9] =3D msa_mod_u_df(DF_BYTE, pws->b[9], pwt->b[9]); + pwd->b[10] =3D msa_mod_u_df(DF_BYTE, pws->b[10], pwt->b[10]); + pwd->b[11] =3D msa_mod_u_df(DF_BYTE, pws->b[11], pwt->b[11]); + pwd->b[12] =3D msa_mod_u_df(DF_BYTE, pws->b[12], pwt->b[12]); + pwd->b[13] =3D msa_mod_u_df(DF_BYTE, pws->b[13], pwt->b[13]); + pwd->b[14] =3D msa_mod_u_df(DF_BYTE, pws->b[14], pwt->b[14]); + pwd->b[15] =3D msa_mod_u_df(DF_BYTE, pws->b[15], pwt->b[15]); +} + +void helper_msa_mod_u_h(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); + + pwd->h[0] =3D msa_mod_u_df(DF_HALF, pws->h[0], pwt->h[0]); + pwd->h[1] =3D msa_mod_u_df(DF_HALF, pws->h[1], pwt->h[1]); + pwd->h[2] =3D msa_mod_u_df(DF_HALF, pws->h[2], pwt->h[2]); + pwd->h[3] =3D msa_mod_u_df(DF_HALF, pws->h[3], pwt->h[3]); + pwd->h[4] =3D msa_mod_u_df(DF_HALF, pws->h[4], pwt->h[4]); + pwd->h[5] =3D msa_mod_u_df(DF_HALF, pws->h[5], pwt->h[5]); + pwd->h[6] =3D msa_mod_u_df(DF_HALF, pws->h[6], pwt->h[6]); + pwd->h[7] =3D msa_mod_u_df(DF_HALF, pws->h[7], pwt->h[7]); +} + +void helper_msa_mod_u_w(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); + + pwd->w[0] =3D msa_mod_u_df(DF_WORD, pws->w[0], pwt->w[0]); + pwd->w[1] =3D msa_mod_u_df(DF_WORD, pws->w[1], pwt->w[1]); + pwd->w[2] =3D msa_mod_u_df(DF_WORD, pws->w[2], pwt->w[2]); + pwd->w[3] =3D msa_mod_u_df(DF_WORD, pws->w[3], pwt->w[3]); +} + +void helper_msa_mod_u_d(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); + + pwd->d[0] =3D msa_mod_u_df(DF_DOUBLE, pws->d[0], pwt->d[0]); + pwd->d[1] =3D msa_mod_u_df(DF_DOUBLE, pws->d[1], pwt->d[1]); +} =20 =20 /* @@ -2434,21 +2579,6 @@ static inline int64_t msa_mulv_df(uint32_t df, int64= _t arg1, int64_t arg2) return arg1 * arg2; } =20 -static inline int64_t msa_mod_s_df(uint32_t df, int64_t arg1, int64_t arg2) -{ - if (arg1 =3D=3D DF_MIN_INT(df) && arg2 =3D=3D -1) { - return 0; - } - return arg2 ? arg1 % arg2 : arg1; -} - -static inline int64_t msa_mod_u_df(uint32_t df, int64_t arg1, int64_t arg2) -{ - uint64_t u_arg1 =3D UNSIGNED(arg1, df); - uint64_t u_arg2 =3D UNSIGNED(arg2, df); - return u_arg2 ? u_arg1 % u_arg2 : u_arg1; -} - #define SIGNED_EVEN(a, df) \ ((((int64_t)(a)) << (64 - DF_BITS(df) / 2)) >> (64 - DF_BITS(df) /= 2)) =20 @@ -2654,8 +2784,6 @@ MSA_BINOP_DF(subsuu_s) MSA_BINOP_DF(asub_s) MSA_BINOP_DF(asub_u) MSA_BINOP_DF(mulv) -MSA_BINOP_DF(mod_s) -MSA_BINOP_DF(mod_u) MSA_BINOP_DF(dotp_s) MSA_BINOP_DF(dotp_u) MSA_BINOP_DF(srar) diff --git a/target/mips/translate.c b/target/mips/translate.c index 27eca0a..5039716 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -28642,6 +28642,38 @@ static void gen_msa_3r(CPUMIPSState *env, DisasCon= text *ctx) break; } break; + case OPC_MOD_S_df: + switch (df) { + case DF_BYTE: + gen_helper_msa_mod_s_b(cpu_env, twd, tws, twt); + break; + case DF_HALF: + gen_helper_msa_mod_s_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_mod_s_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_mod_s_d(cpu_env, twd, tws, twt); + break; + } + break; + case OPC_MOD_U_df: + switch (df) { + case DF_BYTE: + gen_helper_msa_mod_u_b(cpu_env, twd, tws, twt); + break; + case DF_HALF: + gen_helper_msa_mod_u_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_mod_u_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_mod_u_d(cpu_env, twd, tws, twt); + break; + } + break; case OPC_SLL_df: gen_helper_msa_sll_df(cpu_env, tdf, twd, tws, twt); break; @@ -28738,18 +28770,12 @@ static void gen_msa_3r(CPUMIPSState *env, DisasCo= ntext *ctx) case OPC_MAX_A_df: gen_helper_msa_max_a_df(cpu_env, tdf, twd, tws, twt); break; - case OPC_MOD_S_df: - gen_helper_msa_mod_s_df(cpu_env, tdf, twd, tws, twt); - break; case OPC_ILVEV_df: gen_helper_msa_ilvev_df(cpu_env, tdf, twd, tws, twt); break; case OPC_MIN_A_df: gen_helper_msa_min_a_df(cpu_env, tdf, twd, tws, twt); break; - case OPC_MOD_U_df: - gen_helper_msa_mod_u_df(cpu_env, tdf, twd, tws, twt); - break; case OPC_ILVOD_df: gen_helper_msa_ilvod_df(cpu_env, tdf, twd, tws, twt); break; --=20 2.7.4 From nobody Sat May 4 18:23:24 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1569943700; cv=none; d=zoho.com; s=zohoarc; b=GI6cf2nOwnHKnXu6vUPhhSLxmJFQKfbX8rbnysD9mc8u+KCoNXxk+h0CU2shC9iMzsy6rs9naO9CKfVRcbSYmGZRvD2l2LMHi8B07vcYggtlQFQFHduAFwRCKqOupYEo8yGNpOHv75okSqU6FYpv2PQ2yg6AGzaUjTW51s2mx1M= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1569943700; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; 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Tue, 01 Oct 2019 11:17:14 -0400 Received: from mx2.rt-rk.com ([89.216.37.149]:59982 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1iFJtp-0001uh-6z for qemu-devel@nongnu.org; Tue, 01 Oct 2019 11:17:13 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id 6348D1A22D0; Tue, 1 Oct 2019 17:15:55 +0200 (CEST) Received: from rtrkw774-lin.domain.local (rtrkw774-lin.domain.local [10.10.13.55]) by mail.rt-rk.com (Postfix) with ESMTPSA id 161F01A239A; Tue, 1 Oct 2019 17:15:55 +0200 (CEST) X-Virus-Scanned: amavisd-new at rt-rk.com From: Aleksandar Markovic To: qemu-devel@nongnu.org Subject: [PULL 17/18] target/mips: msa: Simplify and move helper for MOVE.V Date: Tue, 1 Oct 2019 17:15:43 +0200 Message-Id: <1569942944-10381-18-git-send-email-aleksandar.markovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1569942944-10381-1-git-send-email-aleksandar.markovic@rt-rk.com> References: <1569942944-10381-1-git-send-email-aleksandar.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 89.216.37.149 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, amarkovic@wavecomp.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Aleksandar Markovic Achieves clearer code and slightly better performance. Signed-off-by: Aleksandar Markovic Reviewed-by: Aleksandar Rikalo Message-Id: <1569415572-19635-20-git-send-email-aleksandar.markovic@rt-rk.c= om> --- target/mips/helper.h | 2 +- target/mips/msa_helper.c | 31 +++++++++++++------------------ 2 files changed, 14 insertions(+), 19 deletions(-) diff --git a/target/mips/helper.h b/target/mips/helper.h index cc216f7..3b1a965 100644 --- a/target/mips/helper.h +++ b/target/mips/helper.h @@ -887,6 +887,7 @@ DEF_HELPER_4(msa_mod_s_h, void, env, i32, i32, i32) DEF_HELPER_4(msa_mod_s_w, void, env, i32, i32, i32) DEF_HELPER_4(msa_mod_s_d, void, env, i32, i32, i32) =20 +DEF_HELPER_3(msa_move_v, void, env, i32, i32) =20 DEF_HELPER_4(msa_andi_b, void, env, i32, i32, i32) DEF_HELPER_4(msa_ori_b, void, env, i32, i32, i32) @@ -977,7 +978,6 @@ DEF_HELPER_5(msa_splati_df, void, env, i32, i32, i32, i= 32) DEF_HELPER_5(msa_insve_df, void, env, i32, i32, i32, i32) DEF_HELPER_3(msa_ctcmsa, void, env, tl, i32) DEF_HELPER_2(msa_cfcmsa, tl, env, i32) -DEF_HELPER_3(msa_move_v, void, env, i32, i32) =20 DEF_HELPER_5(msa_fcaf_df, void, env, i32, i32, i32, i32) DEF_HELPER_5(msa_fcun_df, void, env, i32, i32, i32, i32) diff --git a/target/mips/msa_helper.c b/target/mips/msa_helper.c index 04fee66..03b198c 100644 --- a/target/mips/msa_helper.c +++ b/target/mips/msa_helper.c @@ -2022,7 +2022,19 @@ void helper_msa_mod_u_d(CPUMIPSState *env, * +---------------+------------------------------------------------------= ----+ */ =20 -/* TODO: insert Move group helpers here */ +static inline void msa_move_v(wr_t *pwd, wr_t *pws) +{ + pwd->d[0] =3D pws->d[0]; + pwd->d[1] =3D pws->d[1]; +} + +void helper_msa_move_v(CPUMIPSState *env, uint32_t wd, uint32_t ws) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + + msa_move_v(pwd, pws); +} =20 =20 /* @@ -2079,15 +2091,6 @@ void helper_msa_mod_u_d(CPUMIPSState *env, /* TODO: insert Shift group helpers here */ =20 =20 -static inline void msa_move_v(wr_t *pwd, wr_t *pws) -{ - uint32_t i; - - for (i =3D 0; i < DF_ELEMENTS(DF_DOUBLE); i++) { - pwd->d[i] =3D pws->d[i]; - } -} - #define MSA_FN_IMM8(FUNC, DEST, OPERATION) \ void helper_msa_ ## FUNC(CPUMIPSState *env, uint32_t wd, uint32_t ws, \ uint32_t i8) \ @@ -3874,14 +3877,6 @@ target_ulong helper_msa_cfcmsa(CPUMIPSState *env, ui= nt32_t cs) return 0; } =20 -void helper_msa_move_v(CPUMIPSState *env, uint32_t wd, uint32_t ws) -{ - wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); - wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); - - msa_move_v(pwd, pws); -} - void helper_msa_fill_df(CPUMIPSState *env, uint32_t df, uint32_t wd, uint32_t rs) { --=20 2.7.4 From nobody Sat May 4 18:23:24 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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Tue, 01 Oct 2019 11:17:13 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id 691A41A22D4; Tue, 1 Oct 2019 17:15:55 +0200 (CEST) Received: from rtrkw774-lin.domain.local (rtrkw774-lin.domain.local [10.10.13.55]) by mail.rt-rk.com (Postfix) with ESMTPSA id 1EEA61A239D; Tue, 1 Oct 2019 17:15:55 +0200 (CEST) X-Virus-Scanned: amavisd-new at rt-rk.com From: Aleksandar Markovic To: qemu-devel@nongnu.org Subject: [PULL 18/18] target/mips: msa: Move helpers for .V Date: Tue, 1 Oct 2019 17:15:44 +0200 Message-Id: <1569942944-10381-19-git-send-email-aleksandar.markovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1569942944-10381-1-git-send-email-aleksandar.markovic@rt-rk.com> References: <1569942944-10381-1-git-send-email-aleksandar.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 89.216.37.149 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, amarkovic@wavecomp.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Aleksandar Markovic Cosmetic reorganization. Signed-off-by: Aleksandar Markovic Reviewed-by: Aleksandar Rikalo Message-Id: <1569415572-19635-21-git-send-email-aleksandar.markovic@rt-rk.c= om> --- target/mips/helper.h | 9 +++--- target/mips/msa_helper.c | 81 ++++++++++++++++++++++++--------------------= ---- 2 files changed, 45 insertions(+), 45 deletions(-) diff --git a/target/mips/helper.h b/target/mips/helper.h index 3b1a965..d615c83 100644 --- a/target/mips/helper.h +++ b/target/mips/helper.h @@ -887,6 +887,11 @@ DEF_HELPER_4(msa_mod_s_h, void, env, i32, i32, i32) DEF_HELPER_4(msa_mod_s_w, void, env, i32, i32, i32) DEF_HELPER_4(msa_mod_s_d, void, env, i32, i32, i32) =20 +DEF_HELPER_4(msa_and_v, void, env, i32, i32, i32) +DEF_HELPER_4(msa_nor_v, void, env, i32, i32, i32) +DEF_HELPER_4(msa_or_v, void, env, i32, i32, i32) +DEF_HELPER_4(msa_xor_v, void, env, i32, i32, i32) + DEF_HELPER_3(msa_move_v, void, env, i32, i32) =20 DEF_HELPER_4(msa_andi_b, void, env, i32, i32, i32) @@ -1021,10 +1026,6 @@ DEF_HELPER_5(msa_mulr_q_df, void, env, i32, i32, i32= , i32) DEF_HELPER_5(msa_maddr_q_df, void, env, i32, i32, i32, i32) DEF_HELPER_5(msa_msubr_q_df, void, env, i32, i32, i32, i32) =20 -DEF_HELPER_4(msa_and_v, void, env, i32, i32, i32) -DEF_HELPER_4(msa_or_v, void, env, i32, i32, i32) -DEF_HELPER_4(msa_nor_v, void, env, i32, i32, i32) -DEF_HELPER_4(msa_xor_v, void, env, i32, i32, i32) DEF_HELPER_4(msa_fill_df, void, env, i32, i32, i32) =20 DEF_HELPER_4(msa_copy_s_b, void, env, i32, i32, i32) diff --git a/target/mips/msa_helper.c b/target/mips/msa_helper.c index 03b198c..a2052ba 100644 --- a/target/mips/msa_helper.c +++ b/target/mips/msa_helper.c @@ -2010,7 +2010,46 @@ void helper_msa_mod_u_d(CPUMIPSState *env, * +---------------+------------------------------------------------------= ----+ */ =20 -/* TODO: insert Logic group helpers here */ + +void helper_msa_and_v(CPUMIPSState *env, uint32_t wd, uint32_t ws, uint32_= t wt) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); + + pwd->d[0] =3D pws->d[0] & pwt->d[0]; + pwd->d[1] =3D pws->d[1] & pwt->d[1]; +} + +void helper_msa_nor_v(CPUMIPSState *env, uint32_t wd, uint32_t ws, uint32_= t wt) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); + + pwd->d[0] =3D ~(pws->d[0] | pwt->d[0]); + pwd->d[1] =3D ~(pws->d[1] | pwt->d[1]); +} + +void helper_msa_or_v(CPUMIPSState *env, uint32_t wd, uint32_t ws, uint32_t= wt) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); + + pwd->d[0] =3D pws->d[0] | pwt->d[0]; + pwd->d[1] =3D pws->d[1] | pwt->d[1]; +} + +void helper_msa_xor_v(CPUMIPSState *env, uint32_t wd, uint32_t ws, uint32_= t wt) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); + + pwd->d[0] =3D pws->d[0] ^ pwt->d[0]; + pwd->d[1] =3D pws->d[1] ^ pwt->d[1]; +} =20 =20 /* @@ -2160,46 +2199,6 @@ void helper_msa_shf_df(CPUMIPSState *env, uint32_t d= f, uint32_t wd, msa_move_v(pwd, pwx); } =20 -void helper_msa_and_v(CPUMIPSState *env, uint32_t wd, uint32_t ws, uint32_= t wt) -{ - wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); - wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); - wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); - - pwd->d[0] =3D pws->d[0] & pwt->d[0]; - pwd->d[1] =3D pws->d[1] & pwt->d[1]; -} - -void helper_msa_or_v(CPUMIPSState *env, uint32_t wd, uint32_t ws, uint32_t= wt) -{ - wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); - wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); - wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); - - pwd->d[0] =3D pws->d[0] | pwt->d[0]; - pwd->d[1] =3D pws->d[1] | pwt->d[1]; -} - -void helper_msa_nor_v(CPUMIPSState *env, uint32_t wd, uint32_t ws, uint32_= t wt) -{ - wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); - wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); - wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); - - pwd->d[0] =3D ~(pws->d[0] | pwt->d[0]); - pwd->d[1] =3D ~(pws->d[1] | pwt->d[1]); -} - -void helper_msa_xor_v(CPUMIPSState *env, uint32_t wd, uint32_t ws, uint32_= t wt) -{ - wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); - wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); - wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); - - pwd->d[0] =3D pws->d[0] ^ pwt->d[0]; - pwd->d[1] =3D pws->d[1] ^ pwt->d[1]; -} - static inline int64_t msa_addv_df(uint32_t df, int64_t arg1, int64_t arg2) { return arg1 + arg2; --=20 2.7.4