From nobody Wed May 8 07:28:49 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=kernel.org ARC-Seal: i=1; a=rsa-sha256; t=1569457019; cv=none; d=zoho.com; s=zohoarc; b=lEytSgLBr+LUGCuGsKhp6uOaeWwL+hLWAQg/DqELTIl/0dEKuEqYx+ItNqKrttY+7sTCnQYhUfpyEfgLtDgLKW+l40Xpgw6m5hLDUEFaSuUusgDx733wYChvLBhQtK0ogvaMktnAYg0oBrjApQEnKP8xh0/bQsISOlUMGdWanDM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1569457019; h=Cc:Date:From:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:Sender:Subject:To:ARC-Authentication-Results; bh=7OGP5qQ2Uut3YeYbKCZ/xxskn3kUQkMycdIk0sFOqbw=; b=JzBAXIlEJVuStKzuTI/BEzBcReSit06jd2PEi6WE2oAyqBL/djxpfTeYFBYWikaV1Aw0vs+RP+ukLsxHtS83mw1daEL3nWMdKrnRKpw+sZTus4JyHRojQZxo+BM6SEsFAi+/aZFZLU+3G1PsTbtHHHrKhXW/4N2WhtSZNtk4FVc= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1569457019105464.9839826827913; Wed, 25 Sep 2019 17:16:59 -0700 (PDT) Received: from localhost ([::1]:58600 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iDHSa-0001ST-B9 for importer@patchew.org; Wed, 25 Sep 2019 20:16:40 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:47678) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iDHQZ-0000Hn-F7 for qemu-devel@nongnu.org; Wed, 25 Sep 2019 20:14:36 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iDHQX-0000Xs-I5 for qemu-devel@nongnu.org; Wed, 25 Sep 2019 20:14:34 -0400 Received: from mail.kernel.org ([198.145.29.99]:36090) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1iDHQW-0000SS-Il; Wed, 25 Sep 2019 20:14:33 -0400 Received: from guoren-Inspiron-7460.lan (89.208.247.74.16clouds.com [89.208.247.74]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id A0F5720872; Thu, 26 Sep 2019 00:14:25 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1569456868; bh=nkYa3WtRIEfBWb7YBlTFdX/qMHhKMBrRs4NV9j2H004=; h=From:To:Cc:Subject:Date:From; b=xHMkPOtG2yIc0lDPVxtW00HufdmozLXvSm6BWlIGBIThiahFIKVL0oLqGf9cfcZxW 3jmXrHE+DYdJJO8ENtITOukYG/VbMMYxnkpbPmWSI2TqT1DZ06Z3jEuCIu9TBjkwmg O1QMtHK+Kh15+MrCZLkBs+kcPm7/+9o7xpUWcuMo= From: guoren@kernel.org To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH V6] target/riscv: Ignore reserved bits in PTE for RV64 Date: Thu, 26 Sep 2019 08:14:21 +0800 Message-Id: <1569456861-8502-1-git-send-email-guoren@kernel.org> X-Mailer: git-send-email 2.7.4 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 198.145.29.99 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair23@gmail.com, palmer@sifive.com, alistair.francis@wdc.com, Guo Ren , bmeng.cn@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Guo Ren Highest 10 bits of PTE are reserved in riscv-privileged, ref: [1], so we need to ignore them. They cannot be a part of ppn. 1: The RISC-V Instruction Set Manual, Volume II: Privileged Architecture 4.4 Sv39: Page-Based 39-bit Virtual-Memory System 4.5 Sv48: Page-Based 48-bit Virtual-Memory System Signed-off-by: Guo Ren Tested-by: Bin Meng Reviewed-by: Liu Zhiwei Reviewed-by: Bin Meng Reviewed-by: Alistair Francis --- target/riscv/cpu_bits.h | 7 +++++++ target/riscv/cpu_helper.c | 2 +- 2 files changed, 8 insertions(+), 1 deletion(-) Changelog V6: - Add Reviewer: Alistair Francis Changelog V5: - Add Reviewer and Tester: Bin Meng Changelog V4: - Change title to Ignore not Bugfix - Use PTE_PPN_MASK for RV32 and RV64 Changelog V3: - Use UUL define for PTE_RESERVED - Keep ppn >> PTE_PPN_SHIFT Changelog V2: - Bugfix pte destroyed cause boot fail - Change to AND with a mask instead of shifting both directions diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index e998348..399c2c6 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -473,6 +473,13 @@ /* Page table PPN shift amount */ #define PTE_PPN_SHIFT 10 =20 +/* Page table PPN mask */ +#if defined(TARGET_RISCV32) +#define PTE_PPN_MASK 0xffffffffUL +#elif defined(TARGET_RISCV64) +#define PTE_PPN_MASK 0x3fffffffffffffULL +#endif + /* Leaf page shift amount */ #define PGSHIFT 12 =20 diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 87dd6a6..9961b37 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -261,7 +261,7 @@ restart: #elif defined(TARGET_RISCV64) target_ulong pte =3D ldq_phys(cs->as, pte_addr); #endif - hwaddr ppn =3D pte >> PTE_PPN_SHIFT; + hwaddr ppn =3D (pte & PTE_PPN_MASK) >> PTE_PPN_SHIFT; =20 if (!(pte & PTE_V)) { /* Invalid PTE */ --=20 2.7.4