From nobody Wed Nov 12 08:36:18 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1569416050; cv=none; d=zoho.com; s=zohoarc; b=I8mEpOoYb+vsJxFBQ5bGGWDuFpwltxmUU5K9J6pq8lk1jDWUCpaDdIs+HVvLUyffGRT4nWO27BwWfeI0vSlNNKW0EF9F6z8AKZwufXrQCI30hGCjvbDqFl1A3SmIRYefGwoQ2B6TebDFOQlzu31YbVh8aIEQ5XejFR24g5ts2Lw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1569416050; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=zq+vX1LJkl781wAyHDQvON3SoOKagO25cm30LXYjN3M=; b=Bu5XlxysTr8AoFHyoggURxQRb87Op7rxp8CeotkYbL5q4nHGbVjWs8AqhzPGfHbjquDhf6wnbs1Bx1E74A496LSIr2M2+CkFXxWgJyKGBDSo99xSJB/ILkddzXw4uFEvsuWDnJAe2sN26rfv4Zkvs7NLKxoBiCguiJWS/xdl3HE= ARC-Authentication-Results: i=1; mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1569416050992729.1648181847874; Wed, 25 Sep 2019 05:54:10 -0700 (PDT) Received: from localhost ([::1]:49610 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iD6o5-00074v-L0 for importer@patchew.org; Wed, 25 Sep 2019 08:54:09 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:57827) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iD6gd-0001GR-QT for qemu-devel@nongnu.org; Wed, 25 Sep 2019 08:46:30 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iD6gc-0002Eo-1W for qemu-devel@nongnu.org; Wed, 25 Sep 2019 08:46:27 -0400 Received: from mx2.rt-rk.com ([89.216.37.149]:56081 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1iD6gb-0002DE-Js for qemu-devel@nongnu.org; Wed, 25 Sep 2019 08:46:25 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id 88C8F1A23B8; Wed, 25 Sep 2019 14:46:21 +0200 (CEST) Received: from rtrkw774-lin.domain.local (rtrkw774-lin.domain.local [10.10.13.43]) by mail.rt-rk.com (Postfix) with ESMTPSA id 60EDD1A2060; Wed, 25 Sep 2019 14:46:21 +0200 (CEST) X-Virus-Scanned: amavisd-new at rt-rk.com From: Aleksandar Markovic To: qemu-devel@nongnu.org Subject: [PATCH v2 02/20] target/mips: Clean up internal.h Date: Wed, 25 Sep 2019 14:45:54 +0200 Message-Id: <1569415572-19635-3-git-send-email-aleksandar.markovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1569415572-19635-1-git-send-email-aleksandar.markovic@rt-rk.com> References: <1569415572-19635-1-git-send-email-aleksandar.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 89.216.37.149 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: arikalo@wavecomp.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Aleksandar Markovic Mostly fix errors and warnings reported by 'checkpatch.pl -f'. Signed-off-by: Aleksandar Markovic Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/mips/internal.h | 60 +++++++++++++++++++++++++++++++---------------= ---- 1 file changed, 37 insertions(+), 23 deletions(-) diff --git a/target/mips/internal.h b/target/mips/internal.h index 685e8d6..3f435b5 100644 --- a/target/mips/internal.h +++ b/target/mips/internal.h @@ -1,4 +1,5 @@ -/* mips internal definitions and helpers +/* + * MIPS internal definitions and helpers * * This work is licensed under the terms of the GNU GPL, version 2 or late= r. * See the COPYING file in the top-level directory. @@ -9,8 +10,10 @@ =20 #include "fpu/softfloat-helpers.h" =20 -/* MMU types, the first four entries have the same layout as the - CP0C0_MT field. */ +/* + * MMU types, the first four entries have the same layout as the + * CP0C0_MT field. + */ enum mips_mmu_types { MMU_TYPE_NONE, MMU_TYPE_R4000, @@ -160,9 +163,11 @@ static inline bool cpu_mips_hw_interrupts_enabled(CPUM= IPSState *env) !(env->CP0_Status & (1 << CP0St_EXL)) && !(env->CP0_Status & (1 << CP0St_ERL)) && !(env->hflags & MIPS_HFLAG_DM) && - /* Note that the TCStatus IXMT field is initialized to zero, - and only MT capable cores can set it to one. So we don't - need to check for MT capabilities here. */ + /* + * Note that the TCStatus IXMT field is initialized to zero, + * and only MT capable cores can set it to one. So we don't + * need to check for MT capabilities here. + */ !(env->active_tc.CP0_TCStatus & (1 << CP0TCSt_IXMT)); } =20 @@ -177,14 +182,18 @@ static inline bool cpu_mips_hw_interrupts_pending(CPU= MIPSState *env) status =3D env->CP0_Status & CP0Ca_IP_mask; =20 if (env->CP0_Config3 & (1 << CP0C3_VEIC)) { - /* A MIPS configured with a vectorizing external interrupt control= ler - will feed a vector into the Cause pending lines. The core treats - the status lines as a vector level, not as indiviual masks. */ + /* + * A MIPS configured with a vectorizing external interrupt control= ler + * will feed a vector into the Cause pending lines. The core treats + * the status lines as a vector level, not as indiviual masks. + */ r =3D pending > status; } else { - /* A MIPS configured with compatibility or VInt (Vectored Interrup= ts) - treats the pending lines as individual interrupt lines, the sta= tus - lines are individual masks. */ + /* + * A MIPS configured with compatibility or VInt (Vectored Interrup= ts) + * treats the pending lines as individual interrupt lines, the sta= tus + * lines are individual masks. + */ r =3D (pending & status) !=3D 0; } return r; @@ -275,12 +284,14 @@ static inline int mips_vpe_active(CPUMIPSState *env) active =3D 0; } =20 - /* Now verify that there are active thread contexts in the VPE. - - This assumes the CPU model will internally reschedule threads - if the active one goes to sleep. If there are no threads available - the active one will be in a sleeping state, and we can turn off - the entire VPE. */ + /* + * Now verify that there are active thread contexts in the VPE. + * + * This assumes the CPU model will internally reschedule threads + * if the active one goes to sleep. If there are no threads available + * the active one will be in a sleeping state, and we can turn off + * the entire VPE. + */ if (!(env->active_tc.CP0_TCStatus & (1 << CP0TCSt_A))) { /* TC is not activated. */ active =3D 0; @@ -326,7 +337,8 @@ static inline void compute_hflags(CPUMIPSState *env) if (!(env->CP0_Status & (1 << CP0St_EXL)) && !(env->CP0_Status & (1 << CP0St_ERL)) && !(env->hflags & MIPS_HFLAG_DM)) { - env->hflags |=3D (env->CP0_Status >> CP0St_KSU) & MIPS_HFLAG_KSU; + env->hflags |=3D (env->CP0_Status >> CP0St_KSU) & + MIPS_HFLAG_KSU; } #if defined(TARGET_MIPS64) if ((env->insn_flags & ISA_MIPS3) && @@ -403,10 +415,12 @@ static inline void compute_hflags(CPUMIPSState *env) env->hflags |=3D MIPS_HFLAG_COP1X; } } else if (env->insn_flags & ISA_MIPS4) { - /* All supported MIPS IV CPUs use the XX (CU3) to enable - and disable the MIPS IV extensions to the MIPS III ISA. - Some other MIPS IV CPUs ignore the bit, so the check here - would be too restrictive for them. */ + /* + * All supported MIPS IV CPUs use the XX (CU3) to enable + * and disable the MIPS IV extensions to the MIPS III ISA. + * Some other MIPS IV CPUs ignore the bit, so the check here + * would be too restrictive for them. + */ if (env->CP0_Status & (1U << CP0St_CU3)) { env->hflags |=3D MIPS_HFLAG_COP1X; } --=20 2.7.4