From nobody Wed Nov 12 08:37:48 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1569417079; cv=none; d=zoho.com; s=zohoarc; b=RQ15mxOIlfw8Qbf1KZPvuvqsC+jV4ezw2FcR+czXDl1SRAXoTgxaFfFHeErQb3vkXW6iF6hGRlptumfNHUg/wOLX2KXdD8GSTCZ2GSIk/p578lRIeZaRzR8OsBy1g4LpYSsYK4PdXQFQ4+oO7LCTYm7CRVANZSrepxSwPWG9ucQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1569417079; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=4z1HLEKygo+2ZpzdtYDA69I5RMJStbOa/zb/Gx+VwuA=; b=WBC7q80BHHRlD4L5H0u32PDbOHuL5PKrZtW24exAStkfH34IP0pJbXapBASkgdsTX2i1SCB0mD34TV7+RkzohkcVRr7ZCm6VVeH5vpajeoWZpINo6ytBDBchRSSg0emD2zKeqKMvPNfMgWMHys8NCscopHPeAKGno9P2zFjD0P0= ARC-Authentication-Results: i=1; mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1569417079510827.7152689221365; Wed, 25 Sep 2019 06:11:19 -0700 (PDT) Received: from localhost ([::1]:49758 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iD74g-00005o-4C for importer@patchew.org; Wed, 25 Sep 2019 09:11:18 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:58000) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iD6gq-0001Tg-Qd for qemu-devel@nongnu.org; Wed, 25 Sep 2019 08:46:42 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iD6gp-0002ME-5q for qemu-devel@nongnu.org; Wed, 25 Sep 2019 08:46:40 -0400 Received: from mx2.rt-rk.com ([89.216.37.149]:56142 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1iD6go-0002Gn-N0 for qemu-devel@nongnu.org; Wed, 25 Sep 2019 08:46:39 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id 537DA1A23A9; Wed, 25 Sep 2019 14:46:22 +0200 (CEST) Received: from rtrkw774-lin.domain.local (rtrkw774-lin.domain.local [10.10.13.43]) by mail.rt-rk.com (Postfix) with ESMTPSA id 1F4DF1A23E2; Wed, 25 Sep 2019 14:46:22 +0200 (CEST) X-Virus-Scanned: amavisd-new at rt-rk.com From: Aleksandar Markovic To: qemu-devel@nongnu.org Subject: [PATCH v2 20/20] target/mips: msa: Move helpers for .V Date: Wed, 25 Sep 2019 14:46:12 +0200 Message-Id: <1569415572-19635-21-git-send-email-aleksandar.markovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1569415572-19635-1-git-send-email-aleksandar.markovic@rt-rk.com> References: <1569415572-19635-1-git-send-email-aleksandar.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 89.216.37.149 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: arikalo@wavecomp.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Aleksandar Markovic Cosmetic reorganization. Signed-off-by: Aleksandar Markovic --- target/mips/helper.h | 9 +++--- target/mips/msa_helper.c | 81 ++++++++++++++++++++++++--------------------= ---- 2 files changed, 45 insertions(+), 45 deletions(-) diff --git a/target/mips/helper.h b/target/mips/helper.h index 3b1a965..d615c83 100644 --- a/target/mips/helper.h +++ b/target/mips/helper.h @@ -887,6 +887,11 @@ DEF_HELPER_4(msa_mod_s_h, void, env, i32, i32, i32) DEF_HELPER_4(msa_mod_s_w, void, env, i32, i32, i32) DEF_HELPER_4(msa_mod_s_d, void, env, i32, i32, i32) =20 +DEF_HELPER_4(msa_and_v, void, env, i32, i32, i32) +DEF_HELPER_4(msa_nor_v, void, env, i32, i32, i32) +DEF_HELPER_4(msa_or_v, void, env, i32, i32, i32) +DEF_HELPER_4(msa_xor_v, void, env, i32, i32, i32) + DEF_HELPER_3(msa_move_v, void, env, i32, i32) =20 DEF_HELPER_4(msa_andi_b, void, env, i32, i32, i32) @@ -1021,10 +1026,6 @@ DEF_HELPER_5(msa_mulr_q_df, void, env, i32, i32, i32= , i32) DEF_HELPER_5(msa_maddr_q_df, void, env, i32, i32, i32, i32) DEF_HELPER_5(msa_msubr_q_df, void, env, i32, i32, i32, i32) =20 -DEF_HELPER_4(msa_and_v, void, env, i32, i32, i32) -DEF_HELPER_4(msa_or_v, void, env, i32, i32, i32) -DEF_HELPER_4(msa_nor_v, void, env, i32, i32, i32) -DEF_HELPER_4(msa_xor_v, void, env, i32, i32, i32) DEF_HELPER_4(msa_fill_df, void, env, i32, i32, i32) =20 DEF_HELPER_4(msa_copy_s_b, void, env, i32, i32, i32) diff --git a/target/mips/msa_helper.c b/target/mips/msa_helper.c index cece69b..e52d74f 100644 --- a/target/mips/msa_helper.c +++ b/target/mips/msa_helper.c @@ -1962,7 +1962,46 @@ void helper_msa_mod_u_d(CPUMIPSState *env, uint32_t = wd, uint32_t ws, uint32_t wt * +---------------+------------------------------------------------------= ----+ */ =20 -/* TODO: insert Logic group helpers here */ + +void helper_msa_and_v(CPUMIPSState *env, uint32_t wd, uint32_t ws, uint32_= t wt) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); + + pwd->d[0] =3D pws->d[0] & pwt->d[0]; + pwd->d[1] =3D pws->d[1] & pwt->d[1]; +} + +void helper_msa_nor_v(CPUMIPSState *env, uint32_t wd, uint32_t ws, uint32_= t wt) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); + + pwd->d[0] =3D ~(pws->d[0] | pwt->d[0]); + pwd->d[1] =3D ~(pws->d[1] | pwt->d[1]); +} + +void helper_msa_or_v(CPUMIPSState *env, uint32_t wd, uint32_t ws, uint32_t= wt) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); + + pwd->d[0] =3D pws->d[0] | pwt->d[0]; + pwd->d[1] =3D pws->d[1] | pwt->d[1]; +} + +void helper_msa_xor_v(CPUMIPSState *env, uint32_t wd, uint32_t ws, uint32_= t wt) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); + + pwd->d[0] =3D pws->d[0] ^ pwt->d[0]; + pwd->d[1] =3D pws->d[1] ^ pwt->d[1]; +} =20 =20 /* @@ -2112,46 +2151,6 @@ void helper_msa_shf_df(CPUMIPSState *env, uint32_t d= f, uint32_t wd, msa_move_v(pwd, pwx); } =20 -void helper_msa_and_v(CPUMIPSState *env, uint32_t wd, uint32_t ws, uint32_= t wt) -{ - wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); - wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); - wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); - - pwd->d[0] =3D pws->d[0] & pwt->d[0]; - pwd->d[1] =3D pws->d[1] & pwt->d[1]; -} - -void helper_msa_or_v(CPUMIPSState *env, uint32_t wd, uint32_t ws, uint32_t= wt) -{ - wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); - wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); - wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); - - pwd->d[0] =3D pws->d[0] | pwt->d[0]; - pwd->d[1] =3D pws->d[1] | pwt->d[1]; -} - -void helper_msa_nor_v(CPUMIPSState *env, uint32_t wd, uint32_t ws, uint32_= t wt) -{ - wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); - wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); - wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); - - pwd->d[0] =3D ~(pws->d[0] | pwt->d[0]); - pwd->d[1] =3D ~(pws->d[1] | pwt->d[1]); -} - -void helper_msa_xor_v(CPUMIPSState *env, uint32_t wd, uint32_t ws, uint32_= t wt) -{ - wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); - wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); - wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); - - pwd->d[0] =3D pws->d[0] ^ pwt->d[0]; - pwd->d[1] =3D pws->d[1] ^ pwt->d[1]; -} - static inline int64_t msa_addv_df(uint32_t df, int64_t arg1, int64_t arg2) { return arg1 + arg2; --=20 2.7.4