From nobody Wed Nov 12 08:36:17 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1569416857; cv=none; d=zoho.com; s=zohoarc; b=nByIVUNdFymZQ6DRATiL6RzV5MI7elqwuyHfMKjPzi9oJVhDILG4OgEYJYNYSSLSB1cSXypiWWrWNDoeGiF3qA39TRUAfE79PJnlDh8k2UHAs9e8gr2tsKk/I2aLaB0faPFba2kR99ORY3tzJs7xWe+MmEAVyCjd+Eger+Kr3FY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1569416857; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=2ASx1Q72rUzmWJXJli4brZ/au0ZqiYOAHsykfziAhdo=; b=UDFyZkyiaJBOiW1mjOAcXzA5KwIqHYaVPSf/j/pywqiRkwKgjeRbtE9mEu8O4usV3EPakyWyj3K36BHB6ZOSpZtNFIXRYJb1ZBVROkrXAA/y4AEZ8CwpcfRiXW2+izCBZuBbIecci0CunN900v8Kc8pinKWRzZJVOJaleyFILzw= ARC-Authentication-Results: i=1; mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1569416857622129.70705805679006; Wed, 25 Sep 2019 06:07:37 -0700 (PDT) Received: from localhost ([::1]:49720 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iD714-0004RJ-KS for importer@patchew.org; Wed, 25 Sep 2019 09:07:34 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:58021) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iD6gr-0001UN-SK for qemu-devel@nongnu.org; Wed, 25 Sep 2019 08:46:43 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iD6gp-0002M6-3g for qemu-devel@nongnu.org; Wed, 25 Sep 2019 08:46:41 -0400 Received: from mx2.rt-rk.com ([89.216.37.149]:56140 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1iD6go-0002Gi-K5 for qemu-devel@nongnu.org; Wed, 25 Sep 2019 08:46:38 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id 3B5F31A1FFF; Wed, 25 Sep 2019 14:46:22 +0200 (CEST) Received: from rtrkw774-lin.domain.local (rtrkw774-lin.domain.local [10.10.13.43]) by mail.rt-rk.com (Postfix) with ESMTPSA id EF9131A23A9; Wed, 25 Sep 2019 14:46:21 +0200 (CEST) X-Virus-Scanned: amavisd-new at rt-rk.com From: Aleksandar Markovic To: qemu-devel@nongnu.org Subject: [PATCH v2 16/20] target/mips: msa: Split helpers for CLT_. Date: Wed, 25 Sep 2019 14:46:08 +0200 Message-Id: <1569415572-19635-17-git-send-email-aleksandar.markovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1569415572-19635-1-git-send-email-aleksandar.markovic@rt-rk.com> References: <1569415572-19635-1-git-send-email-aleksandar.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 89.216.37.149 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: arikalo@wavecomp.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Aleksandar Markovic Achieves clearer code and slightly better performance. Signed-off-by: Aleksandar Markovic --- target/mips/helper.h | 12 +++- target/mips/msa_helper.c | 150 ++++++++++++++++++++++++++++++++++++++++++-= ---- target/mips/translate.c | 38 ++++++++++-- 3 files changed, 178 insertions(+), 22 deletions(-) diff --git a/target/mips/helper.h b/target/mips/helper.h index 32ff24b..29dfcf0 100644 --- a/target/mips/helper.h +++ b/target/mips/helper.h @@ -857,6 +857,16 @@ DEF_HELPER_4(msa_cle_u_h, void, env, i32, i32, i32) DEF_HELPER_4(msa_cle_u_w, void, env, i32, i32, i32) DEF_HELPER_4(msa_cle_u_d, void, env, i32, i32, i32) =20 +DEF_HELPER_4(msa_clt_s_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_clt_s_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_clt_s_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_clt_s_d, void, env, i32, i32, i32) + +DEF_HELPER_4(msa_clt_u_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_clt_u_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_clt_u_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_clt_u_d, void, env, i32, i32, i32) + =20 DEF_HELPER_4(msa_andi_b, void, env, i32, i32, i32) DEF_HELPER_4(msa_ori_b, void, env, i32, i32, i32) @@ -906,8 +916,6 @@ DEF_HELPER_5(msa_min_s_df, void, env, i32, i32, i32, i3= 2) DEF_HELPER_5(msa_min_u_df, void, env, i32, i32, i32, i32) DEF_HELPER_5(msa_max_a_df, void, env, i32, i32, i32, i32) DEF_HELPER_5(msa_min_a_df, void, env, i32, i32, i32, i32) -DEF_HELPER_5(msa_clt_s_df, void, env, i32, i32, i32, i32) -DEF_HELPER_5(msa_clt_u_df, void, env, i32, i32, i32, i32) DEF_HELPER_5(msa_add_a_df, void, env, i32, i32, i32, i32) DEF_HELPER_5(msa_adds_a_df, void, env, i32, i32, i32, i32) DEF_HELPER_5(msa_adds_s_df, void, env, i32, i32, i32, i32) diff --git a/target/mips/msa_helper.c b/target/mips/msa_helper.c index c4bff76..4cf1a57 100644 --- a/target/mips/msa_helper.c +++ b/target/mips/msa_helper.c @@ -1340,6 +1340,142 @@ void helper_msa_cle_u_d(CPUMIPSState *env, uint32_t= wd, uint32_t ws, uint32_t wt pwd->d[1] =3D msa_cle_u_df(DF_DOUBLE, pws->d[0], pwt->d[1]); } =20 +static inline int64_t msa_clt_s_df(uint32_t df, int64_t arg1, int64_t arg2) +{ + return arg1 < arg2 ? -1 : 0; +} + +void helper_msa_clt_s_b(CPUMIPSState *env, uint32_t wd, uint32_t ws, uint3= 2_t wt) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); + + pwd->b[0] =3D msa_clt_s_df(DF_BYTE, pws->b[0], pwt->b[0]); + pwd->b[1] =3D msa_clt_s_df(DF_BYTE, pws->b[0], pwt->b[1]); + pwd->b[2] =3D msa_clt_s_df(DF_BYTE, pws->b[0], pwt->b[2]); + pwd->b[3] =3D msa_clt_s_df(DF_BYTE, pws->b[0], pwt->b[3]); + pwd->b[4] =3D msa_clt_s_df(DF_BYTE, pws->b[0], pwt->b[4]); + pwd->b[5] =3D msa_clt_s_df(DF_BYTE, pws->b[0], pwt->b[5]); + pwd->b[6] =3D msa_clt_s_df(DF_BYTE, pws->b[0], pwt->b[6]); + pwd->b[7] =3D msa_clt_s_df(DF_BYTE, pws->b[0], pwt->b[7]); + pwd->b[8] =3D msa_clt_s_df(DF_BYTE, pws->b[0], pwt->b[8]); + pwd->b[9] =3D msa_clt_s_df(DF_BYTE, pws->b[0], pwt->b[9]); + pwd->b[10] =3D msa_clt_s_df(DF_BYTE, pws->b[0], pwt->b[10]); + pwd->b[11] =3D msa_clt_s_df(DF_BYTE, pws->b[0], pwt->b[11]); + pwd->b[12] =3D msa_clt_s_df(DF_BYTE, pws->b[0], pwt->b[12]); + pwd->b[13] =3D msa_clt_s_df(DF_BYTE, pws->b[0], pwt->b[13]); + pwd->b[14] =3D msa_clt_s_df(DF_BYTE, pws->b[0], pwt->b[14]); + pwd->b[15] =3D msa_clt_s_df(DF_BYTE, pws->b[0], pwt->b[15]); +} + +void helper_msa_clt_s_h(CPUMIPSState *env, uint32_t wd, uint32_t ws, uint3= 2_t wt) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); + + pwd->h[0] =3D msa_clt_s_df(DF_HALF, pws->h[0], pwt->h[0]); + pwd->h[1] =3D msa_clt_s_df(DF_HALF, pws->h[0], pwt->h[1]); + pwd->h[2] =3D msa_clt_s_df(DF_HALF, pws->h[0], pwt->h[2]); + pwd->h[3] =3D msa_clt_s_df(DF_HALF, pws->h[0], pwt->h[3]); + pwd->h[4] =3D msa_clt_s_df(DF_HALF, pws->h[0], pwt->h[4]); + pwd->h[5] =3D msa_clt_s_df(DF_HALF, pws->h[0], pwt->h[5]); + pwd->h[6] =3D msa_clt_s_df(DF_HALF, pws->h[0], pwt->h[6]); + pwd->h[7] =3D msa_clt_s_df(DF_HALF, pws->h[0], pwt->h[7]); +} + +void helper_msa_clt_s_w(CPUMIPSState *env, uint32_t wd, uint32_t ws, uint3= 2_t wt) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); + + pwd->w[0] =3D msa_clt_s_df(DF_WORD, pws->w[0], pwt->w[0]); + pwd->w[1] =3D msa_clt_s_df(DF_WORD, pws->w[0], pwt->w[1]); + pwd->w[2] =3D msa_clt_s_df(DF_WORD, pws->w[0], pwt->w[2]); + pwd->w[3] =3D msa_clt_s_df(DF_WORD, pws->w[0], pwt->w[3]); +} + +void helper_msa_clt_s_d(CPUMIPSState *env, uint32_t wd, uint32_t ws, uint3= 2_t wt) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); + + pwd->d[0] =3D msa_clt_s_df(DF_DOUBLE, pws->d[0], pwt->d[0]); + pwd->d[1] =3D msa_clt_s_df(DF_DOUBLE, pws->d[0], pwt->d[1]); +} + +static inline int64_t msa_clt_u_df(uint32_t df, int64_t arg1, int64_t arg2) +{ + uint64_t u_arg1 =3D UNSIGNED(arg1, df); + uint64_t u_arg2 =3D UNSIGNED(arg2, df); + return u_arg1 < u_arg2 ? -1 : 0; +} + +void helper_msa_clt_u_b(CPUMIPSState *env, uint32_t wd, uint32_t ws, uint3= 2_t wt) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); + + pwd->b[0] =3D msa_clt_u_df(DF_BYTE, pws->b[0], pwt->b[0]); + pwd->b[1] =3D msa_clt_u_df(DF_BYTE, pws->b[0], pwt->b[1]); + pwd->b[2] =3D msa_clt_u_df(DF_BYTE, pws->b[0], pwt->b[2]); + pwd->b[3] =3D msa_clt_u_df(DF_BYTE, pws->b[0], pwt->b[3]); + pwd->b[4] =3D msa_clt_u_df(DF_BYTE, pws->b[0], pwt->b[4]); + pwd->b[5] =3D msa_clt_u_df(DF_BYTE, pws->b[0], pwt->b[5]); + pwd->b[6] =3D msa_clt_u_df(DF_BYTE, pws->b[0], pwt->b[6]); + pwd->b[7] =3D msa_clt_u_df(DF_BYTE, pws->b[0], pwt->b[7]); + pwd->b[8] =3D msa_clt_u_df(DF_BYTE, pws->b[0], pwt->b[8]); + pwd->b[9] =3D msa_clt_u_df(DF_BYTE, pws->b[0], pwt->b[9]); + pwd->b[10] =3D msa_clt_u_df(DF_BYTE, pws->b[0], pwt->b[10]); + pwd->b[11] =3D msa_clt_u_df(DF_BYTE, pws->b[0], pwt->b[11]); + pwd->b[12] =3D msa_clt_u_df(DF_BYTE, pws->b[0], pwt->b[12]); + pwd->b[13] =3D msa_clt_u_df(DF_BYTE, pws->b[0], pwt->b[13]); + pwd->b[14] =3D msa_clt_u_df(DF_BYTE, pws->b[0], pwt->b[14]); + pwd->b[15] =3D msa_clt_u_df(DF_BYTE, pws->b[0], pwt->b[15]); +} + +void helper_msa_clt_u_h(CPUMIPSState *env, uint32_t wd, uint32_t ws, uint3= 2_t wt) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); + + pwd->h[0] =3D msa_clt_u_df(DF_HALF, pws->h[0], pwt->h[0]); + pwd->h[1] =3D msa_clt_u_df(DF_HALF, pws->h[0], pwt->h[1]); + pwd->h[2] =3D msa_clt_u_df(DF_HALF, pws->h[0], pwt->h[2]); + pwd->h[3] =3D msa_clt_u_df(DF_HALF, pws->h[0], pwt->h[3]); + pwd->h[4] =3D msa_clt_u_df(DF_HALF, pws->h[0], pwt->h[4]); + pwd->h[5] =3D msa_clt_u_df(DF_HALF, pws->h[0], pwt->h[5]); + pwd->h[6] =3D msa_clt_u_df(DF_HALF, pws->h[0], pwt->h[6]); + pwd->h[7] =3D msa_clt_u_df(DF_HALF, pws->h[0], pwt->h[7]); +} + +void helper_msa_clt_u_w(CPUMIPSState *env, uint32_t wd, uint32_t ws, uint3= 2_t wt) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); + + pwd->w[0] =3D msa_clt_u_df(DF_WORD, pws->w[0], pwt->w[0]); + pwd->w[1] =3D msa_clt_u_df(DF_WORD, pws->w[0], pwt->w[1]); + pwd->w[2] =3D msa_clt_u_df(DF_WORD, pws->w[0], pwt->w[2]); + pwd->w[3] =3D msa_clt_u_df(DF_WORD, pws->w[0], pwt->w[3]); +} + +void helper_msa_clt_u_d(CPUMIPSState *env, uint32_t wd, uint32_t ws, uint3= 2_t wt) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); + + pwd->d[0] =3D msa_clt_u_df(DF_DOUBLE, pws->d[0], pwt->d[0]); + pwd->d[1] =3D msa_clt_u_df(DF_DOUBLE, pws->d[0], pwt->d[1]); +} + =20 /* * Int Divide @@ -1747,18 +1883,6 @@ static inline int64_t msa_subv_df(uint32_t df, int64= _t arg1, int64_t arg2) return arg1 - arg2; } =20 -static inline int64_t msa_clt_s_df(uint32_t df, int64_t arg1, int64_t arg2) -{ - return arg1 < arg2 ? -1 : 0; -} - -static inline int64_t msa_clt_u_df(uint32_t df, int64_t arg1, int64_t arg2) -{ - uint64_t u_arg1 =3D UNSIGNED(arg1, df); - uint64_t u_arg2 =3D UNSIGNED(arg2, df); - return u_arg1 < u_arg2 ? -1 : 0; -} - static inline int64_t msa_max_s_df(uint32_t df, int64_t arg1, int64_t arg2) { return arg1 > arg2 ? arg1 : arg2; @@ -2356,8 +2480,6 @@ MSA_BINOP_DF(min_s) MSA_BINOP_DF(min_u) MSA_BINOP_DF(max_a) MSA_BINOP_DF(min_a) -MSA_BINOP_DF(clt_s) -MSA_BINOP_DF(clt_u) MSA_BINOP_DF(add_a) MSA_BINOP_DF(adds_a) MSA_BINOP_DF(adds_s) diff --git a/target/mips/translate.c b/target/mips/translate.c index 614b9e7..4db87d6 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -28578,6 +28578,38 @@ static void gen_msa_3r(CPUMIPSState *env, DisasCon= text *ctx) break; } break; + case OPC_CLT_S_df: + switch (df) { + case DF_BYTE: + gen_helper_msa_clt_s_b(cpu_env, twd, tws, twt); + break; + case DF_HALF: + gen_helper_msa_clt_s_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_clt_s_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_clt_s_d(cpu_env, twd, tws, twt); + break; + } + break; + case OPC_CLT_U_df: + switch (df) { + case DF_BYTE: + gen_helper_msa_clt_u_b(cpu_env, twd, tws, twt); + break; + case DF_HALF: + gen_helper_msa_clt_u_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_clt_u_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_clt_u_d(cpu_env, twd, tws, twt); + break; + } + break; case OPC_SLL_df: gen_helper_msa_sll_df(cpu_env, tdf, twd, tws, twt); break; @@ -28626,9 +28658,6 @@ static void gen_msa_3r(CPUMIPSState *env, DisasCont= ext *ctx) case OPC_MAX_S_df: gen_helper_msa_max_s_df(cpu_env, tdf, twd, tws, twt); break; - case OPC_CLT_S_df: - gen_helper_msa_clt_s_df(cpu_env, tdf, twd, tws, twt); - break; case OPC_ADDS_S_df: gen_helper_msa_adds_s_df(cpu_env, tdf, twd, tws, twt); break; @@ -28647,9 +28676,6 @@ static void gen_msa_3r(CPUMIPSState *env, DisasCont= ext *ctx) case OPC_MAX_U_df: gen_helper_msa_max_u_df(cpu_env, tdf, twd, tws, twt); break; - case OPC_CLT_U_df: - gen_helper_msa_clt_u_df(cpu_env, tdf, twd, tws, twt); - break; case OPC_ADDS_U_df: gen_helper_msa_adds_u_df(cpu_env, tdf, twd, tws, twt); break; --=20 2.7.4