From nobody Wed Nov 12 08:37:48 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1569416064; cv=none; d=zoho.com; s=zohoarc; b=Ztdg4cnHFeEzzqv6FiKiib/vwACVr/jzqr0al5yDllq3LHtDmThcO2iRpLL59X0rqtgPqNhB1iG2GvHyAK7AyUZOjyPJOdw9fb2Kyjjc4SHYrMMu2u8pC8hGAproLRqHRzs8OQG/mx+X608bDR+4z1lISBmDr8waehR3BfZd6Tw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1569416064; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=3fIYPJy82Z68mBWsk88tqd0nQJSEuXtgZ5YSTOZBdQ0=; b=UZCMNorJrlJwkLXQMpUWEvnAS3bpKP8dwlBrijfjMYv2INyUxac+ALI5M1Suac8Ui9SjmyX9XMXbbv4VPWW73RVKCP0yb1qrtyEFvEpFTQdHrktC0EuCwH5tD5HQAsLmqwrT8IeO6MqXMoUYPuN6z2QdAHbTYEsqj0XCd1mCqFM= ARC-Authentication-Results: i=1; mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1569416064378784.3883323500978; Wed, 25 Sep 2019 05:54:24 -0700 (PDT) Received: from localhost ([::1]:49616 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iD6oI-0007Ky-V1 for importer@patchew.org; Wed, 25 Sep 2019 08:54:23 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:57974) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iD6gp-0001S6-FX for qemu-devel@nongnu.org; Wed, 25 Sep 2019 08:46:41 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iD6gn-0002Ks-Gt for qemu-devel@nongnu.org; Wed, 25 Sep 2019 08:46:39 -0400 Received: from mx2.rt-rk.com ([89.216.37.149]:56129 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1iD6gn-0002FQ-5r for qemu-devel@nongnu.org; Wed, 25 Sep 2019 08:46:37 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id 255021A23E1; Wed, 25 Sep 2019 14:46:22 +0200 (CEST) Received: from rtrkw774-lin.domain.local (rtrkw774-lin.domain.local [10.10.13.43]) by mail.rt-rk.com (Postfix) with ESMTPSA id CE8C41A23C3; Wed, 25 Sep 2019 14:46:21 +0200 (CEST) X-Virus-Scanned: amavisd-new at rt-rk.com From: Aleksandar Markovic To: qemu-devel@nongnu.org Subject: [PATCH v2 13/20] target/mips: msa: Split helpers for AVER_. Date: Wed, 25 Sep 2019 14:46:05 +0200 Message-Id: <1569415572-19635-14-git-send-email-aleksandar.markovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1569415572-19635-1-git-send-email-aleksandar.markovic@rt-rk.com> References: <1569415572-19635-1-git-send-email-aleksandar.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 89.216.37.149 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: arikalo@wavecomp.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Aleksandar Markovic Achieves clearer code and slightly better performance. Signed-off-by: Aleksandar Markovic --- target/mips/helper.h | 12 +++- target/mips/msa_helper.c | 154 ++++++++++++++++++++++++++++++++++++++++++-= ---- target/mips/translate.c | 38 ++++++++++-- 3 files changed, 180 insertions(+), 24 deletions(-) diff --git a/target/mips/helper.h b/target/mips/helper.h index 455dd25..9d4c9f1 100644 --- a/target/mips/helper.h +++ b/target/mips/helper.h @@ -832,6 +832,16 @@ DEF_HELPER_4(msa_ave_u_h, void, env, i32, i32, i32) DEF_HELPER_4(msa_ave_u_w, void, env, i32, i32, i32) DEF_HELPER_4(msa_ave_u_d, void, env, i32, i32, i32) =20 +DEF_HELPER_4(msa_aver_s_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_aver_s_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_aver_s_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_aver_s_d, void, env, i32, i32, i32) + +DEF_HELPER_4(msa_aver_u_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_aver_u_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_aver_u_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_aver_u_d, void, env, i32, i32, i32) + =20 DEF_HELPER_4(msa_andi_b, void, env, i32, i32, i32) DEF_HELPER_4(msa_ori_b, void, env, i32, i32, i32) @@ -890,8 +900,6 @@ DEF_HELPER_5(msa_add_a_df, void, env, i32, i32, i32, i3= 2) DEF_HELPER_5(msa_adds_a_df, void, env, i32, i32, i32, i32) DEF_HELPER_5(msa_adds_s_df, void, env, i32, i32, i32, i32) DEF_HELPER_5(msa_adds_u_df, void, env, i32, i32, i32, i32) -DEF_HELPER_5(msa_aver_s_df, void, env, i32, i32, i32, i32) -DEF_HELPER_5(msa_aver_u_df, void, env, i32, i32, i32, i32) DEF_HELPER_5(msa_subs_s_df, void, env, i32, i32, i32, i32) DEF_HELPER_5(msa_subs_u_df, void, env, i32, i32, i32, i32) DEF_HELPER_5(msa_subsus_u_df, void, env, i32, i32, i32, i32) diff --git a/target/mips/msa_helper.c b/target/mips/msa_helper.c index f0dbf24..a4f51c6 100644 --- a/target/mips/msa_helper.c +++ b/target/mips/msa_helper.c @@ -970,6 +970,144 @@ void helper_msa_ave_u_d(CPUMIPSState *env, uint32_t w= d, uint32_t ws, uint32_t wt pwd->d[1] =3D msa_ave_u_df(DF_DOUBLE, pws->d[0], pwt->d[1]); } =20 +static inline int64_t msa_aver_s_df(uint32_t df, int64_t arg1, int64_t arg= 2) +{ + /* signed shift */ + return (arg1 >> 1) + (arg2 >> 1) + ((arg1 | arg2) & 1); +} + +void helper_msa_aver_s_b(CPUMIPSState *env, uint32_t wd, uint32_t ws, uint= 32_t wt) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); + + pwd->b[0] =3D msa_aver_s_df(DF_BYTE, pws->b[0], pwt->b[0]); + pwd->b[1] =3D msa_aver_s_df(DF_BYTE, pws->b[0], pwt->b[1]); + pwd->b[2] =3D msa_aver_s_df(DF_BYTE, pws->b[0], pwt->b[2]); + pwd->b[3] =3D msa_aver_s_df(DF_BYTE, pws->b[0], pwt->b[3]); + pwd->b[4] =3D msa_aver_s_df(DF_BYTE, pws->b[0], pwt->b[4]); + pwd->b[5] =3D msa_aver_s_df(DF_BYTE, pws->b[0], pwt->b[5]); + pwd->b[6] =3D msa_aver_s_df(DF_BYTE, pws->b[0], pwt->b[6]); + pwd->b[7] =3D msa_aver_s_df(DF_BYTE, pws->b[0], pwt->b[7]); + pwd->b[8] =3D msa_aver_s_df(DF_BYTE, pws->b[0], pwt->b[8]); + pwd->b[9] =3D msa_aver_s_df(DF_BYTE, pws->b[0], pwt->b[9]); + pwd->b[10] =3D msa_aver_s_df(DF_BYTE, pws->b[0], pwt->b[10]); + pwd->b[11] =3D msa_aver_s_df(DF_BYTE, pws->b[0], pwt->b[11]); + pwd->b[12] =3D msa_aver_s_df(DF_BYTE, pws->b[0], pwt->b[12]); + pwd->b[13] =3D msa_aver_s_df(DF_BYTE, pws->b[0], pwt->b[13]); + pwd->b[14] =3D msa_aver_s_df(DF_BYTE, pws->b[0], pwt->b[14]); + pwd->b[15] =3D msa_aver_s_df(DF_BYTE, pws->b[0], pwt->b[15]); +} + +void helper_msa_aver_s_h(CPUMIPSState *env, uint32_t wd, uint32_t ws, uint= 32_t wt) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); + + pwd->h[0] =3D msa_aver_s_df(DF_HALF, pws->h[0], pwt->h[0]); + pwd->h[1] =3D msa_aver_s_df(DF_HALF, pws->h[0], pwt->h[1]); + pwd->h[2] =3D msa_aver_s_df(DF_HALF, pws->h[0], pwt->h[2]); + pwd->h[3] =3D msa_aver_s_df(DF_HALF, pws->h[0], pwt->h[3]); + pwd->h[4] =3D msa_aver_s_df(DF_HALF, pws->h[0], pwt->h[4]); + pwd->h[5] =3D msa_aver_s_df(DF_HALF, pws->h[0], pwt->h[5]); + pwd->h[6] =3D msa_aver_s_df(DF_HALF, pws->h[0], pwt->h[6]); + pwd->h[7] =3D msa_aver_s_df(DF_HALF, pws->h[0], pwt->h[7]); +} + +void helper_msa_aver_s_w(CPUMIPSState *env, uint32_t wd, uint32_t ws, uint= 32_t wt) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); + + pwd->w[0] =3D msa_aver_s_df(DF_WORD, pws->w[0], pwt->w[0]); + pwd->w[1] =3D msa_aver_s_df(DF_WORD, pws->w[0], pwt->w[1]); + pwd->w[2] =3D msa_aver_s_df(DF_WORD, pws->w[0], pwt->w[2]); + pwd->w[3] =3D msa_aver_s_df(DF_WORD, pws->w[0], pwt->w[3]); +} + +void helper_msa_aver_s_d(CPUMIPSState *env, uint32_t wd, uint32_t ws, uint= 32_t wt) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); + + pwd->d[0] =3D msa_aver_s_df(DF_DOUBLE, pws->d[0], pwt->d[0]); + pwd->d[1] =3D msa_aver_s_df(DF_DOUBLE, pws->d[0], pwt->d[1]); +} + +static inline uint64_t msa_aver_u_df(uint32_t df, uint64_t arg1, uint64_t = arg2) +{ + uint64_t u_arg1 =3D UNSIGNED(arg1, df); + uint64_t u_arg2 =3D UNSIGNED(arg2, df); + /* unsigned shift */ + return (u_arg1 >> 1) + (u_arg2 >> 1) + ((u_arg1 | u_arg2) & 1); +} + +void helper_msa_aver_u_b(CPUMIPSState *env, uint32_t wd, uint32_t ws, uint= 32_t wt) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); + + pwd->b[0] =3D msa_aver_u_df(DF_BYTE, pws->b[0], pwt->b[0]); + pwd->b[1] =3D msa_aver_u_df(DF_BYTE, pws->b[0], pwt->b[1]); + pwd->b[2] =3D msa_aver_u_df(DF_BYTE, pws->b[0], pwt->b[2]); + pwd->b[3] =3D msa_aver_u_df(DF_BYTE, pws->b[0], pwt->b[3]); + pwd->b[4] =3D msa_aver_u_df(DF_BYTE, pws->b[0], pwt->b[4]); + pwd->b[5] =3D msa_aver_u_df(DF_BYTE, pws->b[0], pwt->b[5]); + pwd->b[6] =3D msa_aver_u_df(DF_BYTE, pws->b[0], pwt->b[6]); + pwd->b[7] =3D msa_aver_u_df(DF_BYTE, pws->b[0], pwt->b[7]); + pwd->b[8] =3D msa_aver_u_df(DF_BYTE, pws->b[0], pwt->b[8]); + pwd->b[9] =3D msa_aver_u_df(DF_BYTE, pws->b[0], pwt->b[9]); + pwd->b[10] =3D msa_aver_u_df(DF_BYTE, pws->b[0], pwt->b[10]); + pwd->b[11] =3D msa_aver_u_df(DF_BYTE, pws->b[0], pwt->b[11]); + pwd->b[12] =3D msa_aver_u_df(DF_BYTE, pws->b[0], pwt->b[12]); + pwd->b[13] =3D msa_aver_u_df(DF_BYTE, pws->b[0], pwt->b[13]); + pwd->b[14] =3D msa_aver_u_df(DF_BYTE, pws->b[0], pwt->b[14]); + pwd->b[15] =3D msa_aver_u_df(DF_BYTE, pws->b[0], pwt->b[15]); +} + +void helper_msa_aver_u_h(CPUMIPSState *env, uint32_t wd, uint32_t ws, uint= 32_t wt) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); + + pwd->h[0] =3D msa_aver_u_df(DF_HALF, pws->h[0], pwt->h[0]); + pwd->h[1] =3D msa_aver_u_df(DF_HALF, pws->h[0], pwt->h[1]); + pwd->h[2] =3D msa_aver_u_df(DF_HALF, pws->h[0], pwt->h[2]); + pwd->h[3] =3D msa_aver_u_df(DF_HALF, pws->h[0], pwt->h[3]); + pwd->h[4] =3D msa_aver_u_df(DF_HALF, pws->h[0], pwt->h[4]); + pwd->h[5] =3D msa_aver_u_df(DF_HALF, pws->h[0], pwt->h[5]); + pwd->h[6] =3D msa_aver_u_df(DF_HALF, pws->h[0], pwt->h[6]); + pwd->h[7] =3D msa_aver_u_df(DF_HALF, pws->h[0], pwt->h[7]); +} + +void helper_msa_aver_u_w(CPUMIPSState *env, uint32_t wd, uint32_t ws, uint= 32_t wt) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); + + pwd->w[0] =3D msa_aver_u_df(DF_WORD, pws->w[0], pwt->w[0]); + pwd->w[1] =3D msa_aver_u_df(DF_WORD, pws->w[0], pwt->w[1]); + pwd->w[2] =3D msa_aver_u_df(DF_WORD, pws->w[0], pwt->w[2]); + pwd->w[3] =3D msa_aver_u_df(DF_WORD, pws->w[0], pwt->w[3]); +} + +void helper_msa_aver_u_d(CPUMIPSState *env, uint32_t wd, uint32_t ws, uint= 32_t wt) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); + + pwd->d[0] =3D msa_aver_u_df(DF_DOUBLE, pws->d[0], pwt->d[0]); + pwd->d[1] =3D msa_aver_u_df(DF_DOUBLE, pws->d[0], pwt->d[1]); +} + =20 /* * Int Compare @@ -1736,20 +1874,6 @@ static inline uint64_t msa_adds_u_df(uint32_t df, ui= nt64_t arg1, uint64_t arg2) return (u_arg1 < max_uint - u_arg2) ? u_arg1 + u_arg2 : max_uint; } =20 -static inline int64_t msa_aver_s_df(uint32_t df, int64_t arg1, int64_t arg= 2) -{ - /* signed shift */ - return (arg1 >> 1) + (arg2 >> 1) + ((arg1 | arg2) & 1); -} - -static inline uint64_t msa_aver_u_df(uint32_t df, uint64_t arg1, uint64_t = arg2) -{ - uint64_t u_arg1 =3D UNSIGNED(arg1, df); - uint64_t u_arg2 =3D UNSIGNED(arg2, df); - /* unsigned shift */ - return (u_arg1 >> 1) + (u_arg2 >> 1) + ((u_arg1 | u_arg2) & 1); -} - static inline int64_t msa_subs_s_df(uint32_t df, int64_t arg1, int64_t arg= 2) { int64_t max_int =3D DF_MAX_INT(df); @@ -2057,8 +2181,6 @@ MSA_BINOP_DF(add_a) MSA_BINOP_DF(adds_a) MSA_BINOP_DF(adds_s) MSA_BINOP_DF(adds_u) -MSA_BINOP_DF(aver_s) -MSA_BINOP_DF(aver_u) MSA_BINOP_DF(subs_s) MSA_BINOP_DF(subs_u) MSA_BINOP_DF(subsus_u) diff --git a/target/mips/translate.c b/target/mips/translate.c index 2b0abbb..9b186d3 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -28498,6 +28498,38 @@ static void gen_msa_3r(CPUMIPSState *env, DisasCon= text *ctx) break; } break; + case OPC_AVER_S_df: + switch (df) { + case DF_BYTE: + gen_helper_msa_aver_s_b(cpu_env, twd, tws, twt); + break; + case DF_HALF: + gen_helper_msa_aver_s_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_aver_s_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_aver_s_d(cpu_env, twd, tws, twt); + break; + } + break; + case OPC_AVER_U_df: + switch (df) { + case DF_BYTE: + gen_helper_msa_aver_u_b(cpu_env, twd, tws, twt); + break; + case DF_HALF: + gen_helper_msa_aver_u_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_aver_u_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_aver_u_d(cpu_env, twd, tws, twt); + break; + } + break; case OPC_SLL_df: gen_helper_msa_sll_df(cpu_env, tdf, twd, tws, twt); break; @@ -28615,9 +28647,6 @@ static void gen_msa_3r(CPUMIPSState *env, DisasCont= ext *ctx) case OPC_MAX_A_df: gen_helper_msa_max_a_df(cpu_env, tdf, twd, tws, twt); break; - case OPC_AVER_S_df: - gen_helper_msa_aver_s_df(cpu_env, tdf, twd, tws, twt); - break; case OPC_MOD_S_df: gen_helper_msa_mod_s_df(cpu_env, tdf, twd, tws, twt); break; @@ -28627,9 +28656,6 @@ static void gen_msa_3r(CPUMIPSState *env, DisasCont= ext *ctx) case OPC_MIN_A_df: gen_helper_msa_min_a_df(cpu_env, tdf, twd, tws, twt); break; - case OPC_AVER_U_df: - gen_helper_msa_aver_u_df(cpu_env, tdf, twd, tws, twt); - break; case OPC_MOD_U_df: gen_helper_msa_mod_u_df(cpu_env, tdf, twd, tws, twt); break; --=20 2.7.4