From nobody Mon Feb 9 23:18:13 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1569335678; cv=none; d=zoho.com; s=zohoarc; b=gMDtcI7UR+MiWbU4LZFxQrxPBntaCz1jsOjN766T3eOru72KLRZ3eV79E9z3IXZ6x3brzyHNU5effw/IHcyMgNJiUTvZxEUERTQuiV64dyTg7wQvkpwSZajCN7k0FsgjHItoe/EjzcXwhLbzYlfJki8EPZQ+wCGd8aV3OOBzsVU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1569335678; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=kVdpV7kojL6abL3Gzj9vFR8bt4yg7A5wl3D6BvZILI0=; b=GCLlYgxTP3WHx7NBeywY/vjywHotufwgnswjV56JvpWFPbgSB6gG/kN5YZVfENxpBzXbzXGknj1vfjOT3vIhBRaZsrqzmWez2+ovfxq91c8Xt9SaUB5bswqKmP/TcZwXzuLLXQ6ERT4g76rOPwMr2/cB0mJaI8sUm60+R/IZr0s= ARC-Authentication-Results: i=1; mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1569335678192465.8129331202464; Tue, 24 Sep 2019 07:34:38 -0700 (PDT) Received: from localhost ([::1]:46386 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iCltk-0002nH-2t for importer@patchew.org; Tue, 24 Sep 2019 10:34:36 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:58545) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iCkrN-0007zC-Pe for qemu-devel@nongnu.org; Tue, 24 Sep 2019 09:28:08 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iCkrK-0001Ey-0r for qemu-devel@nongnu.org; Tue, 24 Sep 2019 09:28:05 -0400 Received: from mx2.rt-rk.com ([89.216.37.149]:46873 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1iCkrG-0001AZ-Uk for qemu-devel@nongnu.org; Tue, 24 Sep 2019 09:28:00 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id CA46F1A22BC; Tue, 24 Sep 2019 15:26:48 +0200 (CEST) Received: from rtrkw774-lin.domain.local (rtrkw774-lin.domain.local [10.10.13.43]) by mail.rt-rk.com (Postfix) with ESMTPSA id 9B7D31A2266; Tue, 24 Sep 2019 15:26:48 +0200 (CEST) X-Virus-Scanned: amavisd-new at rt-rk.com From: Aleksandar Markovic To: qemu-devel@nongnu.org Subject: [PATCH 07/11] target/mips: msa: Split helpers for . Date: Tue, 24 Sep 2019 15:26:38 +0200 Message-Id: <1569331602-2586-8-git-send-email-aleksandar.markovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1569331602-2586-1-git-send-email-aleksandar.markovic@rt-rk.com> References: <1569331602-2586-1-git-send-email-aleksandar.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 89.216.37.149 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: arikalo@wavecomp.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Aleksandar Markovic Achieves clearer code and slightly better performance. Signed-off-by: Aleksandar Markovic --- target/mips/helper.h | 14 +++- target/mips/msa_helper.c | 170 +++++++++++++++++++++++++++++++++++++++----= ---- target/mips/translate.c | 30 ++++++++- 3 files changed, 181 insertions(+), 33 deletions(-) diff --git a/target/mips/helper.h b/target/mips/helper.h index 51f0e1c..d709083 100644 --- a/target/mips/helper.h +++ b/target/mips/helper.h @@ -777,6 +777,18 @@ DEF_HELPER_FLAGS_3(wrdsp, 0, void, tl, tl, env) DEF_HELPER_FLAGS_2(rddsp, 0, tl, tl, env) =20 /* MIPS SIMD Architecture */ + +DEF_HELPER_3(msa_nloc_b, void, env, i32, i32) +DEF_HELPER_3(msa_nloc_h, void, env, i32, i32) +DEF_HELPER_3(msa_nloc_w, void, env, i32, i32) +DEF_HELPER_3(msa_nloc_d, void, env, i32, i32) + +DEF_HELPER_3(msa_nlzc_b, void, env, i32, i32) +DEF_HELPER_3(msa_nlzc_h, void, env, i32, i32) +DEF_HELPER_3(msa_nlzc_w, void, env, i32, i32) +DEF_HELPER_3(msa_nlzc_d, void, env, i32, i32) + + DEF_HELPER_4(msa_andi_b, void, env, i32, i32, i32) DEF_HELPER_4(msa_ori_b, void, env, i32, i32, i32) DEF_HELPER_4(msa_nori_b, void, env, i32, i32, i32) @@ -935,8 +947,6 @@ DEF_HELPER_4(msa_bmz_v, void, env, i32, i32, i32) DEF_HELPER_4(msa_bsel_v, void, env, i32, i32, i32) DEF_HELPER_4(msa_fill_df, void, env, i32, i32, i32) DEF_HELPER_4(msa_pcnt_df, void, env, i32, i32, i32) -DEF_HELPER_4(msa_nloc_df, void, env, i32, i32, i32) -DEF_HELPER_4(msa_nlzc_df, void, env, i32, i32, i32) =20 DEF_HELPER_4(msa_copy_s_b, void, env, i32, i32, i32) DEF_HELPER_4(msa_copy_s_h, void, env, i32, i32, i32) diff --git a/target/mips/msa_helper.c b/target/mips/msa_helper.c index f24061e..8c27c1b 100644 --- a/target/mips/msa_helper.c +++ b/target/mips/msa_helper.c @@ -65,7 +65,147 @@ * +---------------+------------------------------------------------------= ----+ */ =20 -/* TODO: insert Bit Count group helpers here */ +static inline int64_t msa_nlzc_df(uint32_t df, int64_t arg) +{ + uint64_t x, y; + int n, c; + + x =3D UNSIGNED(arg, df); + n =3D DF_BITS(df); + c =3D DF_BITS(df) / 2; + + do { + y =3D x >> c; + if (y !=3D 0) { + n =3D n - c; + x =3D y; + } + c =3D c >> 1; + } while (c !=3D 0); + + return n - x; +} + +static inline int64_t msa_nloc_df(uint32_t df, int64_t arg) +{ + return msa_nlzc_df(df, UNSIGNED((~arg), df)); +} + +void helper_msa_nloc_b(CPUMIPSState *env, uint32_t wd, uint32_t ws) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + + pwd->b[0] =3D msa_nloc_df(DF_BYTE, pws->b[0]); + pwd->b[1] =3D msa_nloc_df(DF_BYTE, pws->b[1]); + pwd->b[2] =3D msa_nloc_df(DF_BYTE, pws->b[2]); + pwd->b[3] =3D msa_nloc_df(DF_BYTE, pws->b[3]); + pwd->b[4] =3D msa_nloc_df(DF_BYTE, pws->b[4]); + pwd->b[5] =3D msa_nloc_df(DF_BYTE, pws->b[5]); + pwd->b[6] =3D msa_nloc_df(DF_BYTE, pws->b[6]); + pwd->b[7] =3D msa_nloc_df(DF_BYTE, pws->b[7]); + pwd->b[8] =3D msa_nloc_df(DF_BYTE, pws->b[8]); + pwd->b[9] =3D msa_nloc_df(DF_BYTE, pws->b[9]); + pwd->b[10] =3D msa_nloc_df(DF_BYTE, pws->b[10]); + pwd->b[11] =3D msa_nloc_df(DF_BYTE, pws->b[11]); + pwd->b[12] =3D msa_nloc_df(DF_BYTE, pws->b[12]); + pwd->b[13] =3D msa_nloc_df(DF_BYTE, pws->b[13]); + pwd->b[14] =3D msa_nloc_df(DF_BYTE, pws->b[14]); + pwd->b[15] =3D msa_nloc_df(DF_BYTE, pws->b[15]); +} + +void helper_msa_nloc_h(CPUMIPSState *env, uint32_t wd, uint32_t ws) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + + pwd->h[0] =3D msa_nloc_df(DF_HALF, pws->h[0]); + pwd->h[1] =3D msa_nloc_df(DF_HALF, pws->h[1]); + pwd->h[2] =3D msa_nloc_df(DF_HALF, pws->h[2]); + pwd->h[3] =3D msa_nloc_df(DF_HALF, pws->h[3]); + pwd->h[4] =3D msa_nloc_df(DF_HALF, pws->h[4]); + pwd->h[5] =3D msa_nloc_df(DF_HALF, pws->h[5]); + pwd->h[6] =3D msa_nloc_df(DF_HALF, pws->h[6]); + pwd->h[7] =3D msa_nloc_df(DF_HALF, pws->h[7]); +} + +void helper_msa_nloc_w(CPUMIPSState *env, uint32_t wd, uint32_t ws) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + + pwd->w[0] =3D msa_nloc_df(DF_WORD, pws->w[0]); + pwd->w[1] =3D msa_nloc_df(DF_WORD, pws->w[1]); + pwd->w[2] =3D msa_nloc_df(DF_WORD, pws->w[2]); + pwd->w[3] =3D msa_nloc_df(DF_WORD, pws->w[3]); +} + +void helper_msa_nloc_d(CPUMIPSState *env, uint32_t wd, uint32_t ws) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + + pwd->d[0] =3D msa_nloc_df(DF_DOUBLE, pws->d[0]); + pwd->d[1] =3D msa_nloc_df(DF_DOUBLE, pws->d[1]); +} + +void helper_msa_nlzc_b(CPUMIPSState *env, uint32_t wd, uint32_t ws) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + + pwd->b[0] =3D msa_nlzc_df(DF_BYTE, pws->b[0]); + pwd->b[1] =3D msa_nlzc_df(DF_BYTE, pws->b[1]); + pwd->b[2] =3D msa_nlzc_df(DF_BYTE, pws->b[2]); + pwd->b[3] =3D msa_nlzc_df(DF_BYTE, pws->b[3]); + pwd->b[4] =3D msa_nlzc_df(DF_BYTE, pws->b[4]); + pwd->b[5] =3D msa_nlzc_df(DF_BYTE, pws->b[5]); + pwd->b[6] =3D msa_nlzc_df(DF_BYTE, pws->b[6]); + pwd->b[7] =3D msa_nlzc_df(DF_BYTE, pws->b[7]); + pwd->b[8] =3D msa_nlzc_df(DF_BYTE, pws->b[8]); + pwd->b[9] =3D msa_nlzc_df(DF_BYTE, pws->b[9]); + pwd->b[10] =3D msa_nlzc_df(DF_BYTE, pws->b[10]); + pwd->b[11] =3D msa_nlzc_df(DF_BYTE, pws->b[11]); + pwd->b[12] =3D msa_nlzc_df(DF_BYTE, pws->b[12]); + pwd->b[13] =3D msa_nlzc_df(DF_BYTE, pws->b[13]); + pwd->b[14] =3D msa_nlzc_df(DF_BYTE, pws->b[14]); + pwd->b[15] =3D msa_nlzc_df(DF_BYTE, pws->b[15]); +} + +void helper_msa_nlzc_h(CPUMIPSState *env, uint32_t wd, uint32_t ws) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + + pwd->h[0] =3D msa_nlzc_df(DF_HALF, pws->h[0]); + pwd->h[1] =3D msa_nlzc_df(DF_HALF, pws->h[1]); + pwd->h[2] =3D msa_nlzc_df(DF_HALF, pws->h[2]); + pwd->h[3] =3D msa_nlzc_df(DF_HALF, pws->h[3]); + pwd->h[4] =3D msa_nlzc_df(DF_HALF, pws->h[4]); + pwd->h[5] =3D msa_nlzc_df(DF_HALF, pws->h[5]); + pwd->h[6] =3D msa_nlzc_df(DF_HALF, pws->h[6]); + pwd->h[7] =3D msa_nlzc_df(DF_HALF, pws->h[7]); +} + +void helper_msa_nlzc_w(CPUMIPSState *env, uint32_t wd, uint32_t ws) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + + pwd->w[0] =3D msa_nlzc_df(DF_WORD, pws->w[0]); + pwd->w[1] =3D msa_nlzc_df(DF_WORD, pws->w[1]); + pwd->w[2] =3D msa_nlzc_df(DF_WORD, pws->w[2]); + pwd->w[3] =3D msa_nlzc_df(DF_WORD, pws->w[3]); +} + +void helper_msa_nlzc_d(CPUMIPSState *env, uint32_t wd, uint32_t ws) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + + pwd->d[0] =3D msa_nlzc_df(DF_DOUBLE, pws->d[0]); + pwd->d[1] =3D msa_nlzc_df(DF_DOUBLE, pws->d[1]); +} =20 =20 /* @@ -2524,32 +2664,6 @@ static inline int64_t msa_pcnt_df(uint32_t df, int64= _t arg) return x; } =20 -static inline int64_t msa_nlzc_df(uint32_t df, int64_t arg) -{ - uint64_t x, y; - int n, c; - - x =3D UNSIGNED(arg, df); - n =3D DF_BITS(df); - c =3D DF_BITS(df) / 2; - - do { - y =3D x >> c; - if (y !=3D 0) { - n =3D n - c; - x =3D y; - } - c =3D c >> 1; - } while (c !=3D 0); - - return n - x; -} - -static inline int64_t msa_nloc_df(uint32_t df, int64_t arg) -{ - return msa_nlzc_df(df, UNSIGNED((~arg), df)); -} - void helper_msa_fill_df(CPUMIPSState *env, uint32_t df, uint32_t wd, uint32_t rs) { @@ -2633,8 +2747,6 @@ void helper_msa_ ## func ## _df(CPUMIPSState *env, ui= nt32_t df, \ } \ } =20 -MSA_UNOP_DF(nlzc) -MSA_UNOP_DF(nloc) MSA_UNOP_DF(pcnt) #undef MSA_UNOP_DF =20 diff --git a/target/mips/translate.c b/target/mips/translate.c index cc5af2a..6de4609 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -28962,10 +28962,36 @@ static void gen_msa_2r(CPUMIPSState *env, DisasCo= ntext *ctx) gen_helper_msa_pcnt_df(cpu_env, tdf, twd, tws); break; case OPC_NLOC_df: - gen_helper_msa_nloc_df(cpu_env, tdf, twd, tws); + switch (df) { + case DF_BYTE: + gen_helper_msa_nloc_b(cpu_env, twd, tws); + break; + case DF_HALF: + gen_helper_msa_nloc_h(cpu_env, twd, tws); + break; + case DF_WORD: + gen_helper_msa_nloc_w(cpu_env, twd, tws); + break; + case DF_DOUBLE: + gen_helper_msa_nloc_d(cpu_env, twd, tws); + break; + } break; case OPC_NLZC_df: - gen_helper_msa_nlzc_df(cpu_env, tdf, twd, tws); + switch (df) { + case DF_BYTE: + gen_helper_msa_nlzc_b(cpu_env, twd, tws); + break; + case DF_HALF: + gen_helper_msa_nlzc_h(cpu_env, twd, tws); + break; + case DF_WORD: + gen_helper_msa_nlzc_w(cpu_env, twd, tws); + break; + case DF_DOUBLE: + gen_helper_msa_nlzc_d(cpu_env, twd, tws); + break; + } break; default: MIPS_INVAL("MSA instruction"); --=20 2.7.4