From nobody Tue Feb 10 00:25:06 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1569334922; cv=none; d=zoho.com; s=zohoarc; b=F9K8YlsOXmv+a6UXa9LLqiWz8yvbLfyPGEMZ1hf7o+ifCo7wHfq7hkjUsp3b6kqk1w/q3iZihKCuuAwC8G7nPLIWj7hPwI68GBkwE32uPGdEh6T5GNr3n0RBy1qr6emT7bZdlYQq4pgtrTxGJhl00h5TQM79I3ZdU+G23/qoVeE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1569334922; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=VpdvxY+zbNwUvyv//THgxnQQAXs1A7gzEuPndQ+NbM0=; b=QH4YgTWwwyzn0EosWhijltYqsf/FpG5z7MWn5h7whBDi8yYUsgsTEoWMQEgqjAilPshRyoQIgXhnse6TTSeCs9kGPfehEoLV+Qz5Z0hJutp2MiU+KkXo2DGxo/DRYpkYVHXV2eYeyciQOFc0KhpbZCzVCncwEgOOaSLUsjNPmAM= ARC-Authentication-Results: i=1; mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1569334922963310.6275264051492; Tue, 24 Sep 2019 07:22:02 -0700 (PDT) Received: from localhost ([::1]:46278 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iClhZ-00079F-EX for importer@patchew.org; Tue, 24 Sep 2019 10:22:01 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:58548) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iCkrN-0007zE-SY for qemu-devel@nongnu.org; Tue, 24 Sep 2019 09:28:08 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iCkrJ-0001Eo-Vx for qemu-devel@nongnu.org; Tue, 24 Sep 2019 09:28:05 -0400 Received: from mx2.rt-rk.com ([89.216.37.149]:46889 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1iCkrG-0001BW-UK for qemu-devel@nongnu.org; Tue, 24 Sep 2019 09:28:00 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id F1E2B1A1D45; Tue, 24 Sep 2019 15:26:48 +0200 (CEST) Received: from rtrkw774-lin.domain.local (rtrkw774-lin.domain.local [10.10.13.43]) by mail.rt-rk.com (Postfix) with ESMTPSA id BF4DC1A2290; Tue, 24 Sep 2019 15:26:48 +0200 (CEST) X-Virus-Scanned: amavisd-new at rt-rk.com From: Aleksandar Markovic To: qemu-devel@nongnu.org Subject: [PATCH 10/11] target/mips: msa: Unroll loops and demacro .V Date: Tue, 24 Sep 2019 15:26:41 +0200 Message-Id: <1569331602-2586-11-git-send-email-aleksandar.markovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1569331602-2586-1-git-send-email-aleksandar.markovic@rt-rk.com> References: <1569331602-2586-1-git-send-email-aleksandar.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 89.216.37.149 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: arikalo@wavecomp.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Aleksandar Markovic Achieves clearer code and slightly better performance. Signed-off-by: Aleksandar Markovic --- target/mips/helper.h | 7 +++--- target/mips/msa_helper.c | 63 ++++++++++++++++++++++++++++++--------------= ---- 2 files changed, 43 insertions(+), 27 deletions(-) diff --git a/target/mips/helper.h b/target/mips/helper.h index 9349482..27544a1 100644 --- a/target/mips/helper.h +++ b/target/mips/helper.h @@ -803,6 +803,10 @@ DEF_HELPER_4(msa_binsr_h, void, env, i32, i32, i32) DEF_HELPER_4(msa_binsr_w, void, env, i32, i32, i32) DEF_HELPER_4(msa_binsr_d, void, env, i32, i32, i32) =20 +DEF_HELPER_4(msa_bmnz_v, void, env, i32, i32, i32) +DEF_HELPER_4(msa_bmz_v, void, env, i32, i32, i32) +DEF_HELPER_4(msa_bsel_v, void, env, i32, i32, i32) + =20 DEF_HELPER_4(msa_andi_b, void, env, i32, i32, i32) DEF_HELPER_4(msa_ori_b, void, env, i32, i32, i32) @@ -957,9 +961,6 @@ DEF_HELPER_4(msa_and_v, void, env, i32, i32, i32) DEF_HELPER_4(msa_or_v, void, env, i32, i32, i32) DEF_HELPER_4(msa_nor_v, void, env, i32, i32, i32) DEF_HELPER_4(msa_xor_v, void, env, i32, i32, i32) -DEF_HELPER_4(msa_bmnz_v, void, env, i32, i32, i32) -DEF_HELPER_4(msa_bmz_v, void, env, i32, i32, i32) -DEF_HELPER_4(msa_bsel_v, void, env, i32, i32, i32) DEF_HELPER_4(msa_fill_df, void, env, i32, i32, i32) =20 DEF_HELPER_4(msa_copy_s_b, void, env, i32, i32, i32) diff --git a/target/mips/msa_helper.c b/target/mips/msa_helper.c index 7c9da99..eda675a 100644 --- a/target/mips/msa_helper.c +++ b/target/mips/msa_helper.c @@ -466,6 +466,42 @@ void helper_msa_binsr_d(CPUMIPSState *env, pwd->d[1] =3D msa_binsr_df(DF_DOUBLE, pwd->d[0], pws->d[0], pwt->d[1= ]); } =20 +void helper_msa_bmnz_v(CPUMIPSState *env, uint32_t wd, uint32_t ws, uint32= _t wt) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); + + pwd->d[0] =3D UNSIGNED( = \ + ((pwd->d[0] & (~pwt->d[0])) | (pws->d[0] & pwt->d[0])), DF_DOUBLE); + pwd->d[1] =3D UNSIGNED( = \ + ((pwd->d[1] & (~pwt->d[1])) | (pws->d[1] & pwt->d[1])), DF_DOUBLE); +} + +void helper_msa_bmz_v(CPUMIPSState *env, uint32_t wd, uint32_t ws, uint32_= t wt) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); + + pwd->d[0] =3D UNSIGNED( = \ + ((pwd->d[0] & pwt->d[0]) | (pws->d[0] & (~pwt->d[0]))), DF_DOUBLE); + pwd->d[1] =3D UNSIGNED( = \ + ((pwd->d[1] & pwt->d[1]) | (pws->d[1] & (~pwt->d[1]))), DF_DOUBLE); +} + +void helper_msa_bsel_v(CPUMIPSState *env, uint32_t wd, uint32_t ws, uint32= _t wt) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); + + pwd->d[0] =3D UNSIGNED( = \ + (pws->d[0] & (~pwd->d[0])) | (pwt->d[0] & pwd->d[0]), DF_DOUBLE); + pwd->d[1] =3D UNSIGNED( = \ + (pws->d[1] & (~pwd->d[1])) | (pwt->d[1] & pwd->d[1]), DF_DOUBLE); +} + =20 /* * Bit Set @@ -946,6 +982,9 @@ MSA_FN_IMM8(bmzi_b, pwd->b[i], MSA_FN_IMM8(bseli_b, pwd->b[i], BIT_SELECT(pwd->b[i], pws->b[i], i8, DF_BYTE)) =20 +#undef BIT_SELECT +#undef BIT_MOVE_IF_ZERO +#undef BIT_MOVE_IF_NOT_ZERO #undef MSA_FN_IMM8 =20 #define SHF_POS(i, imm) (((i) & 0xfc) + (((imm) >> (2 * ((i) & 0x03))) & 0= x03)) @@ -980,30 +1019,6 @@ void helper_msa_shf_df(CPUMIPSState *env, uint32_t df= , uint32_t wd, msa_move_v(pwd, pwx); } =20 -#define MSA_FN_VECTOR(FUNC, DEST, OPERATION) \ -void helper_msa_ ## FUNC(CPUMIPSState *env, uint32_t wd, uint32_t ws, \ - uint32_t wt) \ -{ \ - wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); \ - wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); \ - wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); \ - uint32_t i; \ - for (i =3D 0; i < DF_ELEMENTS(DF_DOUBLE); i++) { \ - DEST =3D OPERATION; \ - } \ -} - -MSA_FN_VECTOR(bmnz_v, pwd->d[i], - BIT_MOVE_IF_NOT_ZERO(pwd->d[i], pws->d[i], pwt->d[i], DF_DOUBLE)) -MSA_FN_VECTOR(bmz_v, pwd->d[i], - BIT_MOVE_IF_ZERO(pwd->d[i], pws->d[i], pwt->d[i], DF_DOUBLE)) -MSA_FN_VECTOR(bsel_v, pwd->d[i], - BIT_SELECT(pwd->d[i], pws->d[i], pwt->d[i], DF_DOUBLE)) -#undef BIT_MOVE_IF_NOT_ZERO -#undef BIT_MOVE_IF_ZERO -#undef BIT_SELECT -#undef MSA_FN_VECTOR - void helper_msa_and_v(CPUMIPSState *env, uint32_t wd, uint32_t ws, uint32_= t wt) { wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); --=20 2.7.4