From nobody Sat May 4 18:24:35 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1569335193; cv=none; d=zoho.com; s=zohoarc; b=Mh9Cklu/aUkUZYWn/Ie34oOfjahYIRnth3C9wbq0lvDo7YWnRKcJG7cKGEdDdJ2KYqWCPhlkpUOh2z4IgfFQKHnisesI15sVlJ82jbYH61TgjPARRI73dyrzBG5pjYKLYWkoZFoBZ7z0NhfClu6i4J03vfsG6vghi6TdcCNX/DQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1569335193; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=KcXXjZiW8KWVCec+LTWHFzmpPdW/dplNwVtI3DOSYDU=; b=JU9GcxoEt987voVB0iuTUpnqc+G+FGGpcuyuzbbzs5q3XJdF/qaYoSv/qSzaK3bObcULclUXVRT4X/72URAq42eOT+W0SV6Z1O81mqTp88IBPkBQmfam462/66OL/OFJMdo6Fjn5Ap2CM8zd/YifC+TVmHNsFWnvVvHk24CMfRU= ARC-Authentication-Results: i=1; mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1569335193035406.7776170063473; Tue, 24 Sep 2019 07:26:33 -0700 (PDT) Received: from localhost ([::1]:46314 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iCllv-0003Y6-28 for importer@patchew.org; Tue, 24 Sep 2019 10:26:31 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:58480) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iCkrH-0007xd-7t for qemu-devel@nongnu.org; Tue, 24 Sep 2019 09:28:01 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iCkrD-0001Af-KF for qemu-devel@nongnu.org; Tue, 24 Sep 2019 09:27:58 -0400 Received: from mx2.rt-rk.com ([89.216.37.149]:34193 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1iCkrC-0000o2-Mh for qemu-devel@nongnu.org; Tue, 24 Sep 2019 09:27:55 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id 76DB91A2267; Tue, 24 Sep 2019 15:26:48 +0200 (CEST) Received: from rtrkw774-lin.domain.local (rtrkw774-lin.domain.local [10.10.13.43]) by mail.rt-rk.com (Postfix) with ESMTPSA id 4E9E41A1E23; Tue, 24 Sep 2019 15:26:48 +0200 (CEST) X-Virus-Scanned: amavisd-new at rt-rk.com From: Aleksandar Markovic To: qemu-devel@nongnu.org Subject: [PATCH 01/11] target/mips: Clean up helper.c Date: Tue, 24 Sep 2019 15:26:32 +0200 Message-Id: <1569331602-2586-2-git-send-email-aleksandar.markovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1569331602-2586-1-git-send-email-aleksandar.markovic@rt-rk.com> References: <1569331602-2586-1-git-send-email-aleksandar.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 89.216.37.149 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: arikalo@wavecomp.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Aleksandar Markovic Mostly fix errors and warnings reported by 'checkpatch.pl -f'. Signed-off-by: Aleksandar Markovic --- target/mips/helper.c | 132 +++++++++++++++++++++++++++++++----------------= ---- 1 file changed, 80 insertions(+), 52 deletions(-) diff --git a/target/mips/helper.c b/target/mips/helper.c index a2b6459..3dd1aae 100644 --- a/target/mips/helper.c +++ b/target/mips/helper.c @@ -39,8 +39,8 @@ enum { #if !defined(CONFIG_USER_ONLY) =20 /* no MMU emulation */ -int no_mmu_map_address (CPUMIPSState *env, hwaddr *physical, int *prot, - target_ulong address, int rw, int access_type) +int no_mmu_map_address(CPUMIPSState *env, hwaddr *physical, int *prot, + target_ulong address, int rw, int access_type) { *physical =3D address; *prot =3D PAGE_READ | PAGE_WRITE | PAGE_EXEC; @@ -48,26 +48,28 @@ int no_mmu_map_address (CPUMIPSState *env, hwaddr *phys= ical, int *prot, } =20 /* fixed mapping MMU emulation */ -int fixed_mmu_map_address (CPUMIPSState *env, hwaddr *physical, int *prot, - target_ulong address, int rw, int access_type) +int fixed_mmu_map_address(CPUMIPSState *env, hwaddr *physical, int *prot, + target_ulong address, int rw, int access_type) { if (address <=3D (int32_t)0x7FFFFFFFUL) { - if (!(env->CP0_Status & (1 << CP0St_ERL))) + if (!(env->CP0_Status & (1 << CP0St_ERL))) { *physical =3D address + 0x40000000UL; - else + } else { *physical =3D address; - } else if (address <=3D (int32_t)0xBFFFFFFFUL) + } + } else if (address <=3D (int32_t)0xBFFFFFFFUL) { *physical =3D address & 0x1FFFFFFF; - else + } else { *physical =3D address; + } =20 *prot =3D PAGE_READ | PAGE_WRITE | PAGE_EXEC; return TLBRET_MATCH; } =20 /* MIPS32/MIPS64 R4000-style MMU emulation */ -int r4k_map_address (CPUMIPSState *env, hwaddr *physical, int *prot, - target_ulong address, int rw, int access_type) +int r4k_map_address(CPUMIPSState *env, hwaddr *physical, int *prot, + target_ulong address, int rw, int access_type) { uint16_t ASID =3D env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask; int i; @@ -99,8 +101,9 @@ int r4k_map_address (CPUMIPSState *env, hwaddr *physical= , int *prot, if (rw !=3D MMU_DATA_STORE || (n ? tlb->D1 : tlb->D0)) { *physical =3D tlb->PFN[n] | (address & (mask >> 1)); *prot =3D PAGE_READ; - if (n ? tlb->D1 : tlb->D0) + if (n ? tlb->D1 : tlb->D0) { *prot |=3D PAGE_WRITE; + } if (!(n ? tlb->XI1 : tlb->XI0)) { *prot |=3D PAGE_EXEC; } @@ -130,8 +133,11 @@ static int is_seg_am_mapped(unsigned int am, bool eu, = int mmu_idx) int32_t adetlb_mask; =20 switch (mmu_idx) { - case 3 /* ERL */: - /* If EU is set, always unmapped */ + case 3: + /* + * ERL + * If EU is set, always unmapped + */ if (eu) { return 0; } @@ -204,9 +210,9 @@ static int get_segctl_physical_address(CPUMIPSState *en= v, hwaddr *physical, pa & ~(hwaddr)segmask); } =20 -static int get_physical_address (CPUMIPSState *env, hwaddr *physical, - int *prot, target_ulong real_address, - int rw, int access_type, int mmu_idx) +static int get_physical_address(CPUMIPSState *env, hwaddr *physical, + int *prot, target_ulong real_address, + int rw, int access_type, int mmu_idx) { /* User mode can only access useg/xuseg */ #if defined(TARGET_MIPS64) @@ -252,14 +258,15 @@ static int get_physical_address (CPUMIPSState *env, h= waddr *physical, } else { segctl =3D env->CP0_SegCtl2 >> 16; } - ret =3D get_segctl_physical_address(env, physical, prot, real_addr= ess, rw, - access_type, mmu_idx, segctl, - 0x3FFFFFFF); + ret =3D get_segctl_physical_address(env, physical, prot, + real_address, rw, access_type, + mmu_idx, segctl, 0x3FFFFFFF); #if defined(TARGET_MIPS64) } else if (address < 0x4000000000000000ULL) { /* xuseg */ if (UX && address <=3D (0x3FFFFFFFFFFFFFFFULL & env->SEGMask)) { - ret =3D env->tlb->map_address(env, physical, prot, real_addres= s, rw, access_type); + ret =3D env->tlb->map_address(env, physical, prot, + real_address, rw, access_type); } else { ret =3D TLBRET_BADADDR; } @@ -267,7 +274,8 @@ static int get_physical_address (CPUMIPSState *env, hwa= ddr *physical, /* xsseg */ if ((supervisor_mode || kernel_mode) && SX && address <=3D (0x7FFFFFFFFFFFFFFFULL & env->SEGMask)) { - ret =3D env->tlb->map_address(env, physical, prot, real_addres= s, rw, access_type); + ret =3D env->tlb->map_address(env, physical, prot, + real_address, rw, access_type); } else { ret =3D TLBRET_BADADDR; } @@ -307,7 +315,8 @@ static int get_physical_address (CPUMIPSState *env, hwa= ddr *physical, /* xkseg */ if (kernel_mode && KX && address <=3D (0xFFFFFFFF7FFFFFFFULL & env->SEGMask)) { - ret =3D env->tlb->map_address(env, physical, prot, real_addres= s, rw, access_type); + ret =3D env->tlb->map_address(env, physical, prot, + real_address, rw, access_type); } else { ret =3D TLBRET_BADADDR; } @@ -328,8 +337,10 @@ static int get_physical_address (CPUMIPSState *env, hw= addr *physical, access_type, mmu_idx, env->CP0_SegCtl0 >> 16, 0x1FFFFF= FF); } else { - /* kseg3 */ - /* XXX: debug segment is not emulated */ + /* + * kseg3 + * XXX: debug segment is not emulated + */ ret =3D get_segctl_physical_address(env, physical, prot, real_addr= ess, rw, access_type, mmu_idx, env->CP0_SegCtl0, 0x1FFFFFFF); @@ -515,9 +526,9 @@ static void raise_mmu_exception(CPUMIPSState *env, targ= et_ulong address, #if defined(TARGET_MIPS64) env->CP0_EntryHi &=3D env->SEGMask; env->CP0_XContext =3D - /* PTEBase */ (env->CP0_XContext & ((~0ULL) << (env->SEGBITS - 7= ))) | - /* R */ (extract64(address, 62, 2) << (env->SEGBITS - 9)) | - /* BadVPN2 */ (extract64(address, 13, env->SEGBITS - 13) << 4); + (env->CP0_XContext & ((~0ULL) << (env->SEGBITS - 7))) | /* PTEBase= */ + (extract64(address, 62, 2) << (env->SEGBITS - 9)) | /* R = */ + (extract64(address, 13, env->SEGBITS - 13) << 4); /* BadVPN2= */ #endif cs->exception_index =3D exception; env->error_code =3D error_code; @@ -945,7 +956,8 @@ bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, int= size, } =20 #ifndef CONFIG_USER_ONLY -hwaddr cpu_mips_translate_address(CPUMIPSState *env, target_ulong address,= int rw) +hwaddr cpu_mips_translate_address(CPUMIPSState *env, target_ulong address, + int rw) { hwaddr physical; int prot; @@ -1005,7 +1017,7 @@ static const char * const excp_names[EXCP_LAST + 1] = =3D { }; #endif =20 -target_ulong exception_resume_pc (CPUMIPSState *env) +target_ulong exception_resume_pc(CPUMIPSState *env) { target_ulong bad_pc; target_ulong isa_mode; @@ -1013,8 +1025,10 @@ target_ulong exception_resume_pc (CPUMIPSState *env) isa_mode =3D !!(env->hflags & MIPS_HFLAG_M16); bad_pc =3D env->active_tc.PC | isa_mode; if (env->hflags & MIPS_HFLAG_BMASK) { - /* If the exception was raised from a delay slot, come back to - the jump. */ + /* + * If the exception was raised from a delay slot, come back to + * the jump. + */ bad_pc -=3D (env->hflags & MIPS_HFLAG_B16 ? 2 : 4); } =20 @@ -1022,14 +1036,14 @@ target_ulong exception_resume_pc (CPUMIPSState *env) } =20 #if !defined(CONFIG_USER_ONLY) -static void set_hflags_for_handler (CPUMIPSState *env) +static void set_hflags_for_handler(CPUMIPSState *env) { /* Exception handlers are entered in 32-bit mode. */ env->hflags &=3D ~(MIPS_HFLAG_M16); /* ...except that microMIPS lets you choose. */ if (env->insn_flags & ASE_MICROMIPS) { - env->hflags |=3D (!!(env->CP0_Config3 - & (1 << CP0C3_ISA_ON_EXC)) + env->hflags |=3D (!!(env->CP0_Config3 & + (1 << CP0C3_ISA_ON_EXC)) << MIPS_HFLAG_M16_SHIFT); } } @@ -1096,10 +1110,12 @@ void mips_cpu_do_interrupt(CPUState *cs) switch (cs->exception_index) { case EXCP_DSS: env->CP0_Debug |=3D 1 << CP0DB_DSS; - /* Debug single step cannot be raised inside a delay slot and - resume will always occur on the next instruction - (but we assume the pc has always been updated during - code translation). */ + /* + * Debug single step cannot be raised inside a delay slot and + * resume will always occur on the next instruction + * (but we assume the pc has always been updated during + * code translation). + */ env->CP0_DEPC =3D env->active_tc.PC | !!(env->hflags & MIPS_HFLAG_= M16); goto enter_debug_mode; case EXCP_DINT: @@ -1111,7 +1127,8 @@ void mips_cpu_do_interrupt(CPUState *cs) case EXCP_DBp: env->CP0_Debug |=3D 1 << CP0DB_DBp; /* Setup DExcCode - SDBBP instruction */ - env->CP0_Debug =3D (env->CP0_Debug & ~(0x1fULL << CP0DB_DEC)) | 9 = << CP0DB_DEC; + env->CP0_Debug =3D (env->CP0_Debug & ~(0x1fULL << CP0DB_DEC)) | + (9 << CP0DB_DEC); goto set_DEPC; case EXCP_DDBS: env->CP0_Debug |=3D 1 << CP0DB_DDBS; @@ -1132,8 +1149,9 @@ void mips_cpu_do_interrupt(CPUState *cs) env->hflags |=3D MIPS_HFLAG_DM | MIPS_HFLAG_CP0; env->hflags &=3D ~(MIPS_HFLAG_KSU); /* EJTAG probe trap enable is not implemented... */ - if (!(env->CP0_Status & (1 << CP0St_EXL))) + if (!(env->CP0_Status & (1 << CP0St_EXL))) { env->CP0_Cause &=3D ~(1U << CP0Ca_BD); + } env->active_tc.PC =3D env->exception_base + 0x480; set_hflags_for_handler(env); break; @@ -1159,8 +1177,9 @@ void mips_cpu_do_interrupt(CPUState *cs) } env->hflags |=3D MIPS_HFLAG_CP0; env->hflags &=3D ~(MIPS_HFLAG_KSU); - if (!(env->CP0_Status & (1 << CP0St_EXL))) + if (!(env->CP0_Status & (1 << CP0St_EXL))) { env->CP0_Cause &=3D ~(1U << CP0Ca_BD); + } env->active_tc.PC =3D env->exception_base; set_hflags_for_handler(env); break; @@ -1176,12 +1195,16 @@ void mips_cpu_do_interrupt(CPUState *cs) uint32_t pending =3D (env->CP0_Cause & CP0Ca_IP_mask) >> C= P0Ca_IP; =20 if (env->CP0_Config3 & (1 << CP0C3_VEIC)) { - /* For VEIC mode, the external interrupt controller fe= eds - * the vector through the CP0Cause IP lines. */ + /* + * For VEIC mode, the external interrupt controller fe= eds + * the vector through the CP0Cause IP lines. + */ vector =3D pending; } else { - /* Vectored Interrupts - * Mask with Status.IM7-IM0 to get enabled interrupts.= */ + /* + * Vectored Interrupts + * Mask with Status.IM7-IM0 to get enabled interrupts. + */ pending &=3D (env->CP0_Status >> CP0St_IM) & 0xff; /* Find the highest-priority interrupt. */ while (pending >>=3D 1) { @@ -1354,7 +1377,8 @@ void mips_cpu_do_interrupt(CPUState *cs) =20 env->active_tc.PC +=3D offset; set_hflags_for_handler(env); - env->CP0_Cause =3D (env->CP0_Cause & ~(0x1f << CP0Ca_EC)) | (cause= << CP0Ca_EC); + env->CP0_Cause =3D (env->CP0_Cause & ~(0x1f << CP0Ca_EC)) | + (cause << CP0Ca_EC); break; default: abort(); @@ -1390,7 +1414,7 @@ bool mips_cpu_exec_interrupt(CPUState *cs, int interr= upt_request) } =20 #if !defined(CONFIG_USER_ONLY) -void r4k_invalidate_tlb (CPUMIPSState *env, int idx, int use_extra) +void r4k_invalidate_tlb(CPUMIPSState *env, int idx, int use_extra) { CPUState *cs =3D env_cpu(env); r4k_tlb_t *tlb; @@ -1400,16 +1424,20 @@ void r4k_invalidate_tlb (CPUMIPSState *env, int idx= , int use_extra) target_ulong mask; =20 tlb =3D &env->tlb->mmu.r4k.tlb[idx]; - /* The qemu TLB is flushed when the ASID changes, so no need to - flush these entries again. */ + /* + * The qemu TLB is flushed when the ASID changes, so no need to + * flush these entries again. + */ if (tlb->G =3D=3D 0 && tlb->ASID !=3D ASID) { return; } =20 if (use_extra && env->tlb->tlb_in_use < MIPS_TLB_MAX) { - /* For tlbwr, we can shadow the discarded entry into - a new (fake) TLB entry, as long as the guest can not - tell that it's there. */ + /* + * For tlbwr, we can shadow the discarded entry into + * a new (fake) TLB entry, as long as the guest can not + * tell that it's there. + */ env->tlb->mmu.r4k.tlb[env->tlb->tlb_in_use] =3D *tlb; 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Tue, 24 Sep 2019 09:27:58 -0400 Received: from mx2.rt-rk.com ([89.216.37.149]:34195 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1iCkrC-0000o3-Ml for qemu-devel@nongnu.org; Tue, 24 Sep 2019 09:27:55 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id 7F6F61A227F; Tue, 24 Sep 2019 15:26:48 +0200 (CEST) Received: from rtrkw774-lin.domain.local (rtrkw774-lin.domain.local [10.10.13.43]) by mail.rt-rk.com (Postfix) with ESMTPSA id 5BAD61A1FB9; Tue, 24 Sep 2019 15:26:48 +0200 (CEST) X-Virus-Scanned: amavisd-new at rt-rk.com From: Aleksandar Markovic To: qemu-devel@nongnu.org Subject: [PATCH 02/11] target/mips: Clean up internal.h Date: Tue, 24 Sep 2019 15:26:33 +0200 Message-Id: <1569331602-2586-3-git-send-email-aleksandar.markovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1569331602-2586-1-git-send-email-aleksandar.markovic@rt-rk.com> References: <1569331602-2586-1-git-send-email-aleksandar.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 89.216.37.149 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: arikalo@wavecomp.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Aleksandar Markovic Mostly fix errors and warnings reported by 'checkpatch.pl -f'. Signed-off-by: Aleksandar Markovic --- target/mips/internal.h | 60 +++++++++++++++++++++++++++++++---------------= ---- 1 file changed, 37 insertions(+), 23 deletions(-) diff --git a/target/mips/internal.h b/target/mips/internal.h index 685e8d6..3f435b5 100644 --- a/target/mips/internal.h +++ b/target/mips/internal.h @@ -1,4 +1,5 @@ -/* mips internal definitions and helpers +/* + * MIPS internal definitions and helpers * * This work is licensed under the terms of the GNU GPL, version 2 or late= r. * See the COPYING file in the top-level directory. @@ -9,8 +10,10 @@ =20 #include "fpu/softfloat-helpers.h" =20 -/* MMU types, the first four entries have the same layout as the - CP0C0_MT field. */ +/* + * MMU types, the first four entries have the same layout as the + * CP0C0_MT field. + */ enum mips_mmu_types { MMU_TYPE_NONE, MMU_TYPE_R4000, @@ -160,9 +163,11 @@ static inline bool cpu_mips_hw_interrupts_enabled(CPUM= IPSState *env) !(env->CP0_Status & (1 << CP0St_EXL)) && !(env->CP0_Status & (1 << CP0St_ERL)) && !(env->hflags & MIPS_HFLAG_DM) && - /* Note that the TCStatus IXMT field is initialized to zero, - and only MT capable cores can set it to one. So we don't - need to check for MT capabilities here. */ + /* + * Note that the TCStatus IXMT field is initialized to zero, + * and only MT capable cores can set it to one. So we don't + * need to check for MT capabilities here. + */ !(env->active_tc.CP0_TCStatus & (1 << CP0TCSt_IXMT)); } =20 @@ -177,14 +182,18 @@ static inline bool cpu_mips_hw_interrupts_pending(CPU= MIPSState *env) status =3D env->CP0_Status & CP0Ca_IP_mask; =20 if (env->CP0_Config3 & (1 << CP0C3_VEIC)) { - /* A MIPS configured with a vectorizing external interrupt control= ler - will feed a vector into the Cause pending lines. The core treats - the status lines as a vector level, not as indiviual masks. */ + /* + * A MIPS configured with a vectorizing external interrupt control= ler + * will feed a vector into the Cause pending lines. The core treats + * the status lines as a vector level, not as indiviual masks. + */ r =3D pending > status; } else { - /* A MIPS configured with compatibility or VInt (Vectored Interrup= ts) - treats the pending lines as individual interrupt lines, the sta= tus - lines are individual masks. */ + /* + * A MIPS configured with compatibility or VInt (Vectored Interrup= ts) + * treats the pending lines as individual interrupt lines, the sta= tus + * lines are individual masks. + */ r =3D (pending & status) !=3D 0; } return r; @@ -275,12 +284,14 @@ static inline int mips_vpe_active(CPUMIPSState *env) active =3D 0; } =20 - /* Now verify that there are active thread contexts in the VPE. - - This assumes the CPU model will internally reschedule threads - if the active one goes to sleep. If there are no threads available - the active one will be in a sleeping state, and we can turn off - the entire VPE. */ + /* + * Now verify that there are active thread contexts in the VPE. + * + * This assumes the CPU model will internally reschedule threads + * if the active one goes to sleep. If there are no threads available + * the active one will be in a sleeping state, and we can turn off + * the entire VPE. + */ if (!(env->active_tc.CP0_TCStatus & (1 << CP0TCSt_A))) { /* TC is not activated. */ active =3D 0; @@ -326,7 +337,8 @@ static inline void compute_hflags(CPUMIPSState *env) if (!(env->CP0_Status & (1 << CP0St_EXL)) && !(env->CP0_Status & (1 << CP0St_ERL)) && !(env->hflags & MIPS_HFLAG_DM)) { - env->hflags |=3D (env->CP0_Status >> CP0St_KSU) & MIPS_HFLAG_KSU; + env->hflags |=3D (env->CP0_Status >> CP0St_KSU) & + MIPS_HFLAG_KSU; } #if defined(TARGET_MIPS64) if ((env->insn_flags & ISA_MIPS3) && @@ -403,10 +415,12 @@ static inline void compute_hflags(CPUMIPSState *env) env->hflags |=3D MIPS_HFLAG_COP1X; } } else if (env->insn_flags & ISA_MIPS4) { - /* All supported MIPS IV CPUs use the XX (CU3) to enable - and disable the MIPS IV extensions to the MIPS III ISA. - Some other MIPS IV CPUs ignore the bit, so the check here - would be too restrictive for them. */ + /* + * All supported MIPS IV CPUs use the XX (CU3) to enable + * and disable the MIPS IV extensions to the MIPS III ISA. + * Some other MIPS IV CPUs ignore the bit, so the check here + * would be too restrictive for them. + */ if (env->CP0_Status & (1U << CP0St_CU3)) { env->hflags |=3D MIPS_HFLAG_COP1X; } --=20 2.7.4 From nobody Sat May 4 18:24:35 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1569334946; cv=none; d=zoho.com; s=zohoarc; b=AZmL5FRVCWq0ThwLIji2PgbRrBmJO7AbWXjcG1SIDmoEpt+mldWAxjaErepyqEpG50UEVwmDPzcYoWAAIsVDbsA3aQgrm6DNGYhQBGsyPNHyKiVOi1WhU/zfQGSCUp3345BKOjrtnsDmn3c+K5t2No61EN2SsY8AJmD73hZICFc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1569334946; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=0KgQvmSCpdTox6PFMPyz/15r35Z2bSYMP0FTJjnGnZs=; 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Tue, 24 Sep 2019 09:27:58 -0400 Received: from mx2.rt-rk.com ([89.216.37.149]:34207 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1iCkrC-0000o6-LK for qemu-devel@nongnu.org; Tue, 24 Sep 2019 09:27:55 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id 8D4991A1E23; Tue, 24 Sep 2019 15:26:48 +0200 (CEST) Received: from rtrkw774-lin.domain.local (rtrkw774-lin.domain.local [10.10.13.43]) by mail.rt-rk.com (Postfix) with ESMTPSA id 63F431A221B; Tue, 24 Sep 2019 15:26:48 +0200 (CEST) X-Virus-Scanned: amavisd-new at rt-rk.com From: Aleksandar Markovic To: qemu-devel@nongnu.org Subject: [PATCH 03/11] target/mips: Clean up kvm_mips.h Date: Tue, 24 Sep 2019 15:26:34 +0200 Message-Id: <1569331602-2586-4-git-send-email-aleksandar.markovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1569331602-2586-1-git-send-email-aleksandar.markovic@rt-rk.com> References: <1569331602-2586-1-git-send-email-aleksandar.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 89.216.37.149 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: arikalo@wavecomp.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Aleksandar Markovic Mostly fix errors and warnings reported by 'checkpatch.pl -f'. Signed-off-by: Aleksandar Markovic --- target/mips/kvm_mips.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/mips/kvm_mips.h b/target/mips/kvm_mips.h index ae957f3..1e40147 100644 --- a/target/mips/kvm_mips.h +++ b/target/mips/kvm_mips.h @@ -7,7 +7,7 @@ * * Copyright (C) 2012-2014 Imagination Technologies Ltd. * Authors: Sanjay Lal -*/ + */ =20 #ifndef KVM_MIPS_H #define KVM_MIPS_H --=20 2.7.4 From nobody Sat May 4 18:24:35 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1569334609; cv=none; d=zoho.com; s=zohoarc; b=K8i+1f/GgmJP9us0NgjsLyYx76uifWEaWqJdTpHQnHAb+xiqzMUVKNkW9kMcF9lH/u+SDSss9RJrPKKpgvdeUQya7JfSf2UER/vKjOt1RFSqjQbgxQ/B8WF9WtjGnd6aoYqr3YwIB0Bjt0/s/OvhYd0b1dHu4LuYrhNMTsU4W3s= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1569334609; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=qFaCJx8tbrhRj0nOJAgsjXV9kkHEC27ObknN9L3cGBc=; b=Mq9NrHLyEURsBr73UvYMSZs7vGajfaN9bWvjMhYQGGRe7/CCtn+fY7aTUKEMTOv9CyoBDn6blBK1TWHhp/3nmow0aG7YPkW3f42/wHGW6FEU1iws2HeVAjsxYY8ifY9h5HMPCHXYh/XO0O2hNpNcnWk8Hjp1RqcjVVY6zJi4rUM= ARC-Authentication-Results: i=1; mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1569334609654576.3554255392079; Tue, 24 Sep 2019 07:16:49 -0700 (PDT) Received: from localhost ([::1]:46230 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iClcT-0002SU-En for importer@patchew.org; Tue, 24 Sep 2019 10:16:45 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:58482) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iCkrH-0007xf-JK for qemu-devel@nongnu.org; Tue, 24 Sep 2019 09:28:01 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iCkrD-0001Av-O0 for qemu-devel@nongnu.org; Tue, 24 Sep 2019 09:27:58 -0400 Received: from mx2.rt-rk.com ([89.216.37.149]:34213 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1iCkrC-0000o9-Js for qemu-devel@nongnu.org; Tue, 24 Sep 2019 09:27:55 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id 980B21A2251; Tue, 24 Sep 2019 15:26:48 +0200 (CEST) Received: from rtrkw774-lin.domain.local (rtrkw774-lin.domain.local [10.10.13.43]) by mail.rt-rk.com (Postfix) with ESMTPSA id 698161A1D45; Tue, 24 Sep 2019 15:26:48 +0200 (CEST) X-Virus-Scanned: amavisd-new at rt-rk.com From: Aleksandar Markovic To: qemu-devel@nongnu.org Subject: [PATCH 04/11] target/mips: Clean up mips-defs.h Date: Tue, 24 Sep 2019 15:26:35 +0200 Message-Id: <1569331602-2586-5-git-send-email-aleksandar.markovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1569331602-2586-1-git-send-email-aleksandar.markovic@rt-rk.com> References: <1569331602-2586-1-git-send-email-aleksandar.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 89.216.37.149 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: arikalo@wavecomp.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Aleksandar Markovic Mostly fix errors and warnings reported by 'checkpatch.pl -f'. Signed-off-by: Aleksandar Markovic --- target/mips/mips-defs.h | 53 ++++++++++++++++++++++++++-------------------= ---- 1 file changed, 28 insertions(+), 25 deletions(-) diff --git a/target/mips/mips-defs.h b/target/mips/mips-defs.h index bbf056a..938c0de 100644 --- a/target/mips/mips-defs.h +++ b/target/mips/mips-defs.h @@ -2,7 +2,7 @@ #define QEMU_MIPS_DEFS_H =20 /* If we want to use host float regs... */ -//#define USE_HOST_FLOAT_REGS +/* #define USE_HOST_FLOAT_REGS */ =20 /* Real pages are variable size... */ #define MIPS_TLB_MAX 128 @@ -57,43 +57,46 @@ #define ASE_MXU 0x0200000000000000ULL =20 /* MIPS CPU defines. */ -#define CPU_MIPS1 (ISA_MIPS1) -#define CPU_MIPS2 (CPU_MIPS1 | ISA_MIPS2) -#define CPU_MIPS3 (CPU_MIPS2 | ISA_MIPS3) -#define CPU_MIPS4 (CPU_MIPS3 | ISA_MIPS4) -#define CPU_VR54XX (CPU_MIPS4 | INSN_VR54XX) -#define CPU_R5900 (CPU_MIPS3 | INSN_R5900) -#define CPU_LOONGSON2E (CPU_MIPS3 | INSN_LOONGSON2E) -#define CPU_LOONGSON2F (CPU_MIPS3 | INSN_LOONGSON2F) +#define CPU_MIPS1 (ISA_MIPS1) +#define CPU_MIPS2 (CPU_MIPS1 | ISA_MIPS2) +#define CPU_MIPS3 (CPU_MIPS2 | ISA_MIPS3) +#define CPU_MIPS4 (CPU_MIPS3 | ISA_MIPS4) +#define CPU_VR54XX (CPU_MIPS4 | INSN_VR54XX) +#define CPU_R5900 (CPU_MIPS3 | INSN_R5900) +#define CPU_LOONGSON2E (CPU_MIPS3 | INSN_LOONGSON2E) +#define CPU_LOONGSON2F (CPU_MIPS3 | INSN_LOONGSON2F) =20 -#define CPU_MIPS5 (CPU_MIPS4 | ISA_MIPS5) +#define CPU_MIPS5 (CPU_MIPS4 | ISA_MIPS5) =20 /* MIPS Technologies "Release 1" */ -#define CPU_MIPS32 (CPU_MIPS2 | ISA_MIPS32) -#define CPU_MIPS64 (CPU_MIPS5 | CPU_MIPS32 | ISA_MIPS64) +#define CPU_MIPS32 (CPU_MIPS2 | ISA_MIPS32) +#define CPU_MIPS64 (CPU_MIPS5 | CPU_MIPS32 | ISA_MIPS64) =20 /* MIPS Technologies "Release 2" */ -#define CPU_MIPS32R2 (CPU_MIPS32 | ISA_MIPS32R2) -#define CPU_MIPS64R2 (CPU_MIPS64 | CPU_MIPS32R2 | ISA_MIPS64R2) +#define CPU_MIPS32R2 (CPU_MIPS32 | ISA_MIPS32R2) +#define CPU_MIPS64R2 (CPU_MIPS64 | CPU_MIPS32R2 | ISA_MIPS64R2) =20 /* MIPS Technologies "Release 3" */ -#define CPU_MIPS32R3 (CPU_MIPS32R2 | ISA_MIPS32R3) -#define CPU_MIPS64R3 (CPU_MIPS64R2 | CPU_MIPS32R3 | ISA_MIPS64R3) +#define CPU_MIPS32R3 (CPU_MIPS32R2 | ISA_MIPS32R3) +#define CPU_MIPS64R3 (CPU_MIPS64R2 | CPU_MIPS32R3 | ISA_MIPS64R3) =20 /* MIPS Technologies "Release 5" */ -#define CPU_MIPS32R5 (CPU_MIPS32R3 | ISA_MIPS32R5) -#define CPU_MIPS64R5 (CPU_MIPS64R3 | CPU_MIPS32R5 | ISA_MIPS64R5) +#define CPU_MIPS32R5 (CPU_MIPS32R3 | ISA_MIPS32R5) +#define CPU_MIPS64R5 (CPU_MIPS64R3 | CPU_MIPS32R5 | ISA_MIPS64R5) =20 /* MIPS Technologies "Release 6" */ -#define CPU_MIPS32R6 (CPU_MIPS32R5 | ISA_MIPS32R6) -#define CPU_MIPS64R6 (CPU_MIPS64R5 | CPU_MIPS32R6 | ISA_MIPS64R6) +#define CPU_MIPS32R6 (CPU_MIPS32R5 | ISA_MIPS32R6) +#define CPU_MIPS64R6 (CPU_MIPS64R5 | CPU_MIPS32R6 | ISA_MIPS64R6) =20 /* Wave Computing: "nanoMIPS" */ -#define CPU_NANOMIPS32 (CPU_MIPS32R6 | ISA_NANOMIPS32) +#define CPU_NANOMIPS32 (CPU_MIPS32R6 | ISA_NANOMIPS32) =20 -/* Strictly follow the architecture standard: - - Disallow "special" instruction handling for PMON/SPIM. - Note that we still maintain Count/Compare to match the host clock. */ -//#define MIPS_STRICT_STANDARD 1 +/* + * Strictly follow the architecture standard: + * - Disallow "special" instruction handling for PMON/SPIM. + * Note that we still maintain Count/Compare to match the host clock. + * + * #define MIPS_STRICT_STANDARD 1 + */ =20 #endif /* QEMU_MIPS_DEFS_H */ --=20 2.7.4 From nobody Sat May 4 18:24:35 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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Tue, 24 Sep 2019 09:28:00 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id E0F751A2266; Tue, 24 Sep 2019 15:26:48 +0200 (CEST) Received: from rtrkw774-lin.domain.local (rtrkw774-lin.domain.local [10.10.13.43]) by mail.rt-rk.com (Postfix) with ESMTPSA id 719551A1FD2; Tue, 24 Sep 2019 15:26:48 +0200 (CEST) X-Virus-Scanned: amavisd-new at rt-rk.com From: Aleksandar Markovic To: qemu-devel@nongnu.org Subject: [PATCH 05/11] target/mips: Clean up op_helper.c Date: Tue, 24 Sep 2019 15:26:36 +0200 Message-Id: <1569331602-2586-6-git-send-email-aleksandar.markovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1569331602-2586-1-git-send-email-aleksandar.markovic@rt-rk.com> References: <1569331602-2586-1-git-send-email-aleksandar.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 89.216.37.149 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: arikalo@wavecomp.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Aleksandar Markovic Mostly fix errors and warnings reported by 'checkpatch.pl -f'. Signed-off-by: Aleksandar Markovic --- target/mips/op_helper.c | 913 ++++++++++++++++++++++++++++++++------------= ---- 1 file changed, 606 insertions(+), 307 deletions(-) diff --git a/target/mips/op_helper.c b/target/mips/op_helper.c index 4de6465..beca781 100644 --- a/target/mips/op_helper.c +++ b/target/mips/op_helper.c @@ -64,8 +64,7 @@ static inline type do_##name(CPUMIPSState *env, target_ul= ong addr, \ static inline type do_##name(CPUMIPSState *env, target_ulong addr, \ int mem_idx, uintptr_t retaddr) \ { \ - switch (mem_idx) \ - { \ + switch (mem_idx) { \ case 0: return (type) cpu_##insn##_kernel_ra(env, addr, retaddr); \ case 1: return (type) cpu_##insn##_super_ra(env, addr, retaddr); \ default: \ @@ -92,8 +91,7 @@ static inline void do_##name(CPUMIPSState *env, target_ul= ong addr, \ static inline void do_##name(CPUMIPSState *env, target_ulong addr, \ type val, int mem_idx, uintptr_t retaddr) \ { \ - switch (mem_idx) \ - { \ + switch (mem_idx) { \ case 0: cpu_##insn##_kernel_ra(env, addr, val, retaddr); break; \ case 1: cpu_##insn##_super_ra(env, addr, val, retaddr); break; \ default: \ @@ -535,7 +533,7 @@ void helper_lwm(CPUMIPSState *env, target_ulong addr, t= arget_ulong reglist, target_ulong base_reglist =3D reglist & 0xf; target_ulong do_r31 =3D reglist & 0x10; =20 - if (base_reglist > 0 && base_reglist <=3D ARRAY_SIZE (multiple_regs)) { + if (base_reglist > 0 && base_reglist <=3D ARRAY_SIZE(multiple_regs)) { target_ulong i; =20 for (i =3D 0; i < base_reglist; i++) { @@ -557,7 +555,7 @@ void helper_swm(CPUMIPSState *env, target_ulong addr, t= arget_ulong reglist, target_ulong base_reglist =3D reglist & 0xf; target_ulong do_r31 =3D reglist & 0x10; =20 - if (base_reglist > 0 && base_reglist <=3D ARRAY_SIZE (multiple_regs)) { + if (base_reglist > 0 && base_reglist <=3D ARRAY_SIZE(multiple_regs)) { target_ulong i; =20 for (i =3D 0; i < base_reglist; i++) { @@ -579,7 +577,7 @@ void helper_ldm(CPUMIPSState *env, target_ulong addr, t= arget_ulong reglist, target_ulong base_reglist =3D reglist & 0xf; target_ulong do_r31 =3D reglist & 0x10; =20 - if (base_reglist > 0 && base_reglist <=3D ARRAY_SIZE (multiple_regs)) { + if (base_reglist > 0 && base_reglist <=3D ARRAY_SIZE(multiple_regs)) { target_ulong i; =20 for (i =3D 0; i < base_reglist; i++) { @@ -600,7 +598,7 @@ void helper_sdm(CPUMIPSState *env, target_ulong addr, t= arget_ulong reglist, target_ulong base_reglist =3D reglist & 0xf; target_ulong do_r31 =3D reglist & 0x10; =20 - if (base_reglist > 0 && base_reglist <=3D ARRAY_SIZE (multiple_regs)) { + if (base_reglist > 0 && base_reglist <=3D ARRAY_SIZE(multiple_regs)) { target_ulong i; =20 for (i =3D 0; i < base_reglist; i++) { @@ -623,8 +621,10 @@ static bool mips_vpe_is_wfi(MIPSCPU *c) CPUState *cpu =3D CPU(c); CPUMIPSState *env =3D &c->env; =20 - /* If the VPE is halted but otherwise active, it means it's waiting for - an interrupt. */ + /* + * If the VPE is halted but otherwise active, it means it's waiting for + * an interrupt.\ + */ return cpu->halted && mips_vpe_active(env); } =20 @@ -638,9 +638,11 @@ static bool mips_vp_is_wfi(MIPSCPU *c) =20 static inline void mips_vpe_wake(MIPSCPU *c) { - /* Don't set ->halted =3D 0 directly, let it be done via cpu_has_work - because there might be other conditions that state that c should - be sleeping. */ + /* + * Don't set ->halted =3D 0 directly, let it be done via cpu_has_work + * because there might be other conditions that state that c should + * be sleeping. + */ qemu_mutex_lock_iothread(); cpu_interrupt(CPU(c), CPU_INTERRUPT_WAKE); qemu_mutex_unlock_iothread(); @@ -650,8 +652,10 @@ static inline void mips_vpe_sleep(MIPSCPU *cpu) { CPUState *cs =3D CPU(cpu); =20 - /* The VPE was shut off, really go to bed. - Reset any old _WAKE requests. */ + /* + * The VPE was shut off, really go to bed. + * Reset any old _WAKE requests. + */ cs->halted =3D 1; cpu_reset_interrupt(cs, CPU_INTERRUPT_WAKE); } @@ -684,9 +688,12 @@ static inline void mips_tc_sleep(MIPSCPU *cpu, int tc) * This function will transform @tc into a local index within the * returned #CPUMIPSState. */ -/* FIXME: This code assumes that all VPEs have the same number of TCs, - which depends on runtime setup. Can probably be fixed by - walking the list of CPUMIPSStates. */ + +/* + * FIXME: This code assumes that all VPEs have the same number of TCs, + * which depends on runtime setup. Can probably be fixed by + * walking the list of CPUMIPSStates. + */ static CPUMIPSState *mips_cpu_map_tc(CPUMIPSState *env, int *tc) { MIPSCPU *cpu; @@ -712,17 +719,21 @@ static CPUMIPSState *mips_cpu_map_tc(CPUMIPSState *en= v, int *tc) return &cpu->env; } =20 -/* The per VPE CP0_Status register shares some fields with the per TC - CP0_TCStatus registers. These fields are wired to the same registers, - so changes to either of them should be reflected on both registers. - - Also, EntryHi shares the bottom 8 bit ASID with TCStauts. - - These helper call synchronizes the regs for a given cpu. */ +/* + * The per VPE CP0_Status register shares some fields with the per TC + * CP0_TCStatus registers. These fields are wired to the same registers, + * so changes to either of them should be reflected on both registers. + * + * Also, EntryHi shares the bottom 8 bit ASID with TCStauts. + * + * These helper call synchronizes the regs for a given cpu. + */ =20 -/* Called for updates to CP0_Status. Defined in "cpu.h" for gdbstub.c. */ -/* static inline void sync_c0_status(CPUMIPSState *env, CPUMIPSState *cpu, - int tc); */ +/* + * Called for updates to CP0_Status. Defined in "cpu.h" for gdbstub.c. + * static inline void sync_c0_status(CPUMIPSState *env, CPUMIPSState *cpu, + * int tc); + */ =20 /* Called for updates to CP0_TCStatus. */ static void sync_c0_tcstatus(CPUMIPSState *cpu, int tc, @@ -805,10 +816,11 @@ target_ulong helper_mftc0_tcstatus(CPUMIPSState *env) int other_tc =3D env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); CPUMIPSState *other =3D mips_cpu_map_tc(env, &other_tc); =20 - if (other_tc =3D=3D other->current_tc) + if (other_tc =3D=3D other->current_tc) { return other->active_tc.CP0_TCStatus; - else + } else { return other->tcs[other_tc].CP0_TCStatus; + } } =20 target_ulong helper_mfc0_tcbind(CPUMIPSState *env) @@ -821,10 +833,11 @@ target_ulong helper_mftc0_tcbind(CPUMIPSState *env) int other_tc =3D env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); CPUMIPSState *other =3D mips_cpu_map_tc(env, &other_tc); =20 - if (other_tc =3D=3D other->current_tc) + if (other_tc =3D=3D other->current_tc) { return other->active_tc.CP0_TCBind; - else + } else { return other->tcs[other_tc].CP0_TCBind; + } } =20 target_ulong helper_mfc0_tcrestart(CPUMIPSState *env) @@ -837,10 +850,11 @@ target_ulong helper_mftc0_tcrestart(CPUMIPSState *env) int other_tc =3D env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); CPUMIPSState *other =3D mips_cpu_map_tc(env, &other_tc); =20 - if (other_tc =3D=3D other->current_tc) + if (other_tc =3D=3D other->current_tc) { return other->active_tc.PC; - else + } else { return other->tcs[other_tc].PC; + } } =20 target_ulong helper_mfc0_tchalt(CPUMIPSState *env) @@ -853,10 +867,11 @@ target_ulong helper_mftc0_tchalt(CPUMIPSState *env) int other_tc =3D env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); CPUMIPSState *other =3D mips_cpu_map_tc(env, &other_tc); =20 - if (other_tc =3D=3D other->current_tc) + if (other_tc =3D=3D other->current_tc) { return other->active_tc.CP0_TCHalt; - else + } else { return other->tcs[other_tc].CP0_TCHalt; + } } =20 target_ulong helper_mfc0_tccontext(CPUMIPSState *env) @@ -869,10 +884,11 @@ target_ulong helper_mftc0_tccontext(CPUMIPSState *env) int other_tc =3D env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); CPUMIPSState *other =3D mips_cpu_map_tc(env, &other_tc); =20 - if (other_tc =3D=3D other->current_tc) + if (other_tc =3D=3D other->current_tc) { return other->active_tc.CP0_TCContext; - else + } else { return other->tcs[other_tc].CP0_TCContext; + } } =20 target_ulong helper_mfc0_tcschedule(CPUMIPSState *env) @@ -885,10 +901,11 @@ target_ulong helper_mftc0_tcschedule(CPUMIPSState *en= v) int other_tc =3D env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); CPUMIPSState *other =3D mips_cpu_map_tc(env, &other_tc); =20 - if (other_tc =3D=3D other->current_tc) + if (other_tc =3D=3D other->current_tc) { return other->active_tc.CP0_TCSchedule; - else + } else { return other->tcs[other_tc].CP0_TCSchedule; + } } =20 target_ulong helper_mfc0_tcschefback(CPUMIPSState *env) @@ -901,10 +918,11 @@ target_ulong helper_mftc0_tcschefback(CPUMIPSState *e= nv) int other_tc =3D env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); CPUMIPSState *other =3D mips_cpu_map_tc(env, &other_tc); =20 - if (other_tc =3D=3D other->current_tc) + if (other_tc =3D=3D other->current_tc) { return other->active_tc.CP0_TCScheFBack; - else + } else { return other->tcs[other_tc].CP0_TCScheFBack; + } } =20 target_ulong helper_mfc0_count(CPUMIPSState *env) @@ -987,8 +1005,9 @@ target_ulong helper_mfc0_watchhi(CPUMIPSState *env, ui= nt32_t sel) target_ulong helper_mfc0_debug(CPUMIPSState *env) { target_ulong t0 =3D env->CP0_Debug; - if (env->hflags & MIPS_HFLAG_DM) + if (env->hflags & MIPS_HFLAG_DM) { t0 |=3D 1 << CP0DB_DM; + } =20 return t0; } @@ -999,10 +1018,11 @@ target_ulong helper_mftc0_debug(CPUMIPSState *env) int32_t tcstatus; CPUMIPSState *other =3D mips_cpu_map_tc(env, &other_tc); =20 - if (other_tc =3D=3D other->current_tc) + if (other_tc =3D=3D other->current_tc) { tcstatus =3D other->active_tc.CP0_Debug_tcstatus; - else + } else { tcstatus =3D other->tcs[other_tc].CP0_Debug_tcstatus; + } =20 /* XXX: Might be wrong, check with EJTAG spec. */ return (other->CP0_Debug & ~((1 << CP0DB_SSt) | (1 << CP0DB_Halt))) | @@ -1076,14 +1096,16 @@ void helper_mtc0_mvpcontrol(CPUMIPSState *env, targ= et_ulong arg1) uint32_t mask =3D 0; uint32_t newval; =20 - if (env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP)) + if (env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP)) { mask |=3D (1 << CP0MVPCo_CPA) | (1 << CP0MVPCo_VPC) | (1 << CP0MVPCo_EVP); - if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC)) + } + if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC)) { mask |=3D (1 << CP0MVPCo_STLB); + } newval =3D (env->mvp->CP0_MVPControl & ~mask) | (arg1 & mask); =20 - // TODO: Enable/disable shared TLB, enable/disable VPEs. + /* TODO: Enable/disable shared TLB, enable/disable VPEs. */ =20 env->mvp->CP0_MVPControl =3D newval; } @@ -1097,10 +1119,12 @@ void helper_mtc0_vpecontrol(CPUMIPSState *env, targ= et_ulong arg1) (1 << CP0VPECo_TE) | (0xff << CP0VPECo_TargTC); newval =3D (env->CP0_VPEControl & ~mask) | (arg1 & mask); =20 - /* Yield scheduler intercept not implemented. */ - /* Gating storage scheduler intercept not implemented. */ + /* + * Yield scheduler intercept not implemented. + * Gating storage scheduler intercept not implemented. + */ =20 - // TODO: Enable/disable TCs. + /* TODO: Enable/disable TCs. */ =20 env->CP0_VPEControl =3D newval; } @@ -1143,13 +1167,14 @@ void helper_mtc0_vpeconf0(CPUMIPSState *env, target= _ulong arg1) uint32_t newval; =20 if (env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP)) { - if (env->CP0_VPEConf0 & (1 << CP0VPEC0_VPA)) + if (env->CP0_VPEConf0 & (1 << CP0VPEC0_VPA)) { mask |=3D (0xff << CP0VPEC0_XTC); + } mask |=3D (1 << CP0VPEC0_MVP) | (1 << CP0VPEC0_VPA); } newval =3D (env->CP0_VPEConf0 & ~mask) | (arg1 & mask); =20 - // TODO: TC exclusive handling due to ERL/EXL. + /* TODO: TC exclusive handling due to ERL/EXL. */ =20 env->CP0_VPEConf0 =3D newval; } @@ -1181,7 +1206,7 @@ void helper_mtc0_vpeconf1(CPUMIPSState *env, target_u= long arg1) /* UDI not implemented. */ /* CP2 not implemented. */ =20 - // TODO: Handle FPU (CP1) binding. + /* TODO: Handle FPU (CP1) binding. */ =20 env->CP0_VPEConf1 =3D newval; } @@ -1233,10 +1258,11 @@ void helper_mttc0_tcstatus(CPUMIPSState *env, targe= t_ulong arg1) int other_tc =3D env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); CPUMIPSState *other =3D mips_cpu_map_tc(env, &other_tc); =20 - if (other_tc =3D=3D other->current_tc) + if (other_tc =3D=3D other->current_tc) { other->active_tc.CP0_TCStatus =3D arg1; - else + } else { other->tcs[other_tc].CP0_TCStatus =3D arg1; + } sync_c0_tcstatus(other, other_tc, arg1); } =20 @@ -1245,8 +1271,9 @@ void helper_mtc0_tcbind(CPUMIPSState *env, target_ulo= ng arg1) uint32_t mask =3D (1 << CP0TCBd_TBE); uint32_t newval; =20 - if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC)) + if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC)) { mask |=3D (1 << CP0TCBd_CurVPE); + } newval =3D (env->active_tc.CP0_TCBind & ~mask) | (arg1 & mask); env->active_tc.CP0_TCBind =3D newval; } @@ -1258,8 +1285,9 @@ void helper_mttc0_tcbind(CPUMIPSState *env, target_ul= ong arg1) uint32_t newval; CPUMIPSState *other =3D mips_cpu_map_tc(env, &other_tc); =20 - if (other->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC)) + if (other->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC)) { mask |=3D (1 << CP0TCBd_CurVPE); + } if (other_tc =3D=3D other->current_tc) { newval =3D (other->active_tc.CP0_TCBind & ~mask) | (arg1 & mask); other->active_tc.CP0_TCBind =3D newval; @@ -1304,7 +1332,7 @@ void helper_mtc0_tchalt(CPUMIPSState *env, target_ulo= ng arg1) =20 env->active_tc.CP0_TCHalt =3D arg1 & 0x1; =20 - // TODO: Halt TC / Restart (if allocated+active) TC. + /* TODO: Halt TC / Restart (if allocated+active) TC. */ if (env->active_tc.CP0_TCHalt & 1) { mips_tc_sleep(cpu, env->current_tc); } else { @@ -1318,12 +1346,13 @@ void helper_mttc0_tchalt(CPUMIPSState *env, target_= ulong arg1) CPUMIPSState *other =3D mips_cpu_map_tc(env, &other_tc); MIPSCPU *other_cpu =3D env_archcpu(other); =20 - // TODO: Halt TC / Restart (if allocated+active) TC. + /* TODO: Halt TC / Restart (if allocated+active) TC. */ =20 - if (other_tc =3D=3D other->current_tc) + if (other_tc =3D=3D other->current_tc) { other->active_tc.CP0_TCHalt =3D arg1; - else + } else { other->tcs[other_tc].CP0_TCHalt =3D arg1; + } =20 if (arg1 & 1) { mips_tc_sleep(other_cpu, other_tc); @@ -1342,10 +1371,11 @@ void helper_mttc0_tccontext(CPUMIPSState *env, targ= et_ulong arg1) int other_tc =3D env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); CPUMIPSState *other =3D mips_cpu_map_tc(env, &other_tc); =20 - if (other_tc =3D=3D other->current_tc) + if (other_tc =3D=3D other->current_tc) { other->active_tc.CP0_TCContext =3D arg1; - else + } else { other->tcs[other_tc].CP0_TCContext =3D arg1; + } } =20 void helper_mtc0_tcschedule(CPUMIPSState *env, target_ulong arg1) @@ -1358,10 +1388,11 @@ void helper_mttc0_tcschedule(CPUMIPSState *env, tar= get_ulong arg1) int other_tc =3D env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); CPUMIPSState *other =3D mips_cpu_map_tc(env, &other_tc); =20 - if (other_tc =3D=3D other->current_tc) + if (other_tc =3D=3D other->current_tc) { other->active_tc.CP0_TCSchedule =3D arg1; - else + } else { other->tcs[other_tc].CP0_TCSchedule =3D arg1; + } } =20 void helper_mtc0_tcschefback(CPUMIPSState *env, target_ulong arg1) @@ -1374,10 +1405,11 @@ void helper_mttc0_tcschefback(CPUMIPSState *env, ta= rget_ulong arg1) int other_tc =3D env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); CPUMIPSState *other =3D mips_cpu_map_tc(env, &other_tc); =20 - if (other_tc =3D=3D other->current_tc) + if (other_tc =3D=3D other->current_tc) { other->active_tc.CP0_TCScheFBack =3D arg1; - else + } else { other->tcs[other_tc].CP0_TCScheFBack =3D arg1; + } } =20 void helper_mtc0_entrylo1(CPUMIPSState *env, target_ulong arg1) @@ -1703,9 +1735,15 @@ void helper_mtc0_status(CPUMIPSState *env, target_ul= ong arg1) case 3: qemu_log(", ERL\n"); break; - case MIPS_HFLAG_UM: qemu_log(", UM\n"); break; - case MIPS_HFLAG_SM: qemu_log(", SM\n"); break; - case MIPS_HFLAG_KM: qemu_log("\n"); break; + case MIPS_HFLAG_UM: + qemu_log(", UM\n"); + break; + case MIPS_HFLAG_SM: + qemu_log(", SM\n"); + break; + case MIPS_HFLAG_KM: + qemu_log("\n"); + break; default: cpu_abort(env_cpu(env), "Invalid MMU mode!\n"); break; @@ -1899,10 +1937,11 @@ void helper_mtc0_framemask(CPUMIPSState *env, targe= t_ulong arg1) void helper_mtc0_debug(CPUMIPSState *env, target_ulong arg1) { env->CP0_Debug =3D (env->CP0_Debug & 0x8C03FC1F) | (arg1 & 0x13300120); - if (arg1 & (1 << CP0DB_DM)) + if (arg1 & (1 << CP0DB_DM)) { env->hflags |=3D MIPS_HFLAG_DM; - else + } else { env->hflags &=3D ~MIPS_HFLAG_DM; + } } =20 void helper_mttc0_debug(CPUMIPSState *env, target_ulong arg1) @@ -1912,10 +1951,11 @@ void helper_mttc0_debug(CPUMIPSState *env, target_u= long arg1) CPUMIPSState *other =3D mips_cpu_map_tc(env, &other_tc); =20 /* XXX: Might be wrong, check with EJTAG spec. */ - if (other_tc =3D=3D other->current_tc) + if (other_tc =3D=3D other->current_tc) { other->active_tc.CP0_Debug_tcstatus =3D val; - else + } else { other->tcs[other_tc].CP0_Debug_tcstatus =3D val; + } other->CP0_Debug =3D (other->CP0_Debug & ((1 << CP0DB_SSt) | (1 << CP0DB_Halt))) | (arg1 & ~((1 << CP0DB_SSt) | (1 << CP0DB_Halt))); @@ -1974,10 +2014,11 @@ target_ulong helper_mftgpr(CPUMIPSState *env, uint3= 2_t sel) int other_tc =3D env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); CPUMIPSState *other =3D mips_cpu_map_tc(env, &other_tc); =20 - if (other_tc =3D=3D other->current_tc) + if (other_tc =3D=3D other->current_tc) { return other->active_tc.gpr[sel]; - else + } else { return other->tcs[other_tc].gpr[sel]; + } } =20 target_ulong helper_mftlo(CPUMIPSState *env, uint32_t sel) @@ -1985,10 +2026,11 @@ target_ulong helper_mftlo(CPUMIPSState *env, uint32= _t sel) int other_tc =3D env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); CPUMIPSState *other =3D mips_cpu_map_tc(env, &other_tc); =20 - if (other_tc =3D=3D other->current_tc) + if (other_tc =3D=3D other->current_tc) { return other->active_tc.LO[sel]; - else + } else { return other->tcs[other_tc].LO[sel]; + } } =20 target_ulong helper_mfthi(CPUMIPSState *env, uint32_t sel) @@ -1996,10 +2038,11 @@ target_ulong helper_mfthi(CPUMIPSState *env, uint32= _t sel) int other_tc =3D env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); CPUMIPSState *other =3D mips_cpu_map_tc(env, &other_tc); =20 - if (other_tc =3D=3D other->current_tc) + if (other_tc =3D=3D other->current_tc) { return other->active_tc.HI[sel]; - else + } else { return other->tcs[other_tc].HI[sel]; + } } =20 target_ulong helper_mftacx(CPUMIPSState *env, uint32_t sel) @@ -2007,10 +2050,11 @@ target_ulong helper_mftacx(CPUMIPSState *env, uint3= 2_t sel) int other_tc =3D env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); CPUMIPSState *other =3D mips_cpu_map_tc(env, &other_tc); =20 - if (other_tc =3D=3D other->current_tc) + if (other_tc =3D=3D other->current_tc) { return other->active_tc.ACX[sel]; - else + } else { return other->tcs[other_tc].ACX[sel]; + } } =20 target_ulong helper_mftdsp(CPUMIPSState *env) @@ -2018,10 +2062,11 @@ target_ulong helper_mftdsp(CPUMIPSState *env) int other_tc =3D env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); CPUMIPSState *other =3D mips_cpu_map_tc(env, &other_tc); =20 - if (other_tc =3D=3D other->current_tc) + if (other_tc =3D=3D other->current_tc) { return other->active_tc.DSPControl; - else + } else { return other->tcs[other_tc].DSPControl; + } } =20 void helper_mttgpr(CPUMIPSState *env, target_ulong arg1, uint32_t sel) @@ -2029,10 +2074,11 @@ void helper_mttgpr(CPUMIPSState *env, target_ulong = arg1, uint32_t sel) int other_tc =3D env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); CPUMIPSState *other =3D mips_cpu_map_tc(env, &other_tc); =20 - if (other_tc =3D=3D other->current_tc) + if (other_tc =3D=3D other->current_tc) { other->active_tc.gpr[sel] =3D arg1; - else + } else { other->tcs[other_tc].gpr[sel] =3D arg1; + } } =20 void helper_mttlo(CPUMIPSState *env, target_ulong arg1, uint32_t sel) @@ -2040,10 +2086,11 @@ void helper_mttlo(CPUMIPSState *env, target_ulong a= rg1, uint32_t sel) int other_tc =3D env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); CPUMIPSState *other =3D mips_cpu_map_tc(env, &other_tc); =20 - if (other_tc =3D=3D other->current_tc) + if (other_tc =3D=3D other->current_tc) { other->active_tc.LO[sel] =3D arg1; - else + } else { other->tcs[other_tc].LO[sel] =3D arg1; + } } =20 void helper_mtthi(CPUMIPSState *env, target_ulong arg1, uint32_t sel) @@ -2051,10 +2098,11 @@ void helper_mtthi(CPUMIPSState *env, target_ulong a= rg1, uint32_t sel) int other_tc =3D env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); CPUMIPSState *other =3D mips_cpu_map_tc(env, &other_tc); =20 - if (other_tc =3D=3D other->current_tc) + if (other_tc =3D=3D other->current_tc) { other->active_tc.HI[sel] =3D arg1; - else + } else { other->tcs[other_tc].HI[sel] =3D arg1; + } } =20 void helper_mttacx(CPUMIPSState *env, target_ulong arg1, uint32_t sel) @@ -2062,10 +2110,11 @@ void helper_mttacx(CPUMIPSState *env, target_ulong = arg1, uint32_t sel) int other_tc =3D env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); CPUMIPSState *other =3D mips_cpu_map_tc(env, &other_tc); =20 - if (other_tc =3D=3D other->current_tc) + if (other_tc =3D=3D other->current_tc) { other->active_tc.ACX[sel] =3D arg1; - else + } else { other->tcs[other_tc].ACX[sel] =3D arg1; + } } =20 void helper_mttdsp(CPUMIPSState *env, target_ulong arg1) @@ -2073,22 +2122,23 @@ void helper_mttdsp(CPUMIPSState *env, target_ulong = arg1) int other_tc =3D env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); CPUMIPSState *other =3D mips_cpu_map_tc(env, &other_tc); =20 - if (other_tc =3D=3D other->current_tc) + if (other_tc =3D=3D other->current_tc) { other->active_tc.DSPControl =3D arg1; - else + } else { other->tcs[other_tc].DSPControl =3D arg1; + } } =20 /* MIPS MT functions */ target_ulong helper_dmt(void) { - // TODO - return 0; + /* TODO */ + return 0; } =20 target_ulong helper_emt(void) { - // TODO + /* TODO */ return 0; } =20 @@ -2130,8 +2180,10 @@ target_ulong helper_evpe(CPUMIPSState *env) =20 void helper_fork(target_ulong arg1, target_ulong arg2) { - // arg1 =3D rt, arg2 =3D rs - // TODO: store to TC register + /* + * arg1 =3D rt, arg2 =3D rs + * TODO: store to TC register + */ } =20 target_ulong helper_yield(CPUMIPSState *env, target_ulong arg) @@ -2149,11 +2201,12 @@ target_ulong helper_yield(CPUMIPSState *env, target= _ulong arg) } } } else if (arg1 =3D=3D 0) { - if (0 /* TODO: TC underflow */) { + if (0) { + /* TODO: TC underflow */ env->CP0_VPEControl &=3D ~(0x7 << CP0VPECo_EXCPT); do_raise_exception(env, EXCP_THREAD, GETPC()); } else { - // TODO: Deallocate TC + /* TODO: Deallocate TC */ } } else if (arg1 > 0) { /* Yield qualifier inputs not implemented. */ @@ -2193,8 +2246,10 @@ target_ulong helper_evp(CPUMIPSState *env) CPU_FOREACH(other_cs) { MIPSCPU *other_cpu =3D MIPS_CPU(other_cs); if ((&other_cpu->env !=3D env) && !mips_vp_is_wfi(other_cpu)) { - /* If the VP is WFI, don't disturb its sleep. - * Otherwise, wake it up. */ + /* + * If the VP is WFI, don't disturb its sleep. + * Otherwise, wake it up. + */ mips_vpe_wake(other_cpu); } } @@ -2206,7 +2261,7 @@ target_ulong helper_evp(CPUMIPSState *env) =20 #ifndef CONFIG_USER_ONLY /* TLB management */ -static void r4k_mips_tlb_flush_extra (CPUMIPSState *env, int first) +static void r4k_mips_tlb_flush_extra(CPUMIPSState *env, int first) { /* Discard entries from env->tlb[first] onwards. */ while (env->tlb->tlb_in_use > first) { @@ -2308,8 +2363,10 @@ void r4k_helper_tlbwi(CPUMIPSState *env) XI1 =3D (env->CP0_EntryLo1 >> CP0EnLo_XI) &1; RI1 =3D (env->CP0_EntryLo1 >> CP0EnLo_RI) &1; =20 - /* Discard cached TLB entries, unless tlbwi is just upgrading access - permissions on the current entry. */ + /* + * Discard cached TLB entries, unless tlbwi is just upgrading access + * permissions on the current entry. + */ if (tlb->VPN !=3D VPN || tlb->ASID !=3D ASID || tlb->G !=3D G || (!tlb->EHINV && EHINV) || (tlb->V0 && !V0) || (tlb->D0 && !D0) || @@ -2370,7 +2427,7 @@ void r4k_helper_tlbp(CPUMIPSState *env) #endif /* Check ASID, virtual page number & size */ if ((tlb->G =3D=3D 1 || tlb->ASID =3D=3D ASID) && VPN =3D=3D t= ag) { - r4k_mips_tlb_flush_extra (env, i); + r4k_mips_tlb_flush_extra(env, i); break; } } @@ -2400,8 +2457,9 @@ void r4k_helper_tlbr(CPUMIPSState *env) tlb =3D &env->tlb->mmu.r4k.tlb[idx]; =20 /* If this will change the current ASID, flush qemu's TLB. */ - if (ASID !=3D tlb->ASID) + if (ASID !=3D tlb->ASID) { cpu_mips_tlb_flush(env); + } =20 r4k_mips_tlb_flush_extra(env, env->tlb->nb_tlb); =20 @@ -2476,10 +2534,12 @@ static void debug_pre_eret(CPUMIPSState *env) if (qemu_loglevel_mask(CPU_LOG_EXEC)) { qemu_log("ERET: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx, env->active_tc.PC, env->CP0_EPC); - if (env->CP0_Status & (1 << CP0St_ERL)) + if (env->CP0_Status & (1 << CP0St_ERL)) { qemu_log(" ErrorEPC " TARGET_FMT_lx, env->CP0_ErrorEPC); - if (env->hflags & MIPS_HFLAG_DM) + } + if (env->hflags & MIPS_HFLAG_DM) { qemu_log(" DEPC " TARGET_FMT_lx, env->CP0_DEPC); + } qemu_log("\n"); } } @@ -2489,17 +2549,25 @@ static void debug_post_eret(CPUMIPSState *env) if (qemu_loglevel_mask(CPU_LOG_EXEC)) { qemu_log(" =3D> PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx, env->active_tc.PC, env->CP0_EPC); - if (env->CP0_Status & (1 << CP0St_ERL)) + if (env->CP0_Status & (1 << CP0St_ERL)) { qemu_log(" ErrorEPC " TARGET_FMT_lx, env->CP0_ErrorEPC); - if (env->hflags & MIPS_HFLAG_DM) + } + if (env->hflags & MIPS_HFLAG_DM) { qemu_log(" DEPC " TARGET_FMT_lx, env->CP0_DEPC); + } switch (cpu_mmu_index(env, false)) { case 3: qemu_log(", ERL\n"); break; - case MIPS_HFLAG_UM: qemu_log(", UM\n"); break; - case MIPS_HFLAG_SM: qemu_log(", SM\n"); break; - case MIPS_HFLAG_KM: qemu_log("\n"); break; + case MIPS_HFLAG_UM: + qemu_log(", UM\n"); + break; + case MIPS_HFLAG_SM: + qemu_log(", SM\n"); + break; + case MIPS_HFLAG_KM: + qemu_log("\n"); + break; default: cpu_abort(env_cpu(env), "Invalid MMU mode!\n"); break; @@ -2609,8 +2677,9 @@ void helper_pmon(CPUMIPSState *env, int function) function /=3D 2; switch (function) { case 2: /* TODO: char inbyte(int waitflag); */ - if (env->active_tc.gpr[4] =3D=3D 0) + if (env->active_tc.gpr[4] =3D=3D 0) { env->active_tc.gpr[2] =3D -1; + } /* Fall through */ case 11: /* TODO: char inbyte (void); */ env->active_tc.gpr[2] =3D -1; @@ -2636,8 +2705,10 @@ void helper_wait(CPUMIPSState *env) =20 cs->halted =3D 1; cpu_reset_interrupt(cs, CPU_INTERRUPT_WAKE); - /* Last instruction in the block, PC was updated before - - no need to recover PC and icount */ + /* + * Last instruction in the block, PC was updated before + * - no need to recover PC and icount. + */ raise_exception(env, EXCP_HLT); } =20 @@ -2731,13 +2802,15 @@ target_ulong helper_cfc1(CPUMIPSState *env, uint32_= t reg) } break; case 25: - arg1 =3D ((env->active_fpu.fcr31 >> 24) & 0xfe) | ((env->active_fp= u.fcr31 >> 23) & 0x1); + arg1 =3D ((env->active_fpu.fcr31 >> 24) & 0xfe) | + ((env->active_fpu.fcr31 >> 23) & 0x1); break; case 26: arg1 =3D env->active_fpu.fcr31 & 0x0003f07c; break; case 28: - arg1 =3D (env->active_fpu.fcr31 & 0x00000f83) | ((env->active_fpu.= fcr31 >> 22) & 0x4); + arg1 =3D (env->active_fpu.fcr31 & 0x00000f83) | + ((env->active_fpu.fcr31 >> 22) & 0x4); break; default: arg1 =3D (int32_t)env->active_fpu.fcr31; @@ -2802,19 +2875,24 @@ void helper_ctc1(CPUMIPSState *env, target_ulong ar= g1, uint32_t fs, uint32_t rt) if ((env->insn_flags & ISA_MIPS32R6) || (arg1 & 0xffffff00)) { return; } - env->active_fpu.fcr31 =3D (env->active_fpu.fcr31 & 0x017fffff) | (= (arg1 & 0xfe) << 24) | - ((arg1 & 0x1) << 23); + env->active_fpu.fcr31 =3D (env->active_fpu.fcr31 & 0x017fffff) | + ((arg1 & 0xfe) << 24) | + ((arg1 & 0x1) << 23); break; case 26: - if (arg1 & 0x007c0000) + if (arg1 & 0x007c0000) { return; - env->active_fpu.fcr31 =3D (env->active_fpu.fcr31 & 0xfffc0f83) | (= arg1 & 0x0003f07c); + } + env->active_fpu.fcr31 =3D (env->active_fpu.fcr31 & 0xfffc0f83) | + (arg1 & 0x0003f07c); break; case 28: - if (arg1 & 0x007c0000) + if (arg1 & 0x007c0000) { return; - env->active_fpu.fcr31 =3D (env->active_fpu.fcr31 & 0xfefff07c) | (= arg1 & 0x00000f83) | - ((arg1 & 0x4) << 22); + } + env->active_fpu.fcr31 =3D (env->active_fpu.fcr31 & 0xfefff07c) | + (arg1 & 0x00000f83) | + ((arg1 & 0x4) << 22); break; case 31: env->active_fpu.fcr31 =3D (arg1 & env->active_fpu.fcr31_rw_bitmask= ) | @@ -2828,8 +2906,10 @@ void helper_ctc1(CPUMIPSState *env, target_ulong arg= 1, uint32_t fs, uint32_t rt) } restore_fp_status(env); set_float_exception_flags(0, &env->active_fpu.fp_status); - if ((GET_FP_ENABLE(env->active_fpu.fcr31) | 0x20) & GET_FP_CAUSE(env->= active_fpu.fcr31)) + if ((GET_FP_ENABLE(env->active_fpu.fcr31) | 0x20) & + GET_FP_CAUSE(env->active_fpu.fcr31)) { do_raise_exception(env, EXCP_FPE, GETPC()); + } } =20 int ieee_ex_to_mips(int xcpt) @@ -2857,7 +2937,8 @@ int ieee_ex_to_mips(int xcpt) =20 static inline void update_fcr31(CPUMIPSState *env, uintptr_t pc) { - int tmp =3D ieee_ex_to_mips(get_float_exception_flags(&env->active_fpu= .fp_status)); + int tmp =3D ieee_ex_to_mips(get_float_exception_flags( + &env->active_fpu.fp_status)); =20 SET_FP_CAUSE(env->active_fpu.fcr31, tmp); =20 @@ -2872,10 +2953,12 @@ static inline void update_fcr31(CPUMIPSState *env, = uintptr_t pc) } } =20 -/* Float support. - Single precition routines have a "s" suffix, double precision a - "d" suffix, 32bit integer "w", 64bit integer "l", paired single "ps", - paired single lower "pl", paired single upper "pu". */ +/* + * Float support. + * Single precition routines have a "s" suffix, double precision a + * "d" suffix, 32bit integer "w", 64bit integer "l", paired single "ps", + * paired single lower "pl", paired single upper "pu". + */ =20 /* unary operations, modifying fp status */ uint64_t helper_float_sqrt_d(CPUMIPSState *env, uint64_t fdt0) @@ -3056,7 +3139,8 @@ uint64_t helper_float_round_l_d(CPUMIPSState *env, ui= nt64_t fdt0) { uint64_t dt2; =20 - set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_= status); + set_float_rounding_mode(float_round_nearest_even, + &env->active_fpu.fp_status); dt2 =3D float64_to_int64(fdt0, &env->active_fpu.fp_status); restore_rounding_mode(env); if (get_float_exception_flags(&env->active_fpu.fp_status) @@ -3071,7 +3155,8 @@ uint64_t helper_float_round_l_s(CPUMIPSState *env, ui= nt32_t fst0) { uint64_t dt2; =20 - set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_= status); + set_float_rounding_mode(float_round_nearest_even, + &env->active_fpu.fp_status); dt2 =3D float32_to_int64(fst0, &env->active_fpu.fp_status); restore_rounding_mode(env); if (get_float_exception_flags(&env->active_fpu.fp_status) @@ -3086,7 +3171,8 @@ uint32_t helper_float_round_w_d(CPUMIPSState *env, ui= nt64_t fdt0) { uint32_t wt2; =20 - set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_= status); + set_float_rounding_mode(float_round_nearest_even, + &env->active_fpu.fp_status); wt2 =3D float64_to_int32(fdt0, &env->active_fpu.fp_status); restore_rounding_mode(env); if (get_float_exception_flags(&env->active_fpu.fp_status) @@ -3101,7 +3187,8 @@ uint32_t helper_float_round_w_s(CPUMIPSState *env, ui= nt32_t fst0) { uint32_t wt2; =20 - set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_= status); + set_float_rounding_mode(float_round_nearest_even, + &env->active_fpu.fp_status); wt2 =3D float32_to_int32(fst0, &env->active_fpu.fp_status); restore_rounding_mode(env); if (get_float_exception_flags(&env->active_fpu.fp_status) @@ -3116,7 +3203,8 @@ uint64_t helper_float_trunc_l_d(CPUMIPSState *env, ui= nt64_t fdt0) { uint64_t dt2; =20 - dt2 =3D float64_to_int64_round_to_zero(fdt0, &env->active_fpu.fp_statu= s); + dt2 =3D float64_to_int64_round_to_zero(fdt0, + &env->active_fpu.fp_status); if (get_float_exception_flags(&env->active_fpu.fp_status) & (float_flag_invalid | float_flag_overflow)) { dt2 =3D FP_TO_INT64_OVERFLOW; @@ -3860,7 +3948,8 @@ uint64_t helper_float_recip2_d(CPUMIPSState *env, uin= t64_t fdt0, uint64_t fdt2) uint32_t helper_float_recip2_s(CPUMIPSState *env, uint32_t fst0, uint32_t = fst2) { fst2 =3D float32_mul(fst0, fst2, &env->active_fpu.fp_status); - fst2 =3D float32_chs(float32_sub(fst2, float32_one, &env->active_fpu.f= p_status)); + fst2 =3D float32_chs(float32_sub(fst2, float32_one, + &env->active_fpu.fp_status)); update_fcr31(env, GETPC()); return fst2; } @@ -3874,8 +3963,10 @@ uint64_t helper_float_recip2_ps(CPUMIPSState *env, u= int64_t fdt0, uint64_t fdt2) =20 fst2 =3D float32_mul(fst0, fst2, &env->active_fpu.fp_status); fsth2 =3D float32_mul(fsth0, fsth2, &env->active_fpu.fp_status); - fst2 =3D float32_chs(float32_sub(fst2, float32_one, &env->active_fpu.f= p_status)); - fsth2 =3D float32_chs(float32_sub(fsth2, float32_one, &env->active_fpu= .fp_status)); + fst2 =3D float32_chs(float32_sub(fst2, float32_one, + &env->active_fpu.fp_status)); + fsth2 =3D float32_chs(float32_sub(fsth2, float32_one, + &env->active_fpu.fp_status)); update_fcr31(env, GETPC()); return ((uint64_t)fsth2 << 32) | fst2; } @@ -3884,7 +3975,8 @@ uint64_t helper_float_rsqrt2_d(CPUMIPSState *env, uin= t64_t fdt0, uint64_t fdt2) { fdt2 =3D float64_mul(fdt0, fdt2, &env->active_fpu.fp_status); fdt2 =3D float64_sub(fdt2, float64_one, &env->active_fpu.fp_status); - fdt2 =3D float64_chs(float64_div(fdt2, FLOAT_TWO64, &env->active_fpu.f= p_status)); + fdt2 =3D float64_chs(float64_div(fdt2, FLOAT_TWO64, + &env->active_fpu.fp_status)); update_fcr31(env, GETPC()); return fdt2; } @@ -3893,7 +3985,8 @@ uint32_t helper_float_rsqrt2_s(CPUMIPSState *env, uin= t32_t fst0, uint32_t fst2) { fst2 =3D float32_mul(fst0, fst2, &env->active_fpu.fp_status); fst2 =3D float32_sub(fst2, float32_one, &env->active_fpu.fp_status); - fst2 =3D float32_chs(float32_div(fst2, FLOAT_TWO32, &env->active_fpu.f= p_status)); + fst2 =3D float32_chs(float32_div(fst2, FLOAT_TWO32, + &env->active_fpu.fp_status)); update_fcr31(env, GETPC()); return fst2; } @@ -3909,8 +4002,10 @@ uint64_t helper_float_rsqrt2_ps(CPUMIPSState *env, u= int64_t fdt0, uint64_t fdt2) fsth2 =3D float32_mul(fsth0, fsth2, &env->active_fpu.fp_status); fst2 =3D float32_sub(fst2, float32_one, &env->active_fpu.fp_status); fsth2 =3D float32_sub(fsth2, float32_one, &env->active_fpu.fp_status); - fst2 =3D float32_chs(float32_div(fst2, FLOAT_TWO32, &env->active_fpu.f= p_status)); - fsth2 =3D float32_chs(float32_div(fsth2, FLOAT_TWO32, &env->active_fpu= .fp_status)); + fst2 =3D float32_chs(float32_div(fst2, FLOAT_TWO32, + &env->active_fpu.fp_status)); + fsth2 =3D float32_chs(float32_div(fsth2, FLOAT_TWO32, + &env->active_fpu.fp_status)); update_fcr31(env, GETPC()); return ((uint64_t)fsth2 << 32) | fst2; } @@ -3924,8 +4019,8 @@ uint64_t helper_float_addr_ps(CPUMIPSState *env, uint= 64_t fdt0, uint64_t fdt1) uint32_t fst2; uint32_t fsth2; =20 - fst2 =3D float32_add (fst0, fsth0, &env->active_fpu.fp_status); - fsth2 =3D float32_add (fst1, fsth1, &env->active_fpu.fp_status); + fst2 =3D float32_add(fst0, fsth0, &env->active_fpu.fp_status); + fsth2 =3D float32_add(fst1, fsth1, &env->active_fpu.fp_status); update_fcr31(env, GETPC()); return ((uint64_t)fsth2 << 32) | fst2; } @@ -3939,8 +4034,8 @@ uint64_t helper_float_mulr_ps(CPUMIPSState *env, uint= 64_t fdt0, uint64_t fdt1) uint32_t fst2; uint32_t fsth2; =20 - fst2 =3D float32_mul (fst0, fsth0, &env->active_fpu.fp_status); - fsth2 =3D float32_mul (fst1, fsth1, &env->active_fpu.fp_status); + fst2 =3D float32_mul(fst0, fsth0, &env->active_fpu.fp_status); + fsth2 =3D float32_mul(fst1, fsth1, &env->active_fpu.fp_status); update_fcr31(env, GETPC()); return ((uint64_t)fsth2 << 32) | fst2; } @@ -4072,26 +4167,58 @@ void helper_cmpabs_d_ ## op(CPUMIPSState *env, uint= 64_t fdt0, \ CLEAR_FP_COND(cc, env->active_fpu); \ } =20 -/* NOTE: the comma operator will make "cond" to eval to false, - * but float64_unordered_quiet() is still called. */ -FOP_COND_D(f, (float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_s= tatus), 0)) -FOP_COND_D(un, float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_st= atus)) -FOP_COND_D(eq, float64_eq_quiet(fdt0, fdt1, &env->active_fpu.fp_status)) -FOP_COND_D(ueq, float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_st= atus) || float64_eq_quiet(fdt0, fdt1, &env->active_fpu.fp_status)) -FOP_COND_D(olt, float64_lt_quiet(fdt0, fdt1, &env->active_fpu.fp_status)) -FOP_COND_D(ult, float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_st= atus) || float64_lt_quiet(fdt0, fdt1, &env->active_fpu.fp_status)) -FOP_COND_D(ole, float64_le_quiet(fdt0, fdt1, &env->active_fpu.fp_status)) -FOP_COND_D(ule, float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_st= atus) || float64_le_quiet(fdt0, fdt1, &env->active_fpu.fp_status)) -/* NOTE: the comma operator will make "cond" to eval to false, - * but float64_unordered() is still called. */ -FOP_COND_D(sf, (float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status)= , 0)) -FOP_COND_D(ngle,float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status)) -FOP_COND_D(seq, float64_eq(fdt0, fdt1, &env->active_fpu.fp_status)) -FOP_COND_D(ngl, float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status) = || float64_eq(fdt0, fdt1, &env->active_fpu.fp_status)) -FOP_COND_D(lt, float64_lt(fdt0, fdt1, &env->active_fpu.fp_status)) -FOP_COND_D(nge, float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status) = || float64_lt(fdt0, fdt1, &env->active_fpu.fp_status)) -FOP_COND_D(le, float64_le(fdt0, fdt1, &env->active_fpu.fp_status)) -FOP_COND_D(ngt, float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status) = || float64_le(fdt0, fdt1, &env->active_fpu.fp_status)) +/* + * NOTE: the comma operator will make "cond" to eval to false, + * but float64_unordered_quiet() is still called. + */ +FOP_COND_D(f, (float64_unordered_quiet(fdt1, fdt0, + &env->active_fpu.fp_status), 0)) +FOP_COND_D(un, float64_unordered_quiet(fdt1, fdt0, + &env->active_fpu.fp_status)) +FOP_COND_D(eq, float64_eq_quiet(fdt0, fdt1, + &env->active_fpu.fp_status)) +FOP_COND_D(ueq, float64_unordered_quiet(fdt1, fdt0, + &env->active_fpu.fp_status) + || float64_eq_quiet(fdt0, fdt1, + &env->active_fpu.fp_status)) +FOP_COND_D(olt, float64_lt_quiet(fdt0, fdt1, + &env->active_fpu.fp_status)) +FOP_COND_D(ult, float64_unordered_quiet(fdt1, fdt0, + &env->active_fpu.fp_status) + || float64_lt_quiet(fdt0, fdt1, + &env->active_fpu.fp_status)) +FOP_COND_D(ole, float64_le_quiet(fdt0, fdt1, + &env->active_fpu.fp_status)) +FOP_COND_D(ule, float64_unordered_quiet(fdt1, fdt0, + &env->active_fpu.fp_status) + || float64_le_quiet(fdt0, fdt1, + &env->active_fpu.fp_status)) +/* + * NOTE: the comma operator will make "cond" to eval to false, + * but float64_unordered() is still called. + */ +FOP_COND_D(sf, (float64_unordered(fdt1, fdt0, + &env->active_fpu.fp_status), 0)) +FOP_COND_D(ngle, float64_unordered(fdt1, fdt0, + &env->active_fpu.fp_status)) +FOP_COND_D(seq, float64_eq(fdt0, fdt1, + &env->active_fpu.fp_status)) +FOP_COND_D(ngl, float64_unordered(fdt1, fdt0, + &env->active_fpu.fp_status) + || float64_eq(fdt0, fdt1, + &env->active_fpu.fp_status)) +FOP_COND_D(lt, float64_lt(fdt0, fdt1, + &env->active_fpu.fp_status)) +FOP_COND_D(nge, float64_unordered(fdt1, fdt0, + &env->active_fpu.fp_status) + || float64_lt(fdt0, fdt1, + &env->active_fpu.fp_status)) +FOP_COND_D(le, float64_le(fdt0, fdt1, + &env->active_fpu.fp_status)) +FOP_COND_D(ngt, float64_unordered(fdt1, fdt0, + &env->active_fpu.fp_status) + || float64_le(fdt0, fdt1, + &env->active_fpu.fp_status)) =20 #define FOP_COND_S(op, cond) \ void helper_cmp_s_ ## op(CPUMIPSState *env, uint32_t fst0, \ @@ -4119,26 +4246,58 @@ void helper_cmpabs_s_ ## op(CPUMIPSState *env, uint= 32_t fst0, \ CLEAR_FP_COND(cc, env->active_fpu); \ } =20 -/* NOTE: the comma operator will make "cond" to eval to false, - * but float32_unordered_quiet() is still called. */ -FOP_COND_S(f, (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_s= tatus), 0)) -FOP_COND_S(un, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_st= atus)) -FOP_COND_S(eq, float32_eq_quiet(fst0, fst1, &env->active_fpu.fp_status)) -FOP_COND_S(ueq, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_st= atus) || float32_eq_quiet(fst0, fst1, &env->active_fpu.fp_status)) -FOP_COND_S(olt, float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status)) -FOP_COND_S(ult, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_st= atus) || float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status)) -FOP_COND_S(ole, float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status)) -FOP_COND_S(ule, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_st= atus) || float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status)) -/* NOTE: the comma operator will make "cond" to eval to false, - * but float32_unordered() is still called. */ -FOP_COND_S(sf, (float32_unordered(fst1, fst0, &env->active_fpu.fp_status)= , 0)) -FOP_COND_S(ngle,float32_unordered(fst1, fst0, &env->active_fpu.fp_status)) -FOP_COND_S(seq, float32_eq(fst0, fst1, &env->active_fpu.fp_status)) -FOP_COND_S(ngl, float32_unordered(fst1, fst0, &env->active_fpu.fp_status) = || float32_eq(fst0, fst1, &env->active_fpu.fp_status)) -FOP_COND_S(lt, float32_lt(fst0, fst1, &env->active_fpu.fp_status)) -FOP_COND_S(nge, float32_unordered(fst1, fst0, &env->active_fpu.fp_status) = || float32_lt(fst0, fst1, &env->active_fpu.fp_status)) -FOP_COND_S(le, float32_le(fst0, fst1, &env->active_fpu.fp_status)) -FOP_COND_S(ngt, float32_unordered(fst1, fst0, &env->active_fpu.fp_status) = || float32_le(fst0, fst1, &env->active_fpu.fp_status)) +/* + * NOTE: the comma operator will make "cond" to eval to false, + * but float32_unordered_quiet() is still called. + */ +FOP_COND_S(f, (float32_unordered_quiet(fst1, fst0, + &env->active_fpu.fp_status), 0)) +FOP_COND_S(un, float32_unordered_quiet(fst1, fst0, + &env->active_fpu.fp_status)) +FOP_COND_S(eq, float32_eq_quiet(fst0, fst1, + &env->active_fpu.fp_status)) +FOP_COND_S(ueq, float32_unordered_quiet(fst1, fst0, + &env->active_fpu.fp_status) + || float32_eq_quiet(fst0, fst1, + &env->active_fpu.fp_status)) +FOP_COND_S(olt, float32_lt_quiet(fst0, fst1, + &env->active_fpu.fp_status)) +FOP_COND_S(ult, float32_unordered_quiet(fst1, fst0, + &env->active_fpu.fp_status) + || float32_lt_quiet(fst0, fst1, + &env->active_fpu.fp_status)) +FOP_COND_S(ole, float32_le_quiet(fst0, fst1, + &env->active_fpu.fp_status)) +FOP_COND_S(ule, float32_unordered_quiet(fst1, fst0, + &env->active_fpu.fp_status) + || float32_le_quiet(fst0, fst1, + &env->active_fpu.fp_status)) +/* + * NOTE: the comma operator will make "cond" to eval to false, + * but float32_unordered() is still called. + */ +FOP_COND_S(sf, (float32_unordered(fst1, fst0, + &env->active_fpu.fp_status), 0)) +FOP_COND_S(ngle, float32_unordered(fst1, fst0, + &env->active_fpu.fp_status)) +FOP_COND_S(seq, float32_eq(fst0, fst1, + &env->active_fpu.fp_status)) +FOP_COND_S(ngl, float32_unordered(fst1, fst0, + &env->active_fpu.fp_status) + || float32_eq(fst0, fst1, + &env->active_fpu.fp_status)) +FOP_COND_S(lt, float32_lt(fst0, fst1, + &env->active_fpu.fp_status)) +FOP_COND_S(nge, float32_unordered(fst1, fst0, + &env->active_fpu.fp_status) + || float32_lt(fst0, fst1, + &env->active_fpu.fp_status)) +FOP_COND_S(le, float32_le(fst0, fst1, + &env->active_fpu.fp_status)) +FOP_COND_S(ngt, float32_unordered(fst1, fst0, + &env->active_fpu.fp_status) + || float32_le(fst0, fst1, + &env->active_fpu.fp_status)) =20 #define FOP_COND_PS(op, condl, condh) \ void helper_cmp_ps_ ## op(CPUMIPSState *env, uint64_t fdt0, \ @@ -4184,42 +4343,102 @@ void helper_cmpabs_ps_ ## op(CPUMIPSState *env, ui= nt64_t fdt0, \ CLEAR_FP_COND(cc + 1, env->active_fpu); \ } =20 -/* NOTE: the comma operator will make "cond" to eval to false, - * but float32_unordered_quiet() is still called. */ -FOP_COND_PS(f, (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_= status), 0), - (float32_unordered_quiet(fsth1, fsth0, &env->active_fpu.f= p_status), 0)) -FOP_COND_PS(un, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_s= tatus), - float32_unordered_quiet(fsth1, fsth0, &env->active_fpu.fp= _status)) -FOP_COND_PS(eq, float32_eq_quiet(fst0, fst1, &env->active_fpu.fp_status), - float32_eq_quiet(fsth0, fsth1, &env->active_fpu.fp_status= )) -FOP_COND_PS(ueq, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_s= tatus) || float32_eq_quiet(fst0, fst1, &env->active_fpu.fp_status), - float32_unordered_quiet(fsth1, fsth0, &env->active_fpu.fp= _status) || float32_eq_quiet(fsth0, fsth1, &env->active_fpu.fp_status)) -FOP_COND_PS(olt, float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status), - float32_lt_quiet(fsth0, fsth1, &env->active_fpu.fp_status= )) -FOP_COND_PS(ult, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_s= tatus) || float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status), - float32_unordered_quiet(fsth1, fsth0, &env->active_fpu.fp= _status) || float32_lt_quiet(fsth0, fsth1, &env->active_fpu.fp_status)) -FOP_COND_PS(ole, float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status), - float32_le_quiet(fsth0, fsth1, &env->active_fpu.fp_status= )) -FOP_COND_PS(ule, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_s= tatus) || float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status), - float32_unordered_quiet(fsth1, fsth0, &env->active_fpu.fp= _status) || float32_le_quiet(fsth0, fsth1, &env->active_fpu.fp_status)) -/* NOTE: the comma operator will make "cond" to eval to false, - * but float32_unordered() is still called. */ -FOP_COND_PS(sf, (float32_unordered(fst1, fst0, &env->active_fpu.fp_status= ), 0), - (float32_unordered(fsth1, fsth0, &env->active_fpu.fp_stat= us), 0)) -FOP_COND_PS(ngle,float32_unordered(fst1, fst0, &env->active_fpu.fp_status), - float32_unordered(fsth1, fsth0, &env->active_fpu.fp_statu= s)) -FOP_COND_PS(seq, float32_eq(fst0, fst1, &env->active_fpu.fp_status), - float32_eq(fsth0, fsth1, &env->active_fpu.fp_status)) -FOP_COND_PS(ngl, float32_unordered(fst1, fst0, &env->active_fpu.fp_status)= || float32_eq(fst0, fst1, &env->active_fpu.fp_status), - float32_unordered(fsth1, fsth0, &env->active_fpu.fp_statu= s) || float32_eq(fsth0, fsth1, &env->active_fpu.fp_status)) -FOP_COND_PS(lt, float32_lt(fst0, fst1, &env->active_fpu.fp_status), - float32_lt(fsth0, fsth1, &env->active_fpu.fp_status)) -FOP_COND_PS(nge, float32_unordered(fst1, fst0, &env->active_fpu.fp_status)= || float32_lt(fst0, fst1, &env->active_fpu.fp_status), - float32_unordered(fsth1, fsth0, &env->active_fpu.fp_statu= s) || float32_lt(fsth0, fsth1, &env->active_fpu.fp_status)) -FOP_COND_PS(le, float32_le(fst0, fst1, &env->active_fpu.fp_status), - float32_le(fsth0, fsth1, &env->active_fpu.fp_status)) -FOP_COND_PS(ngt, float32_unordered(fst1, fst0, &env->active_fpu.fp_status)= || float32_le(fst0, fst1, &env->active_fpu.fp_status), - float32_unordered(fsth1, fsth0, &env->active_fpu.fp_statu= s) || float32_le(fsth0, fsth1, &env->active_fpu.fp_status)) +/* + * NOTE: the comma operator will make "cond" to eval to false, + * but float32_unordered_quiet() is still called. + */ +FOP_COND_PS(f, (float32_unordered_quiet(fst1, fst0, + &env->active_fpu.fp_status), 0), + (float32_unordered_quiet(fsth1, fsth0, + &env->active_fpu.fp_status), 0)) +FOP_COND_PS(un, float32_unordered_quiet(fst1, fst0, + &env->active_fpu.fp_status), + float32_unordered_quiet(fsth1, fsth0, + &env->active_fpu.fp_status)) +FOP_COND_PS(eq, float32_eq_quiet(fst0, fst1, + &env->active_fpu.fp_status), + float32_eq_quiet(fsth0, fsth1, + &env->active_fpu.fp_status)) +FOP_COND_PS(ueq, float32_unordered_quiet(fst1, fst0, + &env->active_fpu.fp_status) + || float32_eq_quiet(fst0, fst1, + &env->active_fpu.fp_status), + float32_unordered_quiet(fsth1, fsth0, + &env->active_fpu.fp_status) + || float32_eq_quiet(fsth0, fsth1, + &env->active_fpu.fp_status)) +FOP_COND_PS(olt, float32_lt_quiet(fst0, fst1, + &env->active_fpu.fp_status), + float32_lt_quiet(fsth0, fsth1, + &env->active_fpu.fp_status)) +FOP_COND_PS(ult, float32_unordered_quiet(fst1, fst0, + &env->active_fpu.fp_status) + || float32_lt_quiet(fst0, fst1, + &env->active_fpu.fp_status), + float32_unordered_quiet(fsth1, fsth0, + &env->active_fpu.fp_status) + || float32_lt_quiet(fsth0, fsth1, + &env->active_fpu.fp_status)) +FOP_COND_PS(ole, float32_le_quiet(fst0, fst1, + &env->active_fpu.fp_status), + float32_le_quiet(fsth0, fsth1, + &env->active_fpu.fp_status)) +FOP_COND_PS(ule, float32_unordered_quiet(fst1, fst0, + &env->active_fpu.fp_status) + || float32_le_quiet(fst0, fst1, + &env->active_fpu.fp_status), + float32_unordered_quiet(fsth1, fsth0, + &env->active_fpu.fp_status) + || float32_le_quiet(fsth0, fsth1, + &env->active_fpu.fp_status)) +/* + * NOTE: the comma operator will make "cond" to eval to false, + * but float32_unordered() is still called. + */ +FOP_COND_PS(sf, (float32_unordered(fst1, fst0, + &env->active_fpu.fp_status), 0), + (float32_unordered(fsth1, fsth0, + &env->active_fpu.fp_status), 0)) +FOP_COND_PS(ngle, float32_unordered(fst1, fst0, + &env->active_fpu.fp_status), + float32_unordered(fsth1, fsth0, + &env->active_fpu.fp_status)) +FOP_COND_PS(seq, float32_eq(fst0, fst1, + &env->active_fpu.fp_status), + float32_eq(fsth0, fsth1, + &env->active_fpu.fp_status)) +FOP_COND_PS(ngl, float32_unordered(fst1, fst0, + &env->active_fpu.fp_status) + || float32_eq(fst0, fst1, + &env->active_fpu.fp_status), + float32_unordered(fsth1, fsth0, + &env->active_fpu.fp_status) + || float32_eq(fsth0, fsth1, + &env->active_fpu.fp_status)) +FOP_COND_PS(lt, float32_lt(fst0, fst1, + &env->active_fpu.fp_status), + float32_lt(fsth0, fsth1, + &env->active_fpu.fp_status)) +FOP_COND_PS(nge, float32_unordered(fst1, fst0, + &env->active_fpu.fp_status) + || float32_lt(fst0, fst1, + &env->active_fpu.fp_status), + float32_unordered(fsth1, fsth0, + &env->active_fpu.fp_status) + || float32_lt(fsth0, fsth1, + &env->active_fpu.fp_status)) +FOP_COND_PS(le, float32_le(fst0, fst1, + &env->active_fpu.fp_status), + float32_le(fsth0, fsth1, + &env->active_fpu.fp_status)) +FOP_COND_PS(ngt, float32_unordered(fst1, fst0, + &env->active_fpu.fp_status) + || float32_le(fst0, fst1, + &env->active_fpu.fp_status), + float32_unordered(fsth1, fsth0, + &env->active_fpu.fp_status) + || float32_le(fsth0, fsth1, + &env->active_fpu.fp_status)) =20 /* R6 compare operations */ #define FOP_CONDN_D(op, cond) \ @@ -4236,46 +4455,86 @@ uint64_t helper_r6_cmp_d_ ## op(CPUMIPSState * env,= uint64_t fdt0, \ } \ } =20 -/* NOTE: the comma operator will make "cond" to eval to false, - * but float64_unordered_quiet() is still called. */ -FOP_CONDN_D(af, (float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_= status), 0)) -FOP_CONDN_D(un, (float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_= status))) -FOP_CONDN_D(eq, (float64_eq_quiet(fdt0, fdt1, &env->active_fpu.fp_status)= )) -FOP_CONDN_D(ueq, (float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_= status) - || float64_eq_quiet(fdt0, fdt1, &env->active_fpu.fp_stat= us))) -FOP_CONDN_D(lt, (float64_lt_quiet(fdt0, fdt1, &env->active_fpu.fp_status)= )) -FOP_CONDN_D(ult, (float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_= status) - || float64_lt_quiet(fdt0, fdt1, &env->active_fpu.fp_stat= us))) -FOP_CONDN_D(le, (float64_le_quiet(fdt0, fdt1, &env->active_fpu.fp_status)= )) -FOP_CONDN_D(ule, (float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_= status) - || float64_le_quiet(fdt0, fdt1, &env->active_fpu.fp_stat= us))) -/* NOTE: the comma operator will make "cond" to eval to false, - * but float64_unordered() is still called. */ -FOP_CONDN_D(saf, (float64_unordered(fdt1, fdt0, &env->active_fpu.fp_statu= s), 0)) -FOP_CONDN_D(sun, (float64_unordered(fdt1, fdt0, &env->active_fpu.fp_statu= s))) -FOP_CONDN_D(seq, (float64_eq(fdt0, fdt1, &env->active_fpu.fp_status))) -FOP_CONDN_D(sueq, (float64_unordered(fdt1, fdt0, &env->active_fpu.fp_statu= s) - || float64_eq(fdt0, fdt1, &env->active_fpu.fp_status))) -FOP_CONDN_D(slt, (float64_lt(fdt0, fdt1, &env->active_fpu.fp_status))) -FOP_CONDN_D(sult, (float64_unordered(fdt1, fdt0, &env->active_fpu.fp_statu= s) - || float64_lt(fdt0, fdt1, &env->active_fpu.fp_status))) -FOP_CONDN_D(sle, (float64_le(fdt0, fdt1, &env->active_fpu.fp_status))) -FOP_CONDN_D(sule, (float64_unordered(fdt1, fdt0, &env->active_fpu.fp_statu= s) - || float64_le(fdt0, fdt1, &env->active_fpu.fp_status))) -FOP_CONDN_D(or, (float64_le_quiet(fdt1, fdt0, &env->active_fpu.fp_status) - || float64_le_quiet(fdt0, fdt1, &env->active_fpu.fp_sta= tus))) -FOP_CONDN_D(une, (float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp= _status) - || float64_lt_quiet(fdt1, fdt0, &env->active_fpu.fp_sta= tus) - || float64_lt_quiet(fdt0, fdt1, &env->active_fpu.fp_sta= tus))) -FOP_CONDN_D(ne, (float64_lt_quiet(fdt1, fdt0, &env->active_fpu.fp_status) - || float64_lt_quiet(fdt0, fdt1, &env->active_fpu.fp_sta= tus))) -FOP_CONDN_D(sor, (float64_le(fdt1, fdt0, &env->active_fpu.fp_status) - || float64_le(fdt0, fdt1, &env->active_fpu.fp_status))) -FOP_CONDN_D(sune, (float64_unordered(fdt1, fdt0, &env->active_fpu.fp_statu= s) - || float64_lt(fdt1, fdt0, &env->active_fpu.fp_status) - || float64_lt(fdt0, fdt1, &env->active_fpu.fp_status))) -FOP_CONDN_D(sne, (float64_lt(fdt1, fdt0, &env->active_fpu.fp_status) - || float64_lt(fdt0, fdt1, &env->active_fpu.fp_status))) +/* + * NOTE: the comma operator will make "cond" to eval to false, + * but float64_unordered_quiet() is still called. + */ +FOP_CONDN_D(af, (float64_unordered_quiet(fdt1, fdt0, + &env->active_fpu.fp_status), 0)) +FOP_CONDN_D(un, (float64_unordered_quiet(fdt1, fdt0, + &env->active_fpu.fp_status))) +FOP_CONDN_D(eq, (float64_eq_quiet(fdt0, fdt1, + &env->active_fpu.fp_status))) +FOP_CONDN_D(ueq, (float64_unordered_quiet(fdt1, fdt0, + &env->active_fpu.fp_status) + || float64_eq_quiet(fdt0, fdt1, + &env->active_fpu.fp_status))) +FOP_CONDN_D(lt, (float64_lt_quiet(fdt0, fdt1, + &env->active_fpu.fp_status))) +FOP_CONDN_D(ult, (float64_unordered_quiet(fdt1, fdt0, + &env->active_fpu.fp_status) + || float64_lt_quiet(fdt0, fdt1, + &env->active_fpu.fp_status))) +FOP_CONDN_D(le, (float64_le_quiet(fdt0, fdt1, + &env->active_fpu.fp_status))) +FOP_CONDN_D(ule, (float64_unordered_quiet(fdt1, fdt0, + &env->active_fpu.fp_status) + || float64_le_quiet(fdt0, fdt1, + &env->active_fpu.fp_status))) +/* + * NOTE: the comma operator will make "cond" to eval to false, + * but float64_unordered() is still called.\ + */ +FOP_CONDN_D(saf, (float64_unordered(fdt1, fdt0, + &env->active_fpu.fp_status), 0)) +FOP_CONDN_D(sun, (float64_unordered(fdt1, fdt0, + &env->active_fpu.fp_status))) +FOP_CONDN_D(seq, (float64_eq(fdt0, fdt1, + &env->active_fpu.fp_status))) +FOP_CONDN_D(sueq, (float64_unordered(fdt1, fdt0, + &env->active_fpu.fp_status) + || float64_eq(fdt0, fdt1, + &env->active_fpu.fp_status))) +FOP_CONDN_D(slt, (float64_lt(fdt0, fdt1, + &env->active_fpu.fp_status))) +FOP_CONDN_D(sult, (float64_unordered(fdt1, fdt0, + &env->active_fpu.fp_status) + || float64_lt(fdt0, fdt1, + &env->active_fpu.fp_status))) +FOP_CONDN_D(sle, (float64_le(fdt0, fdt1, + &env->active_fpu.fp_status))) +FOP_CONDN_D(sule, (float64_unordered(fdt1, fdt0, + &env->active_fpu.fp_status) + || float64_le(fdt0, fdt1, + &env->active_fpu.fp_status))) +FOP_CONDN_D(or, (float64_le_quiet(fdt1, fdt0, + &env->active_fpu.fp_status) + || float64_le_quiet(fdt0, fdt1, + &env->active_fpu.fp_status))) +FOP_CONDN_D(une, (float64_unordered_quiet(fdt1, fdt0, + &env->active_fpu.fp_status) + || float64_lt_quiet(fdt1, fdt0, + &env->active_fpu.fp_status) + || float64_lt_quiet(fdt0, fdt1, + &env->active_fpu.fp_status))) +FOP_CONDN_D(ne, (float64_lt_quiet(fdt1, fdt0, + &env->active_fpu.fp_status) + || float64_lt_quiet(fdt0, fdt1, + &env->active_fpu.fp_status))) +FOP_CONDN_D(sor, (float64_le(fdt1, fdt0, + &env->active_fpu.fp_status) + || float64_le(fdt0, fdt1, + &env->active_fpu.fp_status))) +FOP_CONDN_D(sune, (float64_unordered(fdt1, fdt0, + &env->active_fpu.fp_status) + || float64_lt(fdt1, fdt0, + &env->active_fpu.fp_status) + || float64_lt(fdt0, fdt1, + &env->active_fpu.fp_status))) +FOP_CONDN_D(sne, (float64_lt(fdt1, fdt0, + &env->active_fpu.fp_status) + || float64_lt(fdt0, fdt1, + &env->active_fpu.fp_status))) =20 #define FOP_CONDN_S(op, cond) \ uint32_t helper_r6_cmp_s_ ## op(CPUMIPSState * env, uint32_t fst0, \ @@ -4291,46 +4550,86 @@ uint32_t helper_r6_cmp_s_ ## op(CPUMIPSState * env,= uint32_t fst0, \ } \ } =20 -/* NOTE: the comma operator will make "cond" to eval to false, - * but float32_unordered_quiet() is still called. */ -FOP_CONDN_S(af, (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp= _status), 0)) -FOP_CONDN_S(un, (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp= _status))) -FOP_CONDN_S(eq, (float32_eq_quiet(fst0, fst1, &env->active_fpu.fp_status= ))) -FOP_CONDN_S(ueq, (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp= _status) - || float32_eq_quiet(fst0, fst1, &env->active_fpu.fp_sta= tus))) -FOP_CONDN_S(lt, (float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status= ))) -FOP_CONDN_S(ult, (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp= _status) - || float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_sta= tus))) -FOP_CONDN_S(le, (float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status= ))) -FOP_CONDN_S(ule, (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp= _status) - || float32_le_quiet(fst0, fst1, &env->active_fpu.fp_sta= tus))) -/* NOTE: the comma operator will make "cond" to eval to false, - * but float32_unordered() is still called. */ -FOP_CONDN_S(saf, (float32_unordered(fst1, fst0, &env->active_fpu.fp_statu= s), 0)) -FOP_CONDN_S(sun, (float32_unordered(fst1, fst0, &env->active_fpu.fp_statu= s))) -FOP_CONDN_S(seq, (float32_eq(fst0, fst1, &env->active_fpu.fp_status))) -FOP_CONDN_S(sueq, (float32_unordered(fst1, fst0, &env->active_fpu.fp_statu= s) - || float32_eq(fst0, fst1, &env->active_fpu.fp_status))) -FOP_CONDN_S(slt, (float32_lt(fst0, fst1, &env->active_fpu.fp_status))) -FOP_CONDN_S(sult, (float32_unordered(fst1, fst0, &env->active_fpu.fp_statu= s) - || float32_lt(fst0, fst1, &env->active_fpu.fp_status))) -FOP_CONDN_S(sle, (float32_le(fst0, fst1, &env->active_fpu.fp_status))) -FOP_CONDN_S(sule, (float32_unordered(fst1, fst0, &env->active_fpu.fp_statu= s) - || float32_le(fst0, fst1, &env->active_fpu.fp_status))) -FOP_CONDN_S(or, (float32_le_quiet(fst1, fst0, &env->active_fpu.fp_status) - || float32_le_quiet(fst0, fst1, &env->active_fpu.fp_sta= tus))) -FOP_CONDN_S(une, (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp= _status) - || float32_lt_quiet(fst1, fst0, &env->active_fpu.fp_sta= tus) - || float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_sta= tus))) -FOP_CONDN_S(ne, (float32_lt_quiet(fst1, fst0, &env->active_fpu.fp_status) - || float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_sta= tus))) -FOP_CONDN_S(sor, (float32_le(fst1, fst0, &env->active_fpu.fp_status) - || float32_le(fst0, fst1, &env->active_fpu.fp_status))) -FOP_CONDN_S(sune, (float32_unordered(fst1, fst0, &env->active_fpu.fp_statu= s) - || float32_lt(fst1, fst0, &env->active_fpu.fp_status) - || float32_lt(fst0, fst1, &env->active_fpu.fp_status))) -FOP_CONDN_S(sne, (float32_lt(fst1, fst0, &env->active_fpu.fp_status) - || float32_lt(fst0, fst1, &env->active_fpu.fp_status))) +/* + * NOTE: the comma operator will make "cond" to eval to false, + * but float32_unordered_quiet() is still called. + */ +FOP_CONDN_S(af, (float32_unordered_quiet(fst1, fst0, + &env->active_fpu.fp_status), 0)) +FOP_CONDN_S(un, (float32_unordered_quiet(fst1, fst0, + &env->active_fpu.fp_status))) +FOP_CONDN_S(eq, (float32_eq_quiet(fst0, fst1, + &env->active_fpu.fp_status))) +FOP_CONDN_S(ueq, (float32_unordered_quiet(fst1, fst0, + &env->active_fpu.fp_status) + || float32_eq_quiet(fst0, fst1, + &env->active_fpu.fp_status))) +FOP_CONDN_S(lt, (float32_lt_quiet(fst0, fst1, + &env->active_fpu.fp_status))) +FOP_CONDN_S(ult, (float32_unordered_quiet(fst1, fst0, + &env->active_fpu.fp_status) + || float32_lt_quiet(fst0, fst1, + &env->active_fpu.fp_status))) +FOP_CONDN_S(le, (float32_le_quiet(fst0, fst1, + &env->active_fpu.fp_status))) +FOP_CONDN_S(ule, (float32_unordered_quiet(fst1, fst0, + &env->active_fpu.fp_status) + || float32_le_quiet(fst0, fst1, + &env->active_fpu.fp_status))) +/* + * NOTE: the comma operator will make "cond" to eval to false, + * but float32_unordered() is still called. + */ +FOP_CONDN_S(saf, (float32_unordered(fst1, fst0, + &env->active_fpu.fp_status), 0)) +FOP_CONDN_S(sun, (float32_unordered(fst1, fst0, + &env->active_fpu.fp_status))) +FOP_CONDN_S(seq, (float32_eq(fst0, fst1, + &env->active_fpu.fp_status))) +FOP_CONDN_S(sueq, (float32_unordered(fst1, fst0, + &env->active_fpu.fp_status) + || float32_eq(fst0, fst1, + &env->active_fpu.fp_status))) +FOP_CONDN_S(slt, (float32_lt(fst0, fst1, + &env->active_fpu.fp_status))) +FOP_CONDN_S(sult, (float32_unordered(fst1, fst0, + &env->active_fpu.fp_status) + || float32_lt(fst0, fst1, + &env->active_fpu.fp_status))) +FOP_CONDN_S(sle, (float32_le(fst0, fst1, + &env->active_fpu.fp_status))) +FOP_CONDN_S(sule, (float32_unordered(fst1, fst0, + &env->active_fpu.fp_status) + || float32_le(fst0, fst1, + &env->active_fpu.fp_status))) +FOP_CONDN_S(or, (float32_le_quiet(fst1, fst0, + &env->active_fpu.fp_status) + || float32_le_quiet(fst0, fst1, + &env->active_fpu.fp_status))) +FOP_CONDN_S(une, (float32_unordered_quiet(fst1, fst0, + &env->active_fpu.fp_status) + || float32_lt_quiet(fst1, fst0, + &env->active_fpu.fp_status) + || float32_lt_quiet(fst0, fst1, + &env->active_fpu.fp_status))) +FOP_CONDN_S(ne, (float32_lt_quiet(fst1, fst0, + &env->active_fpu.fp_status) + || float32_lt_quiet(fst0, fst1, + &env->active_fpu.fp_status))) +FOP_CONDN_S(sor, (float32_le(fst1, fst0, + &env->active_fpu.fp_status) + || float32_le(fst0, fst1, + &env->active_fpu.fp_status))) +FOP_CONDN_S(sune, (float32_unordered(fst1, fst0, + &env->active_fpu.fp_status) + || float32_lt(fst1, fst0, + &env->active_fpu.fp_status) + || float32_lt(fst0, fst1, + &env->active_fpu.fp_status))) +FOP_CONDN_S(sne, (float32_lt(fst1, fst0, + &env->active_fpu.fp_status) + || float32_lt(fst0, fst1, + &env->active_fpu.fp_status))) =20 /* MSA */ /* Data format min and max values */ @@ -4522,7 +4821,7 @@ void helper_msa_ld_d(CPUMIPSState *env, uint32_t wd, } =20 #define MSA_PAGESPAN(x) \ - ((((x) & ~TARGET_PAGE_MASK) + MSA_WRLEN/8 - 1) >=3D TARGET_PAGE_SI= ZE) + ((((x) & ~TARGET_PAGE_MASK) + MSA_WRLEN / 8 - 1) >=3D TARGET_PAGE_= SIZE) =20 static inline void ensure_writable_pages(CPUMIPSState *env, target_ulong addr, --=20 2.7.4 From nobody Sat May 4 18:24:35 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1569331896; cv=none; d=zoho.com; s=zohoarc; b=QqvI6rFaxzJ7cNqiPL9Opb+DMtv+oQFLVct9IcVmQ2iWvCwVsVcWd+pTQ19VhA5FBa/E9/KBJyde9ELjV1g/IVESONRBRDsSmfkQXUKyvaSNsAGOb+q9Nw0WwonGeH6cpQszFL8dTHOj+/gyTvzp0+j5xoWjfmdTbcrRgAav4aU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1569331896; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=TDj2aDKXj0ZWPQ5iH6+doFlxtl2Nu8qe1Ki1KGWrQX8=; b=OQbFRFKl6ZANHyiqPyLAayW9vc+NdP/7EsLdEMqZep+DEYdxDvVyXk0kI3ELGS7tJV40D15nCrqq+vEXBOluAoGnJveQ5PnObshcwKxBo1s340Lo3tlcpWxgRfwgVahgGbRg2DBUYcF9DnmMMM9zxMdKHXvCwPuC3XAo5FQEPmA= ARC-Authentication-Results: i=1; mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1569331896604547.5375632503941; Tue, 24 Sep 2019 06:31:36 -0700 (PDT) Received: from localhost ([::1]:45702 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iCkul-0001VX-21 for importer@patchew.org; Tue, 24 Sep 2019 09:31:35 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:58541) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iCkrN-0007z5-NU for qemu-devel@nongnu.org; Tue, 24 Sep 2019 09:28:08 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iCkrJ-0001EZ-UH for qemu-devel@nongnu.org; Tue, 24 Sep 2019 09:28:03 -0400 Received: from mx2.rt-rk.com ([89.216.37.149]:46874 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1iCkrG-0001Aa-UT for qemu-devel@nongnu.org; Tue, 24 Sep 2019 09:28:00 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id C32021A22AB; Tue, 24 Sep 2019 15:26:48 +0200 (CEST) Received: from rtrkw774-lin.domain.local (rtrkw774-lin.domain.local [10.10.13.43]) by mail.rt-rk.com (Postfix) with ESMTPSA id 94B411A221B; Tue, 24 Sep 2019 15:26:48 +0200 (CEST) X-Virus-Scanned: amavisd-new at rt-rk.com From: Aleksandar Markovic To: qemu-devel@nongnu.org Subject: [PATCH 06/11] target/mips: Clean up translate.c Date: Tue, 24 Sep 2019 15:26:37 +0200 Message-Id: <1569331602-2586-7-git-send-email-aleksandar.markovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1569331602-2586-1-git-send-email-aleksandar.markovic@rt-rk.com> References: <1569331602-2586-1-git-send-email-aleksandar.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 89.216.37.149 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: arikalo@wavecomp.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Aleksandar Markovic Mostly fix errors and warnings reported by 'checkpatch.pl -f'. Signed-off-by: Aleksandar Markovic Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/mips/translate.c | 30 ++++++++++++++++++------------ 1 file changed, 18 insertions(+), 12 deletions(-) diff --git a/target/mips/translate.c b/target/mips/translate.c index f211995..cc5af2a 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -7118,7 +7118,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int= reg, int sel) tcg_gen_andi_tl(arg, arg, ~0xffff); register_name =3D "BadInstrX"; break; - default: + default: goto cp0_unimplemented; } break; @@ -7545,7 +7545,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int= reg, int sel) case CP0_REG31__KSCRATCH6: CP0_CHECK(ctx->kscrexist & (1 << sel)); tcg_gen_ld_tl(arg, cpu_env, - offsetof(CPUMIPSState, CP0_KScratch[sel-2])); + offsetof(CPUMIPSState, CP0_KScratch[sel - 2])); tcg_gen_ext32s_tl(arg, arg); register_name =3D "KScratch"; break; @@ -8295,7 +8295,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int= reg, int sel) case CP0_REG31__KSCRATCH6: CP0_CHECK(ctx->kscrexist & (1 << sel)); tcg_gen_st_tl(arg, cpu_env, - offsetof(CPUMIPSState, CP0_KScratch[sel-2])); + offsetof(CPUMIPSState, CP0_KScratch[sel - 2])); register_name =3D "KScratch"; break; default: @@ -8387,17 +8387,20 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, = int reg, int sel) break; case CP0_REG01__YQMASK: CP0_CHECK(ctx->insn_flags & ASE_MT); - tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_YQMask)= ); + tcg_gen_ld_tl(arg, cpu_env, + offsetof(CPUMIPSState, CP0_YQMask)); register_name =3D "YQMask"; break; case CP0_REG01__VPESCHEDULE: CP0_CHECK(ctx->insn_flags & ASE_MT); - tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_VPESche= dule)); + tcg_gen_ld_tl(arg, cpu_env, + offsetof(CPUMIPSState, CP0_VPESchedule)); register_name =3D "VPESchedule"; break; case CP0_REG01__VPESCHEFBACK: CP0_CHECK(ctx->insn_flags & ASE_MT); - tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_VPESche= FBack)); + tcg_gen_ld_tl(arg, cpu_env, + offsetof(CPUMIPSState, CP0_VPEScheFBack)); register_name =3D "VPEScheFBack"; break; case CP0_REG01__VPEOPT: @@ -8412,7 +8415,8 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, in= t reg, int sel) case CP0_REGISTER_02: switch (sel) { case CP0_REG02__ENTRYLO0: - tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_EntryLo= 0)); + tcg_gen_ld_tl(arg, cpu_env, + offsetof(CPUMIPSState, CP0_EntryLo0)); register_name =3D "EntryLo0"; break; case CP0_REG02__TCSTATUS: @@ -8756,7 +8760,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, in= t reg, int sel) gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config5)); register_name =3D "Config5"; break; - /* 6,7 are implementation dependent */ + /* 6,7 are implementation dependent */ case CP0_REG16__CONFIG6: gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config6)); register_name =3D "Config6"; @@ -8837,7 +8841,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, in= t reg, int sel) } break; case CP0_REGISTER_21: - /* Officially reserved, but sel 0 is used for R1x000 framemask */ + /* Officially reserved, but sel 0 is used for R1x000 framemask */ CP0_CHECK(!(ctx->insn_flags & ISA_MIPS32R6)); switch (sel) { case 0: @@ -9022,7 +9026,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, in= t reg, int sel) case CP0_REG31__KSCRATCH6: CP0_CHECK(ctx->kscrexist & (1 << sel)); tcg_gen_ld_tl(arg, cpu_env, - offsetof(CPUMIPSState, CP0_KScratch[sel-2])); + offsetof(CPUMIPSState, CP0_KScratch[sel - 2])); register_name =3D "KScratch"; break; default: @@ -9112,12 +9116,14 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, = int reg, int sel) break; case CP0_REG01__VPESCHEDULE: CP0_CHECK(ctx->insn_flags & ASE_MT); - tcg_gen_st_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_VPESche= dule)); + tcg_gen_st_tl(arg, cpu_env, + offsetof(CPUMIPSState, CP0_VPESchedule)); register_name =3D "VPESchedule"; break; case CP0_REG01__VPESCHEFBACK: CP0_CHECK(ctx->insn_flags & ASE_MT); - tcg_gen_st_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_VPESche= FBack)); + tcg_gen_st_tl(arg, cpu_env, + offsetof(CPUMIPSState, CP0_VPEScheFBack)); register_name =3D "VPEScheFBack"; break; case CP0_REG01__VPEOPT: --=20 2.7.4 From nobody Sat May 4 18:24:35 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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Tue, 24 Sep 2019 09:28:00 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id CA46F1A22BC; Tue, 24 Sep 2019 15:26:48 +0200 (CEST) Received: from rtrkw774-lin.domain.local (rtrkw774-lin.domain.local [10.10.13.43]) by mail.rt-rk.com (Postfix) with ESMTPSA id 9B7D31A2266; Tue, 24 Sep 2019 15:26:48 +0200 (CEST) X-Virus-Scanned: amavisd-new at rt-rk.com From: Aleksandar Markovic To: qemu-devel@nongnu.org Subject: [PATCH 07/11] target/mips: msa: Split helpers for . Date: Tue, 24 Sep 2019 15:26:38 +0200 Message-Id: <1569331602-2586-8-git-send-email-aleksandar.markovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1569331602-2586-1-git-send-email-aleksandar.markovic@rt-rk.com> References: <1569331602-2586-1-git-send-email-aleksandar.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 89.216.37.149 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: arikalo@wavecomp.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Aleksandar Markovic Achieves clearer code and slightly better performance. Signed-off-by: Aleksandar Markovic --- target/mips/helper.h | 14 +++- target/mips/msa_helper.c | 170 +++++++++++++++++++++++++++++++++++++++----= ---- target/mips/translate.c | 30 ++++++++- 3 files changed, 181 insertions(+), 33 deletions(-) diff --git a/target/mips/helper.h b/target/mips/helper.h index 51f0e1c..d709083 100644 --- a/target/mips/helper.h +++ b/target/mips/helper.h @@ -777,6 +777,18 @@ DEF_HELPER_FLAGS_3(wrdsp, 0, void, tl, tl, env) DEF_HELPER_FLAGS_2(rddsp, 0, tl, tl, env) =20 /* MIPS SIMD Architecture */ + +DEF_HELPER_3(msa_nloc_b, void, env, i32, i32) +DEF_HELPER_3(msa_nloc_h, void, env, i32, i32) +DEF_HELPER_3(msa_nloc_w, void, env, i32, i32) +DEF_HELPER_3(msa_nloc_d, void, env, i32, i32) + +DEF_HELPER_3(msa_nlzc_b, void, env, i32, i32) +DEF_HELPER_3(msa_nlzc_h, void, env, i32, i32) +DEF_HELPER_3(msa_nlzc_w, void, env, i32, i32) +DEF_HELPER_3(msa_nlzc_d, void, env, i32, i32) + + DEF_HELPER_4(msa_andi_b, void, env, i32, i32, i32) DEF_HELPER_4(msa_ori_b, void, env, i32, i32, i32) DEF_HELPER_4(msa_nori_b, void, env, i32, i32, i32) @@ -935,8 +947,6 @@ DEF_HELPER_4(msa_bmz_v, void, env, i32, i32, i32) DEF_HELPER_4(msa_bsel_v, void, env, i32, i32, i32) DEF_HELPER_4(msa_fill_df, void, env, i32, i32, i32) DEF_HELPER_4(msa_pcnt_df, void, env, i32, i32, i32) -DEF_HELPER_4(msa_nloc_df, void, env, i32, i32, i32) -DEF_HELPER_4(msa_nlzc_df, void, env, i32, i32, i32) =20 DEF_HELPER_4(msa_copy_s_b, void, env, i32, i32, i32) DEF_HELPER_4(msa_copy_s_h, void, env, i32, i32, i32) diff --git a/target/mips/msa_helper.c b/target/mips/msa_helper.c index f24061e..8c27c1b 100644 --- a/target/mips/msa_helper.c +++ b/target/mips/msa_helper.c @@ -65,7 +65,147 @@ * +---------------+------------------------------------------------------= ----+ */ =20 -/* TODO: insert Bit Count group helpers here */ +static inline int64_t msa_nlzc_df(uint32_t df, int64_t arg) +{ + uint64_t x, y; + int n, c; + + x =3D UNSIGNED(arg, df); + n =3D DF_BITS(df); + c =3D DF_BITS(df) / 2; + + do { + y =3D x >> c; + if (y !=3D 0) { + n =3D n - c; + x =3D y; + } + c =3D c >> 1; + } while (c !=3D 0); + + return n - x; +} + +static inline int64_t msa_nloc_df(uint32_t df, int64_t arg) +{ + return msa_nlzc_df(df, UNSIGNED((~arg), df)); +} + +void helper_msa_nloc_b(CPUMIPSState *env, uint32_t wd, uint32_t ws) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + + pwd->b[0] =3D msa_nloc_df(DF_BYTE, pws->b[0]); + pwd->b[1] =3D msa_nloc_df(DF_BYTE, pws->b[1]); + pwd->b[2] =3D msa_nloc_df(DF_BYTE, pws->b[2]); + pwd->b[3] =3D msa_nloc_df(DF_BYTE, pws->b[3]); + pwd->b[4] =3D msa_nloc_df(DF_BYTE, pws->b[4]); + pwd->b[5] =3D msa_nloc_df(DF_BYTE, pws->b[5]); + pwd->b[6] =3D msa_nloc_df(DF_BYTE, pws->b[6]); + pwd->b[7] =3D msa_nloc_df(DF_BYTE, pws->b[7]); + pwd->b[8] =3D msa_nloc_df(DF_BYTE, pws->b[8]); + pwd->b[9] =3D msa_nloc_df(DF_BYTE, pws->b[9]); + pwd->b[10] =3D msa_nloc_df(DF_BYTE, pws->b[10]); + pwd->b[11] =3D msa_nloc_df(DF_BYTE, pws->b[11]); + pwd->b[12] =3D msa_nloc_df(DF_BYTE, pws->b[12]); + pwd->b[13] =3D msa_nloc_df(DF_BYTE, pws->b[13]); + pwd->b[14] =3D msa_nloc_df(DF_BYTE, pws->b[14]); + pwd->b[15] =3D msa_nloc_df(DF_BYTE, pws->b[15]); +} + +void helper_msa_nloc_h(CPUMIPSState *env, uint32_t wd, uint32_t ws) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + + pwd->h[0] =3D msa_nloc_df(DF_HALF, pws->h[0]); + pwd->h[1] =3D msa_nloc_df(DF_HALF, pws->h[1]); + pwd->h[2] =3D msa_nloc_df(DF_HALF, pws->h[2]); + pwd->h[3] =3D msa_nloc_df(DF_HALF, pws->h[3]); + pwd->h[4] =3D msa_nloc_df(DF_HALF, pws->h[4]); + pwd->h[5] =3D msa_nloc_df(DF_HALF, pws->h[5]); + pwd->h[6] =3D msa_nloc_df(DF_HALF, pws->h[6]); + pwd->h[7] =3D msa_nloc_df(DF_HALF, pws->h[7]); +} + +void helper_msa_nloc_w(CPUMIPSState *env, uint32_t wd, uint32_t ws) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + + pwd->w[0] =3D msa_nloc_df(DF_WORD, pws->w[0]); + pwd->w[1] =3D msa_nloc_df(DF_WORD, pws->w[1]); + pwd->w[2] =3D msa_nloc_df(DF_WORD, pws->w[2]); + pwd->w[3] =3D msa_nloc_df(DF_WORD, pws->w[3]); +} + +void helper_msa_nloc_d(CPUMIPSState *env, uint32_t wd, uint32_t ws) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + + pwd->d[0] =3D msa_nloc_df(DF_DOUBLE, pws->d[0]); + pwd->d[1] =3D msa_nloc_df(DF_DOUBLE, pws->d[1]); +} + +void helper_msa_nlzc_b(CPUMIPSState *env, uint32_t wd, uint32_t ws) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + + pwd->b[0] =3D msa_nlzc_df(DF_BYTE, pws->b[0]); + pwd->b[1] =3D msa_nlzc_df(DF_BYTE, pws->b[1]); + pwd->b[2] =3D msa_nlzc_df(DF_BYTE, pws->b[2]); + pwd->b[3] =3D msa_nlzc_df(DF_BYTE, pws->b[3]); + pwd->b[4] =3D msa_nlzc_df(DF_BYTE, pws->b[4]); + pwd->b[5] =3D msa_nlzc_df(DF_BYTE, pws->b[5]); + pwd->b[6] =3D msa_nlzc_df(DF_BYTE, pws->b[6]); + pwd->b[7] =3D msa_nlzc_df(DF_BYTE, pws->b[7]); + pwd->b[8] =3D msa_nlzc_df(DF_BYTE, pws->b[8]); + pwd->b[9] =3D msa_nlzc_df(DF_BYTE, pws->b[9]); + pwd->b[10] =3D msa_nlzc_df(DF_BYTE, pws->b[10]); + pwd->b[11] =3D msa_nlzc_df(DF_BYTE, pws->b[11]); + pwd->b[12] =3D msa_nlzc_df(DF_BYTE, pws->b[12]); + pwd->b[13] =3D msa_nlzc_df(DF_BYTE, pws->b[13]); + pwd->b[14] =3D msa_nlzc_df(DF_BYTE, pws->b[14]); + pwd->b[15] =3D msa_nlzc_df(DF_BYTE, pws->b[15]); +} + +void helper_msa_nlzc_h(CPUMIPSState *env, uint32_t wd, uint32_t ws) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + + pwd->h[0] =3D msa_nlzc_df(DF_HALF, pws->h[0]); + pwd->h[1] =3D msa_nlzc_df(DF_HALF, pws->h[1]); + pwd->h[2] =3D msa_nlzc_df(DF_HALF, pws->h[2]); + pwd->h[3] =3D msa_nlzc_df(DF_HALF, pws->h[3]); + pwd->h[4] =3D msa_nlzc_df(DF_HALF, pws->h[4]); + pwd->h[5] =3D msa_nlzc_df(DF_HALF, pws->h[5]); + pwd->h[6] =3D msa_nlzc_df(DF_HALF, pws->h[6]); + pwd->h[7] =3D msa_nlzc_df(DF_HALF, pws->h[7]); +} + +void helper_msa_nlzc_w(CPUMIPSState *env, uint32_t wd, uint32_t ws) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + + pwd->w[0] =3D msa_nlzc_df(DF_WORD, pws->w[0]); + pwd->w[1] =3D msa_nlzc_df(DF_WORD, pws->w[1]); + pwd->w[2] =3D msa_nlzc_df(DF_WORD, pws->w[2]); + pwd->w[3] =3D msa_nlzc_df(DF_WORD, pws->w[3]); +} + +void helper_msa_nlzc_d(CPUMIPSState *env, uint32_t wd, uint32_t ws) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + + pwd->d[0] =3D msa_nlzc_df(DF_DOUBLE, pws->d[0]); + pwd->d[1] =3D msa_nlzc_df(DF_DOUBLE, pws->d[1]); +} =20 =20 /* @@ -2524,32 +2664,6 @@ static inline int64_t msa_pcnt_df(uint32_t df, int64= _t arg) return x; } =20 -static inline int64_t msa_nlzc_df(uint32_t df, int64_t arg) -{ - uint64_t x, y; - int n, c; - - x =3D UNSIGNED(arg, df); - n =3D DF_BITS(df); - c =3D DF_BITS(df) / 2; - - do { - y =3D x >> c; - if (y !=3D 0) { - n =3D n - c; - x =3D y; - } - c =3D c >> 1; - } while (c !=3D 0); - - return n - x; -} - -static inline int64_t msa_nloc_df(uint32_t df, int64_t arg) -{ - return msa_nlzc_df(df, UNSIGNED((~arg), df)); -} - void helper_msa_fill_df(CPUMIPSState *env, uint32_t df, uint32_t wd, uint32_t rs) { @@ -2633,8 +2747,6 @@ void helper_msa_ ## func ## _df(CPUMIPSState *env, ui= nt32_t df, \ } \ } =20 -MSA_UNOP_DF(nlzc) -MSA_UNOP_DF(nloc) MSA_UNOP_DF(pcnt) #undef MSA_UNOP_DF =20 diff --git a/target/mips/translate.c b/target/mips/translate.c index cc5af2a..6de4609 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -28962,10 +28962,36 @@ static void gen_msa_2r(CPUMIPSState *env, DisasCo= ntext *ctx) gen_helper_msa_pcnt_df(cpu_env, tdf, twd, tws); break; case OPC_NLOC_df: - gen_helper_msa_nloc_df(cpu_env, tdf, twd, tws); + switch (df) { + case DF_BYTE: + gen_helper_msa_nloc_b(cpu_env, twd, tws); + break; + case DF_HALF: + gen_helper_msa_nloc_h(cpu_env, twd, tws); + break; + case DF_WORD: + gen_helper_msa_nloc_w(cpu_env, twd, tws); + break; + case DF_DOUBLE: + gen_helper_msa_nloc_d(cpu_env, twd, tws); + break; + } break; case OPC_NLZC_df: - gen_helper_msa_nlzc_df(cpu_env, tdf, twd, tws); + switch (df) { + case DF_BYTE: + gen_helper_msa_nlzc_b(cpu_env, twd, tws); + break; + case DF_HALF: + gen_helper_msa_nlzc_h(cpu_env, twd, tws); + break; + case DF_WORD: + gen_helper_msa_nlzc_w(cpu_env, twd, tws); + break; + case DF_DOUBLE: + gen_helper_msa_nlzc_d(cpu_env, twd, tws); + break; + } break; default: MIPS_INVAL("MSA instruction"); --=20 2.7.4 From nobody Sat May 4 18:24:35 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1569335382; cv=none; d=zoho.com; s=zohoarc; b=PJixoKelHEaDS3aAnVj8qIHNnP4Y4BC9UqOO4LM+3SjhWzXhF4z1KlVYfXBuhalHecUYjTuAXGQNZo6nmc8U9bZHhGiUTM0c85n8CUyR4KYrYcSWwDwABNgE5GiqXJgr/GsoqveIpdF//yV5KbeRlP/k/W3Db5JWkcH4WhjWcRM= ARC-Message-Signature: i=1; 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Tue, 24 Sep 2019 10:29:40 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:58543) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iCkrN-0007zA-Q9 for qemu-devel@nongnu.org; Tue, 24 Sep 2019 09:28:08 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iCkrK-0001Ek-0H for qemu-devel@nongnu.org; Tue, 24 Sep 2019 09:28:05 -0400 Received: from mx2.rt-rk.com ([89.216.37.149]:46878 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1iCkrG-0001Al-U0 for qemu-devel@nongnu.org; Tue, 24 Sep 2019 09:28:00 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id DB1561A221B; Tue, 24 Sep 2019 15:26:48 +0200 (CEST) Received: from rtrkw774-lin.domain.local (rtrkw774-lin.domain.local [10.10.13.43]) by mail.rt-rk.com (Postfix) with ESMTPSA id A759C1A1D45; Tue, 24 Sep 2019 15:26:48 +0200 (CEST) X-Virus-Scanned: amavisd-new at rt-rk.com From: Aleksandar Markovic To: qemu-devel@nongnu.org Subject: [PATCH 08/11] target/mips: msa: Split helpers for PCNT. Date: Tue, 24 Sep 2019 15:26:39 +0200 Message-Id: <1569331602-2586-9-git-send-email-aleksandar.markovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1569331602-2586-1-git-send-email-aleksandar.markovic@rt-rk.com> References: <1569331602-2586-1-git-send-email-aleksandar.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 89.216.37.149 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: arikalo@wavecomp.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Aleksandar Markovic Achieves clearer code and slightly better performance. Signed-off-by: Aleksandar Markovic --- target/mips/helper.h | 6 +- target/mips/msa_helper.c | 143 ++++++++++++++++++++++++-------------------= ---- target/mips/translate.c | 19 ++++++- 3 files changed, 95 insertions(+), 73 deletions(-) diff --git a/target/mips/helper.h b/target/mips/helper.h index d709083..18e4c7a 100644 --- a/target/mips/helper.h +++ b/target/mips/helper.h @@ -788,6 +788,11 @@ DEF_HELPER_3(msa_nlzc_h, void, env, i32, i32) DEF_HELPER_3(msa_nlzc_w, void, env, i32, i32) DEF_HELPER_3(msa_nlzc_d, void, env, i32, i32) =20 +DEF_HELPER_3(msa_pcnt_b, void, env, i32, i32) +DEF_HELPER_3(msa_pcnt_h, void, env, i32, i32) +DEF_HELPER_3(msa_pcnt_w, void, env, i32, i32) +DEF_HELPER_3(msa_pcnt_d, void, env, i32, i32) + =20 DEF_HELPER_4(msa_andi_b, void, env, i32, i32, i32) DEF_HELPER_4(msa_ori_b, void, env, i32, i32, i32) @@ -946,7 +951,6 @@ DEF_HELPER_4(msa_bmnz_v, void, env, i32, i32, i32) DEF_HELPER_4(msa_bmz_v, void, env, i32, i32, i32) DEF_HELPER_4(msa_bsel_v, void, env, i32, i32, i32) DEF_HELPER_4(msa_fill_df, void, env, i32, i32, i32) -DEF_HELPER_4(msa_pcnt_df, void, env, i32, i32, i32) =20 DEF_HELPER_4(msa_copy_s_b, void, env, i32, i32, i32) DEF_HELPER_4(msa_copy_s_h, void, env, i32, i32, i32) diff --git a/target/mips/msa_helper.c b/target/mips/msa_helper.c index 8c27c1b..fe27efc 100644 --- a/target/mips/msa_helper.c +++ b/target/mips/msa_helper.c @@ -207,6 +207,80 @@ void helper_msa_nlzc_d(CPUMIPSState *env, uint32_t wd,= uint32_t ws) pwd->d[1] =3D msa_nlzc_df(DF_DOUBLE, pws->d[1]); } =20 +static inline int64_t msa_pcnt_df(uint32_t df, int64_t arg) +{ + uint64_t x; + + x =3D UNSIGNED(arg, df); + + x =3D (x & 0x5555555555555555ULL) + ((x >> 1) & 0x5555555555555555ULL= ); + x =3D (x & 0x3333333333333333ULL) + ((x >> 2) & 0x3333333333333333ULL= ); + x =3D (x & 0x0F0F0F0F0F0F0F0FULL) + ((x >> 4) & 0x0F0F0F0F0F0F0F0FULL= ); + x =3D (x & 0x00FF00FF00FF00FFULL) + ((x >> 8) & 0x00FF00FF00FF00FFULL= ); + x =3D (x & 0x0000FFFF0000FFFFULL) + ((x >> 16) & 0x0000FFFF0000FFFFULL= ); + x =3D (x & 0x00000000FFFFFFFFULL) + ((x >> 32)); + + return x; +} + +void helper_msa_pcnt_b(CPUMIPSState *env, uint32_t wd, uint32_t ws) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + + pwd->b[0] =3D msa_pcnt_df(DF_BYTE, pws->b[0]); + pwd->b[1] =3D msa_pcnt_df(DF_BYTE, pws->b[1]); + pwd->b[2] =3D msa_pcnt_df(DF_BYTE, pws->b[2]); + pwd->b[3] =3D msa_pcnt_df(DF_BYTE, pws->b[3]); + pwd->b[4] =3D msa_pcnt_df(DF_BYTE, pws->b[4]); + pwd->b[5] =3D msa_pcnt_df(DF_BYTE, pws->b[5]); + pwd->b[6] =3D msa_pcnt_df(DF_BYTE, pws->b[6]); + pwd->b[7] =3D msa_pcnt_df(DF_BYTE, pws->b[7]); + pwd->b[8] =3D msa_pcnt_df(DF_BYTE, pws->b[8]); + pwd->b[9] =3D msa_pcnt_df(DF_BYTE, pws->b[9]); + pwd->b[10] =3D msa_pcnt_df(DF_BYTE, pws->b[10]); + pwd->b[11] =3D msa_pcnt_df(DF_BYTE, pws->b[11]); + pwd->b[12] =3D msa_pcnt_df(DF_BYTE, pws->b[12]); + pwd->b[13] =3D msa_pcnt_df(DF_BYTE, pws->b[13]); + pwd->b[14] =3D msa_pcnt_df(DF_BYTE, pws->b[14]); + pwd->b[15] =3D msa_pcnt_df(DF_BYTE, pws->b[15]); +} + +void helper_msa_pcnt_h(CPUMIPSState *env, uint32_t wd, uint32_t ws) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + + pwd->h[0] =3D msa_pcnt_df(DF_HALF, pws->h[0]); + pwd->h[1] =3D msa_pcnt_df(DF_HALF, pws->h[1]); + pwd->h[2] =3D msa_pcnt_df(DF_HALF, pws->h[2]); + pwd->h[3] =3D msa_pcnt_df(DF_HALF, pws->h[3]); + pwd->h[4] =3D msa_pcnt_df(DF_HALF, pws->h[4]); + pwd->h[5] =3D msa_pcnt_df(DF_HALF, pws->h[5]); + pwd->h[6] =3D msa_pcnt_df(DF_HALF, pws->h[6]); + pwd->h[7] =3D msa_pcnt_df(DF_HALF, pws->h[7]); +} + +void helper_msa_pcnt_w(CPUMIPSState *env, uint32_t wd, uint32_t ws) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + + pwd->w[0] =3D msa_pcnt_df(DF_WORD, pws->w[0]); + pwd->w[1] =3D msa_pcnt_df(DF_WORD, pws->w[1]); + pwd->w[2] =3D msa_pcnt_df(DF_WORD, pws->w[2]); + pwd->w[3] =3D msa_pcnt_df(DF_WORD, pws->w[3]); +} + +void helper_msa_pcnt_d(CPUMIPSState *env, uint32_t wd, uint32_t ws) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + + pwd->d[0] =3D msa_pcnt_df(DF_DOUBLE, pws->d[0]); + pwd->d[1] =3D msa_pcnt_df(DF_DOUBLE, pws->d[1]); +} + =20 /* * Bit Move @@ -2648,22 +2722,6 @@ void helper_msa_move_v(CPUMIPSState *env, uint32_t w= d, uint32_t ws) msa_move_v(pwd, pws); } =20 -static inline int64_t msa_pcnt_df(uint32_t df, int64_t arg) -{ - uint64_t x; - - x =3D UNSIGNED(arg, df); - - x =3D (x & 0x5555555555555555ULL) + ((x >> 1) & 0x5555555555555555ULL= ); - x =3D (x & 0x3333333333333333ULL) + ((x >> 2) & 0x3333333333333333ULL= ); - x =3D (x & 0x0F0F0F0F0F0F0F0FULL) + ((x >> 4) & 0x0F0F0F0F0F0F0F0FULL= ); - x =3D (x & 0x00FF00FF00FF00FFULL) + ((x >> 8) & 0x00FF00FF00FF00FFULL= ); - x =3D (x & 0x0000FFFF0000FFFFULL) + ((x >> 16) & 0x0000FFFF0000FFFFULL= ); - x =3D (x & 0x00000000FFFFFFFFULL) + ((x >> 32)); - - return x; -} - void helper_msa_fill_df(CPUMIPSState *env, uint32_t df, uint32_t wd, uint32_t rs) { @@ -2696,59 +2754,6 @@ void helper_msa_fill_df(CPUMIPSState *env, uint32_t = df, uint32_t wd, } } =20 -#define MSA_UNOP_DF(func) \ -void helper_msa_ ## func ## _df(CPUMIPSState *env, uint32_t df, \ - uint32_t wd, uint32_t ws) \ -{ \ - wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); \ - wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); \ - \ - switch (df) { \ - case DF_BYTE: \ - pwd->b[0] =3D msa_ ## func ## _df(df, pws->b[0]); \ - pwd->b[1] =3D msa_ ## func ## _df(df, pws->b[1]); \ - pwd->b[2] =3D msa_ ## func ## _df(df, pws->b[2]); \ - pwd->b[3] =3D msa_ ## func ## _df(df, pws->b[3]); \ - pwd->b[4] =3D msa_ ## func ## _df(df, pws->b[4]); \ - pwd->b[5] =3D msa_ ## func ## _df(df, pws->b[5]); \ - pwd->b[6] =3D msa_ ## func ## _df(df, pws->b[6]); \ - pwd->b[7] =3D msa_ ## func ## _df(df, pws->b[7]); \ - pwd->b[8] =3D msa_ ## func ## _df(df, pws->b[8]); \ - pwd->b[9] =3D msa_ ## func ## _df(df, pws->b[9]); \ - pwd->b[10] =3D msa_ ## func ## _df(df, pws->b[10]); \ - pwd->b[11] =3D msa_ ## func ## _df(df, pws->b[11]); \ - pwd->b[12] =3D msa_ ## func ## _df(df, pws->b[12]); \ - pwd->b[13] =3D msa_ ## func ## _df(df, pws->b[13]); \ - pwd->b[14] =3D msa_ ## func ## _df(df, pws->b[14]); \ - pwd->b[15] =3D msa_ ## func ## _df(df, pws->b[15]); \ - break; \ - case DF_HALF: \ - pwd->h[0] =3D msa_ ## func ## _df(df, pws->h[0]); \ - pwd->h[1] =3D msa_ ## func ## _df(df, pws->h[1]); \ - pwd->h[2] =3D msa_ ## func ## _df(df, pws->h[2]); \ - pwd->h[3] =3D msa_ ## func ## _df(df, pws->h[3]); \ - pwd->h[4] =3D msa_ ## func ## _df(df, pws->h[4]); \ - pwd->h[5] =3D msa_ ## func ## _df(df, pws->h[5]); \ - pwd->h[6] =3D msa_ ## func ## _df(df, pws->h[6]); \ - pwd->h[7] =3D msa_ ## func ## _df(df, pws->h[7]); \ - break; \ - case DF_WORD: \ - pwd->w[0] =3D msa_ ## func ## _df(df, pws->w[0]); \ - pwd->w[1] =3D msa_ ## func ## _df(df, pws->w[1]); \ - pwd->w[2] =3D msa_ ## func ## _df(df, pws->w[2]); \ - pwd->w[3] =3D msa_ ## func ## _df(df, pws->w[3]); \ - break; \ - case DF_DOUBLE: \ - pwd->d[0] =3D msa_ ## func ## _df(df, pws->d[0]); \ - pwd->d[1] =3D msa_ ## func ## _df(df, pws->d[1]); \ - break; \ - default: \ - assert(0); \ - } \ -} - -MSA_UNOP_DF(pcnt) -#undef MSA_UNOP_DF =20 #define FLOAT_ONE32 make_float32(0x3f8 << 20) #define FLOAT_ONE64 make_float64(0x3ffULL << 52) diff --git a/target/mips/translate.c b/target/mips/translate.c index 6de4609..0d06ba9 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -28958,9 +28958,6 @@ static void gen_msa_2r(CPUMIPSState *env, DisasCont= ext *ctx) #endif gen_helper_msa_fill_df(cpu_env, tdf, twd, tws); /* trs */ break; - case OPC_PCNT_df: - gen_helper_msa_pcnt_df(cpu_env, tdf, twd, tws); - break; case OPC_NLOC_df: switch (df) { case DF_BYTE: @@ -28993,6 +28990,22 @@ static void gen_msa_2r(CPUMIPSState *env, DisasCon= text *ctx) break; } break; + case OPC_PCNT_df: + switch (df) { + case DF_BYTE: + gen_helper_msa_pcnt_b(cpu_env, twd, tws); + break; + case DF_HALF: + gen_helper_msa_pcnt_h(cpu_env, twd, tws); + break; + case DF_WORD: + gen_helper_msa_pcnt_w(cpu_env, twd, tws); + break; + case DF_DOUBLE: + gen_helper_msa_pcnt_d(cpu_env, twd, tws); + break; + } + break; default: MIPS_INVAL("MSA instruction"); generate_exception_end(ctx, EXCP_RI); --=20 2.7.4 From nobody Sat May 4 18:24:35 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; 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Tue, 24 Sep 2019 15:26:48 +0200 (CEST) X-Virus-Scanned: amavisd-new at rt-rk.com From: Aleksandar Markovic To: qemu-devel@nongnu.org Subject: [PATCH 09/11] target/mips: msa: Split helpers for BINS. Date: Tue, 24 Sep 2019 15:26:40 +0200 Message-Id: <1569331602-2586-10-git-send-email-aleksandar.markovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1569331602-2586-1-git-send-email-aleksandar.markovic@rt-rk.com> References: <1569331602-2586-1-git-send-email-aleksandar.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 89.216.37.149 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: arikalo@wavecomp.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Aleksandar Markovic Achieves clearer code and slightly better performance. Signed-off-by: Aleksandar Markovic --- target/mips/helper.h | 10 +++ target/mips/msa_helper.c | 198 +++++++++++++++++++++++++++++++++++++++----= ---- target/mips/translate.c | 38 +++++++-- 3 files changed, 206 insertions(+), 40 deletions(-) diff --git a/target/mips/helper.h b/target/mips/helper.h index 18e4c7a..9349482 100644 --- a/target/mips/helper.h +++ b/target/mips/helper.h @@ -793,6 +793,16 @@ DEF_HELPER_3(msa_pcnt_h, void, env, i32, i32) DEF_HELPER_3(msa_pcnt_w, void, env, i32, i32) DEF_HELPER_3(msa_pcnt_d, void, env, i32, i32) =20 +DEF_HELPER_4(msa_binsl_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_binsl_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_binsl_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_binsl_d, void, env, i32, i32, i32) + +DEF_HELPER_4(msa_binsr_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_binsr_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_binsr_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_binsr_d, void, env, i32, i32, i32) + =20 DEF_HELPER_4(msa_andi_b, void, env, i32, i32, i32) DEF_HELPER_4(msa_ori_b, void, env, i32, i32, i32) diff --git a/target/mips/msa_helper.c b/target/mips/msa_helper.c index fe27efc..7c9da99 100644 --- a/target/mips/msa_helper.c +++ b/target/mips/msa_helper.c @@ -301,7 +301,170 @@ void helper_msa_pcnt_d(CPUMIPSState *env, uint32_t wd= , uint32_t ws) * +---------------+------------------------------------------------------= ----+ */ =20 -/* TODO: insert Bit Move group helpers here */ +/* Data format bit position and unsigned values */ +#define BIT_POSITION(x, df) ((uint64_t)(x) % DF_BITS(df)) + +static inline int64_t msa_binsl_df(uint32_t df, + int64_t dest, int64_t arg1, int64_t arg= 2) +{ + uint64_t u_arg1 =3D UNSIGNED(arg1, df); + uint64_t u_dest =3D UNSIGNED(dest, df); + int32_t sh_d =3D BIT_POSITION(arg2, df) + 1; + int32_t sh_a =3D DF_BITS(df) - sh_d; + if (sh_d =3D=3D DF_BITS(df)) { + return u_arg1; + } else { + return UNSIGNED(UNSIGNED(u_dest << sh_d, df) >> sh_d, df) | + UNSIGNED(UNSIGNED(u_arg1 >> sh_a, df) << sh_a, df); + } +} + +void helper_msa_binsl_b(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); + + pwd->b[0] =3D msa_binsl_df(DF_BYTE, pwd->b[0], pws->b[0], pwt->b[0]); + pwd->b[1] =3D msa_binsl_df(DF_BYTE, pwd->b[0], pws->b[0], pwt->b[1]); + pwd->b[2] =3D msa_binsl_df(DF_BYTE, pwd->b[0], pws->b[0], pwt->b[2]); + pwd->b[3] =3D msa_binsl_df(DF_BYTE, pwd->b[0], pws->b[0], pwt->b[3]); + pwd->b[4] =3D msa_binsl_df(DF_BYTE, pwd->b[0], pws->b[0], pwt->b[4]); + pwd->b[5] =3D msa_binsl_df(DF_BYTE, pwd->b[0], pws->b[0], pwt->b[5]); + pwd->b[6] =3D msa_binsl_df(DF_BYTE, pwd->b[0], pws->b[0], pwt->b[6]); + pwd->b[7] =3D msa_binsl_df(DF_BYTE, pwd->b[0], pws->b[0], pwt->b[7]); + pwd->b[8] =3D msa_binsl_df(DF_BYTE, pwd->b[0], pws->b[0], pwt->b[8]); + pwd->b[9] =3D msa_binsl_df(DF_BYTE, pwd->b[0], pws->b[0], pwt->b[9]); + pwd->b[10] =3D msa_binsl_df(DF_BYTE, pwd->b[0], pws->b[0], pwt->b[10]= ); + pwd->b[11] =3D msa_binsl_df(DF_BYTE, pwd->b[0], pws->b[0], pwt->b[11]= ); + pwd->b[12] =3D msa_binsl_df(DF_BYTE, pwd->b[0], pws->b[0], pwt->b[12]= ); + pwd->b[13] =3D msa_binsl_df(DF_BYTE, pwd->b[0], pws->b[0], pwt->b[13]= ); + pwd->b[14] =3D msa_binsl_df(DF_BYTE, pwd->b[0], pws->b[0], pwt->b[14]= ); + pwd->b[15] =3D msa_binsl_df(DF_BYTE, pwd->b[0], pws->b[0], pwt->b[15]= ); +} + +void helper_msa_binsl_h(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); + + pwd->h[0] =3D msa_binsl_df(DF_HALF, pwd->h[0], pws->h[0], pwt->h[0]); + pwd->h[1] =3D msa_binsl_df(DF_HALF, pwd->h[0], pws->h[0], pwt->h[1]); + pwd->h[2] =3D msa_binsl_df(DF_HALF, pwd->h[0], pws->h[0], pwt->h[2]); + pwd->h[3] =3D msa_binsl_df(DF_HALF, pwd->h[0], pws->h[0], pwt->h[3]); + pwd->h[4] =3D msa_binsl_df(DF_HALF, pwd->h[0], pws->h[0], pwt->h[4]); + pwd->h[5] =3D msa_binsl_df(DF_HALF, pwd->h[0], pws->h[0], pwt->h[5]); + pwd->h[6] =3D msa_binsl_df(DF_HALF, pwd->h[0], pws->h[0], pwt->h[6]); + pwd->h[7] =3D msa_binsl_df(DF_HALF, pwd->h[0], pws->h[0], pwt->h[7]); +} + +void helper_msa_binsl_w(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); + + pwd->w[0] =3D msa_binsl_df(DF_WORD, pwd->w[0], pws->w[0], pwt->w[0]); + pwd->w[1] =3D msa_binsl_df(DF_WORD, pwd->w[0], pws->w[0], pwt->w[1]); + pwd->w[2] =3D msa_binsl_df(DF_WORD, pwd->w[0], pws->w[0], pwt->w[2]); + pwd->w[3] =3D msa_binsl_df(DF_WORD, pwd->w[0], pws->w[0], pwt->w[3]); +} + +void helper_msa_binsl_d(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); + + pwd->d[0] =3D msa_binsl_df(DF_DOUBLE, pwd->d[0], pws->d[0], pwt->d[0= ]); + pwd->d[1] =3D msa_binsl_df(DF_DOUBLE, pwd->d[0], pws->d[0], pwt->d[1= ]); +} + +static inline int64_t msa_binsr_df(uint32_t df, + int64_t dest, int64_t arg1, int64_t arg= 2) +{ + uint64_t u_arg1 =3D UNSIGNED(arg1, df); + uint64_t u_dest =3D UNSIGNED(dest, df); + int32_t sh_d =3D BIT_POSITION(arg2, df) + 1; + int32_t sh_a =3D DF_BITS(df) - sh_d; + if (sh_d =3D=3D DF_BITS(df)) { + return u_arg1; + } else { + return UNSIGNED(UNSIGNED(u_dest >> sh_d, df) << sh_d, df) | + UNSIGNED(UNSIGNED(u_arg1 << sh_a, df) >> sh_a, df); + } +} + +void helper_msa_binsr_b(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); + + pwd->b[0] =3D msa_binsr_df(DF_BYTE, pwd->b[0], pws->b[0], pwt->b[0]); + pwd->b[1] =3D msa_binsr_df(DF_BYTE, pwd->b[0], pws->b[0], pwt->b[1]); + pwd->b[2] =3D msa_binsr_df(DF_BYTE, pwd->b[0], pws->b[0], pwt->b[2]); + pwd->b[3] =3D msa_binsr_df(DF_BYTE, pwd->b[0], pws->b[0], pwt->b[3]); + pwd->b[4] =3D msa_binsr_df(DF_BYTE, pwd->b[0], pws->b[0], pwt->b[4]); + pwd->b[5] =3D msa_binsr_df(DF_BYTE, pwd->b[0], pws->b[0], pwt->b[5]); + pwd->b[6] =3D msa_binsr_df(DF_BYTE, pwd->b[0], pws->b[0], pwt->b[6]); + pwd->b[7] =3D msa_binsr_df(DF_BYTE, pwd->b[0], pws->b[0], pwt->b[7]); + pwd->b[8] =3D msa_binsr_df(DF_BYTE, pwd->b[0], pws->b[0], pwt->b[8]); + pwd->b[9] =3D msa_binsr_df(DF_BYTE, pwd->b[0], pws->b[0], pwt->b[9]); + pwd->b[10] =3D msa_binsr_df(DF_BYTE, pwd->b[0], pws->b[0], pwt->b[10]= ); + pwd->b[11] =3D msa_binsr_df(DF_BYTE, pwd->b[0], pws->b[0], pwt->b[11]= ); + pwd->b[12] =3D msa_binsr_df(DF_BYTE, pwd->b[0], pws->b[0], pwt->b[12]= ); + pwd->b[13] =3D msa_binsr_df(DF_BYTE, pwd->b[0], pws->b[0], pwt->b[13]= ); + pwd->b[14] =3D msa_binsr_df(DF_BYTE, pwd->b[0], pws->b[0], pwt->b[14]= ); + pwd->b[15] =3D msa_binsr_df(DF_BYTE, pwd->b[0], pws->b[0], pwt->b[15]= ); +} + +void helper_msa_binsr_h(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); + + pwd->h[0] =3D msa_binsr_df(DF_HALF, pwd->h[0], pws->h[0], pwt->h[0]); + pwd->h[1] =3D msa_binsr_df(DF_HALF, pwd->h[0], pws->h[0], pwt->h[1]); + pwd->h[2] =3D msa_binsr_df(DF_HALF, pwd->h[0], pws->h[0], pwt->h[2]); + pwd->h[3] =3D msa_binsr_df(DF_HALF, pwd->h[0], pws->h[0], pwt->h[3]); + pwd->h[4] =3D msa_binsr_df(DF_HALF, pwd->h[0], pws->h[0], pwt->h[4]); + pwd->h[5] =3D msa_binsr_df(DF_HALF, pwd->h[0], pws->h[0], pwt->h[5]); + pwd->h[6] =3D msa_binsr_df(DF_HALF, pwd->h[0], pws->h[0], pwt->h[6]); + pwd->h[7] =3D msa_binsr_df(DF_HALF, pwd->h[0], pws->h[0], pwt->h[7]); +} + +void helper_msa_binsr_w(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); + + pwd->w[0] =3D msa_binsr_df(DF_WORD, pwd->w[0], pws->w[0], pwt->w[0]); + pwd->w[1] =3D msa_binsr_df(DF_WORD, pwd->w[0], pws->w[0], pwt->w[1]); + pwd->w[2] =3D msa_binsr_df(DF_WORD, pwd->w[0], pws->w[0], pwt->w[2]); + pwd->w[3] =3D msa_binsr_df(DF_WORD, pwd->w[0], pws->w[0], pwt->w[3]); +} + +void helper_msa_binsr_d(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); + + pwd->d[0] =3D msa_binsr_df(DF_DOUBLE, pwd->d[0], pws->d[0], pwt->d[0= ]); + pwd->d[1] =3D msa_binsr_df(DF_DOUBLE, pwd->d[0], pws->d[0], pwt->d[1= ]); +} =20 =20 /* @@ -1023,9 +1186,6 @@ void helper_msa_ldi_df(CPUMIPSState *env, uint32_t df= , uint32_t wd, } } =20 -/* Data format bit position and unsigned values */ -#define BIT_POSITION(x, df) ((uint64_t)(x) % DF_BITS(df)) - static inline int64_t msa_sll_df(uint32_t df, int64_t arg1, int64_t arg2) { int32_t b_arg2 =3D BIT_POSITION(arg2, df); @@ -1064,36 +1224,6 @@ static inline int64_t msa_bneg_df(uint32_t df, int64= _t arg1, int64_t arg2) return UNSIGNED(arg1 ^ (1LL << b_arg2), df); } =20 -static inline int64_t msa_binsl_df(uint32_t df, int64_t dest, int64_t arg1, - int64_t arg2) -{ - uint64_t u_arg1 =3D UNSIGNED(arg1, df); - uint64_t u_dest =3D UNSIGNED(dest, df); - int32_t sh_d =3D BIT_POSITION(arg2, df) + 1; - int32_t sh_a =3D DF_BITS(df) - sh_d; - if (sh_d =3D=3D DF_BITS(df)) { - return u_arg1; - } else { - return UNSIGNED(UNSIGNED(u_dest << sh_d, df) >> sh_d, df) | - UNSIGNED(UNSIGNED(u_arg1 >> sh_a, df) << sh_a, df); - } -} - -static inline int64_t msa_binsr_df(uint32_t df, int64_t dest, int64_t arg1, - int64_t arg2) -{ - uint64_t u_arg1 =3D UNSIGNED(arg1, df); - uint64_t u_dest =3D UNSIGNED(dest, df); - int32_t sh_d =3D BIT_POSITION(arg2, df) + 1; - int32_t sh_a =3D DF_BITS(df) - sh_d; - if (sh_d =3D=3D DF_BITS(df)) { - return u_arg1; - } else { - return UNSIGNED(UNSIGNED(u_dest >> sh_d, df) << sh_d, df) | - UNSIGNED(UNSIGNED(u_arg1 << sh_a, df) >> sh_a, df); - } -} - static inline int64_t msa_sat_s_df(uint32_t df, int64_t arg, uint32_t m) { return arg < M_MIN_INT(m + 1) ? M_MIN_INT(m + 1) : diff --git a/target/mips/translate.c b/target/mips/translate.c index 0d06ba9..6080c72 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -28386,6 +28386,38 @@ static void gen_msa_3r(CPUMIPSState *env, DisasCon= text *ctx) TCGv_i32 twt =3D tcg_const_i32(wt); =20 switch (MASK_MSA_3R(ctx->opcode)) { + case OPC_BINSL_df: + switch (df) { + case DF_BYTE: + gen_helper_msa_binsl_b(cpu_env, twd, tws, twt); + break; + case DF_HALF: + gen_helper_msa_binsl_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_binsl_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_binsl_d(cpu_env, twd, tws, twt); + break; + } + break; + case OPC_BINSR_df: + switch (df) { + case DF_BYTE: + gen_helper_msa_binsr_b(cpu_env, twd, tws, twt); + break; + case DF_HALF: + gen_helper_msa_binsr_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_binsr_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_binsr_d(cpu_env, twd, tws, twt); + break; + } + break; case OPC_SLL_df: gen_helper_msa_sll_df(cpu_env, tdf, twd, tws, twt); break; @@ -28515,9 +28547,6 @@ static void gen_msa_3r(CPUMIPSState *env, DisasCont= ext *ctx) case OPC_ILVR_df: gen_helper_msa_ilvr_df(cpu_env, tdf, twd, tws, twt); break; - case OPC_BINSL_df: - gen_helper_msa_binsl_df(cpu_env, tdf, twd, tws, twt); - break; case OPC_MAX_A_df: gen_helper_msa_max_a_df(cpu_env, tdf, twd, tws, twt); break; @@ -28530,9 +28559,6 @@ static void gen_msa_3r(CPUMIPSState *env, DisasCont= ext *ctx) case OPC_ILVEV_df: gen_helper_msa_ilvev_df(cpu_env, tdf, twd, tws, twt); break; - case OPC_BINSR_df: - gen_helper_msa_binsr_df(cpu_env, tdf, twd, tws, twt); - break; case OPC_MIN_A_df: gen_helper_msa_min_a_df(cpu_env, tdf, twd, tws, twt); break; --=20 2.7.4 From nobody Sat May 4 18:24:35 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Tue, 24 Sep 2019 15:26:48 +0200 (CEST) X-Virus-Scanned: amavisd-new at rt-rk.com From: Aleksandar Markovic To: qemu-devel@nongnu.org Subject: [PATCH 10/11] target/mips: msa: Unroll loops and demacro .V Date: Tue, 24 Sep 2019 15:26:41 +0200 Message-Id: <1569331602-2586-11-git-send-email-aleksandar.markovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1569331602-2586-1-git-send-email-aleksandar.markovic@rt-rk.com> References: <1569331602-2586-1-git-send-email-aleksandar.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 89.216.37.149 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: arikalo@wavecomp.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Aleksandar Markovic Achieves clearer code and slightly better performance. Signed-off-by: Aleksandar Markovic --- target/mips/helper.h | 7 +++--- target/mips/msa_helper.c | 63 ++++++++++++++++++++++++++++++--------------= ---- 2 files changed, 43 insertions(+), 27 deletions(-) diff --git a/target/mips/helper.h b/target/mips/helper.h index 9349482..27544a1 100644 --- a/target/mips/helper.h +++ b/target/mips/helper.h @@ -803,6 +803,10 @@ DEF_HELPER_4(msa_binsr_h, void, env, i32, i32, i32) DEF_HELPER_4(msa_binsr_w, void, env, i32, i32, i32) DEF_HELPER_4(msa_binsr_d, void, env, i32, i32, i32) =20 +DEF_HELPER_4(msa_bmnz_v, void, env, i32, i32, i32) +DEF_HELPER_4(msa_bmz_v, void, env, i32, i32, i32) +DEF_HELPER_4(msa_bsel_v, void, env, i32, i32, i32) + =20 DEF_HELPER_4(msa_andi_b, void, env, i32, i32, i32) DEF_HELPER_4(msa_ori_b, void, env, i32, i32, i32) @@ -957,9 +961,6 @@ DEF_HELPER_4(msa_and_v, void, env, i32, i32, i32) DEF_HELPER_4(msa_or_v, void, env, i32, i32, i32) DEF_HELPER_4(msa_nor_v, void, env, i32, i32, i32) DEF_HELPER_4(msa_xor_v, void, env, i32, i32, i32) -DEF_HELPER_4(msa_bmnz_v, void, env, i32, i32, i32) -DEF_HELPER_4(msa_bmz_v, void, env, i32, i32, i32) -DEF_HELPER_4(msa_bsel_v, void, env, i32, i32, i32) DEF_HELPER_4(msa_fill_df, void, env, i32, i32, i32) =20 DEF_HELPER_4(msa_copy_s_b, void, env, i32, i32, i32) diff --git a/target/mips/msa_helper.c b/target/mips/msa_helper.c index 7c9da99..eda675a 100644 --- a/target/mips/msa_helper.c +++ b/target/mips/msa_helper.c @@ -466,6 +466,42 @@ void helper_msa_binsr_d(CPUMIPSState *env, pwd->d[1] =3D msa_binsr_df(DF_DOUBLE, pwd->d[0], pws->d[0], pwt->d[1= ]); } =20 +void helper_msa_bmnz_v(CPUMIPSState *env, uint32_t wd, uint32_t ws, uint32= _t wt) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); + + pwd->d[0] =3D UNSIGNED( = \ + ((pwd->d[0] & (~pwt->d[0])) | (pws->d[0] & pwt->d[0])), DF_DOUBLE); + pwd->d[1] =3D UNSIGNED( = \ + ((pwd->d[1] & (~pwt->d[1])) | (pws->d[1] & pwt->d[1])), DF_DOUBLE); +} + +void helper_msa_bmz_v(CPUMIPSState *env, uint32_t wd, uint32_t ws, uint32_= t wt) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); + + pwd->d[0] =3D UNSIGNED( = \ + ((pwd->d[0] & pwt->d[0]) | (pws->d[0] & (~pwt->d[0]))), DF_DOUBLE); + pwd->d[1] =3D UNSIGNED( = \ + ((pwd->d[1] & pwt->d[1]) | (pws->d[1] & (~pwt->d[1]))), DF_DOUBLE); +} + +void helper_msa_bsel_v(CPUMIPSState *env, uint32_t wd, uint32_t ws, uint32= _t wt) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); + + pwd->d[0] =3D UNSIGNED( = \ + (pws->d[0] & (~pwd->d[0])) | (pwt->d[0] & pwd->d[0]), DF_DOUBLE); + pwd->d[1] =3D UNSIGNED( = \ + (pws->d[1] & (~pwd->d[1])) | (pwt->d[1] & pwd->d[1]), DF_DOUBLE); +} + =20 /* * Bit Set @@ -946,6 +982,9 @@ MSA_FN_IMM8(bmzi_b, pwd->b[i], MSA_FN_IMM8(bseli_b, pwd->b[i], BIT_SELECT(pwd->b[i], pws->b[i], i8, DF_BYTE)) =20 +#undef BIT_SELECT +#undef BIT_MOVE_IF_ZERO +#undef BIT_MOVE_IF_NOT_ZERO #undef MSA_FN_IMM8 =20 #define SHF_POS(i, imm) (((i) & 0xfc) + (((imm) >> (2 * ((i) & 0x03))) & 0= x03)) @@ -980,30 +1019,6 @@ void helper_msa_shf_df(CPUMIPSState *env, uint32_t df= , uint32_t wd, msa_move_v(pwd, pwx); } =20 -#define MSA_FN_VECTOR(FUNC, DEST, OPERATION) \ -void helper_msa_ ## FUNC(CPUMIPSState *env, uint32_t wd, uint32_t ws, \ - uint32_t wt) \ -{ \ - wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); \ - wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); \ - wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); \ - uint32_t i; \ - for (i =3D 0; i < DF_ELEMENTS(DF_DOUBLE); i++) { \ - DEST =3D OPERATION; \ - } \ -} - -MSA_FN_VECTOR(bmnz_v, pwd->d[i], - BIT_MOVE_IF_NOT_ZERO(pwd->d[i], pws->d[i], pwt->d[i], DF_DOUBLE)) -MSA_FN_VECTOR(bmz_v, pwd->d[i], - BIT_MOVE_IF_ZERO(pwd->d[i], pws->d[i], pwt->d[i], DF_DOUBLE)) -MSA_FN_VECTOR(bsel_v, pwd->d[i], - BIT_SELECT(pwd->d[i], pws->d[i], pwt->d[i], DF_DOUBLE)) -#undef BIT_MOVE_IF_NOT_ZERO -#undef BIT_MOVE_IF_ZERO -#undef BIT_SELECT -#undef MSA_FN_VECTOR - void helper_msa_and_v(CPUMIPSState *env, uint32_t wd, uint32_t ws, uint32_= t wt) { wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); --=20 2.7.4 From nobody Sat May 4 18:24:35 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; 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Tue, 24 Sep 2019 15:26:48 +0200 (CEST) X-Virus-Scanned: amavisd-new at rt-rk.com From: Aleksandar Markovic To: qemu-devel@nongnu.org Subject: [PATCH 11/11] target/mips: msa: Split helpers for B. Date: Tue, 24 Sep 2019 15:26:42 +0200 Message-Id: <1569331602-2586-12-git-send-email-aleksandar.markovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1569331602-2586-1-git-send-email-aleksandar.markovic@rt-rk.com> References: <1569331602-2586-1-git-send-email-aleksandar.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 89.216.37.149 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: arikalo@wavecomp.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Aleksandar Markovic Achieves clearer code and slightly better performance. Signed-off-by: Aleksandar Markovic --- target/mips/helper.h | 18 +++- target/mips/msa_helper.c | 227 ++++++++++++++++++++++++++++++++++++++++++-= ---- target/mips/translate.c | 57 ++++++++++-- 3 files changed, 267 insertions(+), 35 deletions(-) diff --git a/target/mips/helper.h b/target/mips/helper.h index 27544a1..1411e0e 100644 --- a/target/mips/helper.h +++ b/target/mips/helper.h @@ -807,6 +807,21 @@ DEF_HELPER_4(msa_bmnz_v, void, env, i32, i32, i32) DEF_HELPER_4(msa_bmz_v, void, env, i32, i32, i32) DEF_HELPER_4(msa_bsel_v, void, env, i32, i32, i32) =20 +DEF_HELPER_4(msa_bclr_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_bclr_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_bclr_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_bclr_d, void, env, i32, i32, i32) + +DEF_HELPER_4(msa_bneg_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_bneg_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_bneg_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_bneg_d, void, env, i32, i32, i32) + +DEF_HELPER_4(msa_bset_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_bset_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_bset_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_bset_d, void, env, i32, i32, i32) + =20 DEF_HELPER_4(msa_andi_b, void, env, i32, i32, i32) DEF_HELPER_4(msa_ori_b, void, env, i32, i32, i32) @@ -846,9 +861,6 @@ DEF_HELPER_5(msa_srlri_df, void, env, i32, i32, i32, i3= 2) DEF_HELPER_5(msa_sll_df, void, env, i32, i32, i32, i32) DEF_HELPER_5(msa_sra_df, void, env, i32, i32, i32, i32) DEF_HELPER_5(msa_srl_df, void, env, i32, i32, i32, i32) -DEF_HELPER_5(msa_bclr_df, void, env, i32, i32, i32, i32) -DEF_HELPER_5(msa_bset_df, void, env, i32, i32, i32, i32) -DEF_HELPER_5(msa_bneg_df, void, env, i32, i32, i32, i32) DEF_HELPER_5(msa_binsl_df, void, env, i32, i32, i32, i32) DEF_HELPER_5(msa_binsr_df, void, env, i32, i32, i32, i32) DEF_HELPER_5(msa_addv_df, void, env, i32, i32, i32, i32) diff --git a/target/mips/msa_helper.c b/target/mips/msa_helper.c index eda675a..9e4f275 100644 --- a/target/mips/msa_helper.c +++ b/target/mips/msa_helper.c @@ -523,7 +523,210 @@ void helper_msa_bsel_v(CPUMIPSState *env, uint32_t wd= , uint32_t ws, uint32_t wt) * +---------------+------------------------------------------------------= ----+ */ =20 -/* TODO: insert Bit Set group helpers here */ +static inline int64_t msa_bclr_df(uint32_t df, int64_t arg1, int64_t arg2) +{ + int32_t b_arg2 =3D BIT_POSITION(arg2, df); + return UNSIGNED(arg1 & (~(1LL << b_arg2)), df); +} + +void helper_msa_bclr_b(CPUMIPSState *env, uint32_t wd, uint32_t ws, uint32= _t wt) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); + + pwd->b[0] =3D msa_bclr_df(DF_BYTE, pws->b[0], pwt->b[0]); + pwd->b[1] =3D msa_bclr_df(DF_BYTE, pws->b[0], pwt->b[1]); + pwd->b[2] =3D msa_bclr_df(DF_BYTE, pws->b[0], pwt->b[2]); + pwd->b[3] =3D msa_bclr_df(DF_BYTE, pws->b[0], pwt->b[3]); + pwd->b[4] =3D msa_bclr_df(DF_BYTE, pws->b[0], pwt->b[4]); + pwd->b[5] =3D msa_bclr_df(DF_BYTE, pws->b[0], pwt->b[5]); + pwd->b[6] =3D msa_bclr_df(DF_BYTE, pws->b[0], pwt->b[6]); + pwd->b[7] =3D msa_bclr_df(DF_BYTE, pws->b[0], pwt->b[7]); + pwd->b[8] =3D msa_bclr_df(DF_BYTE, pws->b[0], pwt->b[8]); + pwd->b[9] =3D msa_bclr_df(DF_BYTE, pws->b[0], pwt->b[9]); + pwd->b[10] =3D msa_bclr_df(DF_BYTE, pws->b[0], pwt->b[10]); + pwd->b[11] =3D msa_bclr_df(DF_BYTE, pws->b[0], pwt->b[11]); + pwd->b[12] =3D msa_bclr_df(DF_BYTE, pws->b[0], pwt->b[12]); + pwd->b[13] =3D msa_bclr_df(DF_BYTE, pws->b[0], pwt->b[13]); + pwd->b[14] =3D msa_bclr_df(DF_BYTE, pws->b[0], pwt->b[14]); + pwd->b[15] =3D msa_bclr_df(DF_BYTE, pws->b[0], pwt->b[15]); +} + +void helper_msa_bclr_h(CPUMIPSState *env, uint32_t wd, uint32_t ws, uint32= _t wt) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); + + pwd->h[0] =3D msa_bclr_df(DF_HALF, pws->h[0], pwt->h[0]); + pwd->h[1] =3D msa_bclr_df(DF_HALF, pws->h[0], pwt->h[1]); + pwd->h[2] =3D msa_bclr_df(DF_HALF, pws->h[0], pwt->h[2]); + pwd->h[3] =3D msa_bclr_df(DF_HALF, pws->h[0], pwt->h[3]); + pwd->h[4] =3D msa_bclr_df(DF_HALF, pws->h[0], pwt->h[4]); + pwd->h[5] =3D msa_bclr_df(DF_HALF, pws->h[0], pwt->h[5]); + pwd->h[6] =3D msa_bclr_df(DF_HALF, pws->h[0], pwt->h[6]); + pwd->h[7] =3D msa_bclr_df(DF_HALF, pws->h[0], pwt->h[7]); +} + +void helper_msa_bclr_w(CPUMIPSState *env, uint32_t wd, uint32_t ws, uint32= _t wt) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); + + pwd->w[0] =3D msa_bclr_df(DF_WORD, pws->w[0], pwt->w[0]); + pwd->w[1] =3D msa_bclr_df(DF_WORD, pws->w[0], pwt->w[1]); + pwd->w[2] =3D msa_bclr_df(DF_WORD, pws->w[0], pwt->w[2]); + pwd->w[3] =3D msa_bclr_df(DF_WORD, pws->w[0], pwt->w[3]); +} + +void helper_msa_bclr_d(CPUMIPSState *env, uint32_t wd, uint32_t ws, uint32= _t wt) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); + + pwd->d[0] =3D msa_bclr_df(DF_DOUBLE, pws->d[0], pwt->d[0]); + pwd->d[1] =3D msa_bclr_df(DF_DOUBLE, pws->d[0], pwt->d[1]); +} + +static inline int64_t msa_bneg_df(uint32_t df, int64_t arg1, int64_t arg2) +{ + int32_t b_arg2 =3D BIT_POSITION(arg2, df); + return UNSIGNED(arg1 ^ (1LL << b_arg2), df); +} + +void helper_msa_bneg_b(CPUMIPSState *env, uint32_t wd, uint32_t ws, uint32= _t wt) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); + + pwd->b[0] =3D msa_bneg_df(DF_BYTE, pws->b[0], pwt->b[0]); + pwd->b[1] =3D msa_bneg_df(DF_BYTE, pws->b[0], pwt->b[1]); + pwd->b[2] =3D msa_bneg_df(DF_BYTE, pws->b[0], pwt->b[2]); + pwd->b[3] =3D msa_bneg_df(DF_BYTE, pws->b[0], pwt->b[3]); + pwd->b[4] =3D msa_bneg_df(DF_BYTE, pws->b[0], pwt->b[4]); + pwd->b[5] =3D msa_bneg_df(DF_BYTE, pws->b[0], pwt->b[5]); + pwd->b[6] =3D msa_bneg_df(DF_BYTE, pws->b[0], pwt->b[6]); + pwd->b[7] =3D msa_bneg_df(DF_BYTE, pws->b[0], pwt->b[7]); + pwd->b[8] =3D msa_bneg_df(DF_BYTE, pws->b[0], pwt->b[8]); + pwd->b[9] =3D msa_bneg_df(DF_BYTE, pws->b[0], pwt->b[9]); + pwd->b[10] =3D msa_bneg_df(DF_BYTE, pws->b[0], pwt->b[10]); + pwd->b[11] =3D msa_bneg_df(DF_BYTE, pws->b[0], pwt->b[11]); + pwd->b[12] =3D msa_bneg_df(DF_BYTE, pws->b[0], pwt->b[12]); + pwd->b[13] =3D msa_bneg_df(DF_BYTE, pws->b[0], pwt->b[13]); + pwd->b[14] =3D msa_bneg_df(DF_BYTE, pws->b[0], pwt->b[14]); + pwd->b[15] =3D msa_bneg_df(DF_BYTE, pws->b[0], pwt->b[15]); +} + +void helper_msa_bneg_h(CPUMIPSState *env, uint32_t wd, uint32_t ws, uint32= _t wt) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); + + pwd->h[0] =3D msa_bneg_df(DF_HALF, pws->h[0], pwt->h[0]); + pwd->h[1] =3D msa_bneg_df(DF_HALF, pws->h[0], pwt->h[1]); + pwd->h[2] =3D msa_bneg_df(DF_HALF, pws->h[0], pwt->h[2]); + pwd->h[3] =3D msa_bneg_df(DF_HALF, pws->h[0], pwt->h[3]); + pwd->h[4] =3D msa_bneg_df(DF_HALF, pws->h[0], pwt->h[4]); + pwd->h[5] =3D msa_bneg_df(DF_HALF, pws->h[0], pwt->h[5]); + pwd->h[6] =3D msa_bneg_df(DF_HALF, pws->h[0], pwt->h[6]); + pwd->h[7] =3D msa_bneg_df(DF_HALF, pws->h[0], pwt->h[7]); +} + +void helper_msa_bneg_w(CPUMIPSState *env, uint32_t wd, uint32_t ws, uint32= _t wt) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); + + pwd->w[0] =3D msa_bneg_df(DF_WORD, pws->w[0], pwt->w[0]); + pwd->w[1] =3D msa_bneg_df(DF_WORD, pws->w[0], pwt->w[1]); + pwd->w[2] =3D msa_bneg_df(DF_WORD, pws->w[0], pwt->w[2]); + pwd->w[3] =3D msa_bneg_df(DF_WORD, pws->w[0], pwt->w[3]); +} + +void helper_msa_bneg_d(CPUMIPSState *env, uint32_t wd, uint32_t ws, uint32= _t wt) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); + + pwd->d[0] =3D msa_bneg_df(DF_DOUBLE, pws->d[0], pwt->d[0]); + pwd->d[1] =3D msa_bneg_df(DF_DOUBLE, pws->d[0], pwt->d[1]); +} + +static inline int64_t msa_bset_df(uint32_t df, int64_t arg1, + int64_t arg2) +{ + int32_t b_arg2 =3D BIT_POSITION(arg2, df); + return UNSIGNED(arg1 | (1LL << b_arg2), df); +} + +void helper_msa_bset_b(CPUMIPSState *env, uint32_t wd, uint32_t ws, uint32= _t wt) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); + + pwd->b[0] =3D msa_bset_df(DF_BYTE, pws->b[0], pwt->b[0]); + pwd->b[1] =3D msa_bset_df(DF_BYTE, pws->b[0], pwt->b[1]); + pwd->b[2] =3D msa_bset_df(DF_BYTE, pws->b[0], pwt->b[2]); + pwd->b[3] =3D msa_bset_df(DF_BYTE, pws->b[0], pwt->b[3]); + pwd->b[4] =3D msa_bset_df(DF_BYTE, pws->b[0], pwt->b[4]); + pwd->b[5] =3D msa_bset_df(DF_BYTE, pws->b[0], pwt->b[5]); + pwd->b[6] =3D msa_bset_df(DF_BYTE, pws->b[0], pwt->b[6]); + pwd->b[7] =3D msa_bset_df(DF_BYTE, pws->b[0], pwt->b[7]); + pwd->b[8] =3D msa_bset_df(DF_BYTE, pws->b[0], pwt->b[8]); + pwd->b[9] =3D msa_bset_df(DF_BYTE, pws->b[0], pwt->b[9]); + pwd->b[10] =3D msa_bset_df(DF_BYTE, pws->b[0], pwt->b[10]); + pwd->b[11] =3D msa_bset_df(DF_BYTE, pws->b[0], pwt->b[11]); + pwd->b[12] =3D msa_bset_df(DF_BYTE, pws->b[0], pwt->b[12]); + pwd->b[13] =3D msa_bset_df(DF_BYTE, pws->b[0], pwt->b[13]); + pwd->b[14] =3D msa_bset_df(DF_BYTE, pws->b[0], pwt->b[14]); + pwd->b[15] =3D msa_bset_df(DF_BYTE, pws->b[0], pwt->b[15]); +} + +void helper_msa_bset_h(CPUMIPSState *env, uint32_t wd, uint32_t ws, uint32= _t wt) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); + + pwd->h[0] =3D msa_bset_df(DF_HALF, pws->h[0], pwt->h[0]); + pwd->h[1] =3D msa_bset_df(DF_HALF, pws->h[0], pwt->h[1]); + pwd->h[2] =3D msa_bset_df(DF_HALF, pws->h[0], pwt->h[2]); + pwd->h[3] =3D msa_bset_df(DF_HALF, pws->h[0], pwt->h[3]); + pwd->h[4] =3D msa_bset_df(DF_HALF, pws->h[0], pwt->h[4]); + pwd->h[5] =3D msa_bset_df(DF_HALF, pws->h[0], pwt->h[5]); + pwd->h[6] =3D msa_bset_df(DF_HALF, pws->h[0], pwt->h[6]); + pwd->h[7] =3D msa_bset_df(DF_HALF, pws->h[0], pwt->h[7]); +} + +void helper_msa_bset_w(CPUMIPSState *env, uint32_t wd, uint32_t ws, uint32= _t wt) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); + + pwd->w[0] =3D msa_bset_df(DF_WORD, pws->w[0], pwt->w[0]); + pwd->w[1] =3D msa_bset_df(DF_WORD, pws->w[0], pwt->w[1]); + pwd->w[2] =3D msa_bset_df(DF_WORD, pws->w[0], pwt->w[2]); + pwd->w[3] =3D msa_bset_df(DF_WORD, pws->w[0], pwt->w[3]); +} + +void helper_msa_bset_d(CPUMIPSState *env, uint32_t wd, uint32_t ws, uint32= _t wt) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); + + pwd->d[0] =3D msa_bset_df(DF_DOUBLE, pws->d[0], pwt->d[0]); + pwd->d[1] =3D msa_bset_df(DF_DOUBLE, pws->d[0], pwt->d[1]); +} =20 =20 /* @@ -1220,25 +1423,6 @@ static inline int64_t msa_srl_df(uint32_t df, int64_= t arg1, int64_t arg2) return u_arg1 >> b_arg2; } =20 -static inline int64_t msa_bclr_df(uint32_t df, int64_t arg1, int64_t arg2) -{ - int32_t b_arg2 =3D BIT_POSITION(arg2, df); - return UNSIGNED(arg1 & (~(1LL << b_arg2)), df); -} - -static inline int64_t msa_bset_df(uint32_t df, int64_t arg1, - int64_t arg2) -{ - int32_t b_arg2 =3D BIT_POSITION(arg2, df); - return UNSIGNED(arg1 | (1LL << b_arg2), df); -} - -static inline int64_t msa_bneg_df(uint32_t df, int64_t arg1, int64_t arg2) -{ - int32_t b_arg2 =3D BIT_POSITION(arg2, df); - return UNSIGNED(arg1 ^ (1LL << b_arg2), df); -} - static inline int64_t msa_sat_s_df(uint32_t df, int64_t arg, uint32_t m) { return arg < M_MIN_INT(m + 1) ? M_MIN_INT(m + 1) : @@ -1734,9 +1918,6 @@ void helper_msa_ ## func ## _df(CPUMIPSState *env, ui= nt32_t df, \ MSA_BINOP_DF(sll) MSA_BINOP_DF(sra) MSA_BINOP_DF(srl) -MSA_BINOP_DF(bclr) -MSA_BINOP_DF(bset) -MSA_BINOP_DF(bneg) MSA_BINOP_DF(addv) MSA_BINOP_DF(subv) MSA_BINOP_DF(max_s) diff --git a/target/mips/translate.c b/target/mips/translate.c index 6080c72..1a87f79 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -28418,6 +28418,54 @@ static void gen_msa_3r(CPUMIPSState *env, DisasCon= text *ctx) break; } break; + case OPC_BCLR_df: + switch (df) { + case DF_BYTE: + gen_helper_msa_bclr_b(cpu_env, twd, tws, twt); + break; + case DF_HALF: + gen_helper_msa_bclr_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_bclr_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_bclr_d(cpu_env, twd, tws, twt); + break; + } + break; + case OPC_BNEG_df: + switch (df) { + case DF_BYTE: + gen_helper_msa_bneg_b(cpu_env, twd, tws, twt); + break; + case DF_HALF: + gen_helper_msa_bneg_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_bneg_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_bneg_d(cpu_env, twd, tws, twt); + break; + } + break; + case OPC_BSET_df: + switch (df) { + case DF_BYTE: + gen_helper_msa_bset_b(cpu_env, twd, tws, twt); + break; + case DF_HALF: + gen_helper_msa_bset_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_bset_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_bset_d(cpu_env, twd, tws, twt); + break; + } + break; case OPC_SLL_df: gen_helper_msa_sll_df(cpu_env, tdf, twd, tws, twt); break; @@ -28487,9 +28535,6 @@ static void gen_msa_3r(CPUMIPSState *env, DisasCont= ext *ctx) case OPC_SRLR_df: gen_helper_msa_srlr_df(cpu_env, tdf, twd, tws, twt); break; - case OPC_BCLR_df: - gen_helper_msa_bclr_df(cpu_env, tdf, twd, tws, twt); - break; case OPC_MAX_U_df: gen_helper_msa_max_u_df(cpu_env, tdf, twd, tws, twt); break; @@ -28505,9 +28550,6 @@ static void gen_msa_3r(CPUMIPSState *env, DisasCont= ext *ctx) case OPC_PCKOD_df: gen_helper_msa_pckod_df(cpu_env, tdf, twd, tws, twt); break; - case OPC_BSET_df: - gen_helper_msa_bset_df(cpu_env, tdf, twd, tws, twt); - break; case OPC_MIN_S_df: gen_helper_msa_min_s_df(cpu_env, tdf, twd, tws, twt); break; @@ -28526,9 +28568,6 @@ static void gen_msa_3r(CPUMIPSState *env, DisasCont= ext *ctx) case OPC_ILVL_df: gen_helper_msa_ilvl_df(cpu_env, tdf, twd, tws, twt); break; - case OPC_BNEG_df: - gen_helper_msa_bneg_df(cpu_env, tdf, twd, tws, twt); - break; case OPC_MIN_U_df: gen_helper_msa_min_u_df(cpu_env, tdf, twd, tws, twt); break; --=20 2.7.4