From nobody Wed Nov 12 03:43:49 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1568306091; cv=none; d=zoho.com; s=zohoarc; b=DSlztOhDFc4crXhxpS3Yw8W43KkY63ZnJUbX/2lBGTb7JGvxng5BV+EQcRJ7OJaKsdG19RoIOUDcTDfZerEZvPOCMhnhklqE8S4h81dOZ7kYefz5EgsnyMxPAAEod/KyyNZZRuYF8/d+NhtTvfXWr7xP8N0K31XM1hEIbZumk+M= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1568306091; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=gWL0Go19/mFRTwAX3YNlTFJSPAq1fe/qmOY+tN+itek=; b=hf0/7X72U86DpAcJUZe+rL6z/2IUuxM/+NVAnCHHCam4QwuzewHmtK42DuBzvE9nwaMWoB4jogxN6M26TtEP3gYOXZTb/8lw+/dC2uOL0A/VkmS8rblKU5QgTQZyYIQFIRhcoE8HrROicvoslK1fJvQT5oFRuURWMrrx5WCx95A= ARC-Authentication-Results: i=1; mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1568306091007514.1340655047954; Thu, 12 Sep 2019 09:34:51 -0700 (PDT) Received: from localhost ([::1]:36964 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i8S3U-00082x-Ut for importer@patchew.org; Thu, 12 Sep 2019 12:34:48 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:57194) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i8S0g-0005p7-Br for qemu-devel@nongnu.org; Thu, 12 Sep 2019 12:31:55 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1i8S0e-0006K5-TB for qemu-devel@nongnu.org; Thu, 12 Sep 2019 12:31:54 -0400 Received: from mx2.rt-rk.com ([89.216.37.149]:37112 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1i8S0e-00061q-Ho for qemu-devel@nongnu.org; Thu, 12 Sep 2019 12:31:52 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id A5F771A1E25; Thu, 12 Sep 2019 18:30:46 +0200 (CEST) Received: from rtrkw774-lin.domain.local (rtrkw774-lin.domain.local [10.10.13.43]) by mail.rt-rk.com (Postfix) with ESMTPSA id 7D6FB1A1E6B; Thu, 12 Sep 2019 18:30:46 +0200 (CEST) X-Virus-Scanned: amavisd-new at rt-rk.com From: Aleksandar Markovic To: qemu-devel@nongnu.org Date: Thu, 12 Sep 2019 18:30:37 +0200 Message-Id: <1568305840-12550-2-git-send-email-aleksandar.markovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1568305840-12550-1-git-send-email-aleksandar.markovic@rt-rk.com> References: <1568305840-12550-1-git-send-email-aleksandar.markovic@rt-rk.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 89.216.37.149 Subject: [Qemu-devel] [PULL 1/4] hw/mips/mips_jazz: Override do_transaction_failed hook X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, amarkovic@wavecomp.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" From: Peter Maydell The MIPS Jazz ('magnum' and 'pica61') boards have some code which overrides the CPU's do_unassigned_access hook, so they can intercept it and not raise exceptions on data accesses to invalid addresses, only for instruction fetches. We want to switch MIPS over to using the do_transaction_failed hook instead, so add an intercept for that as well, and make the board code install whichever hook the CPU is actually using. Once we've changed the CPU implementation we can remove the redundant code for the old hook. Note: I am suspicious that the behaviour as implemented here may not be what the hardware really does. It was added in commit 54e755588cf1e90f0b14 to restore the behaviour that was broken by commit c658b94f6e8c206c59d. But prior to commit c658b94f6e8c206c59d every MIPS board generated exceptions for instruction access to invalid addresses but not for data accesses; and other boards, notably Malta, were fixed by making all invalid accesses behave as reads-as-zero (see the call to empty_slot_init() in mips_malta_init()). Hardware that raises exceptions for instruction access and not data access seems to me to be an unlikely design, and it's possible that the right way to emulate this is to make the Jazz boards do what we did with Malta (or some variation of that). Nonetheless, since I don't have access to real hardware to test against I have taken the approach of "make QEMU continue to behave the same way it did before this commit". I have updated the comment to correct the parts that are no longer accurate and note that the hardware might behave differently. The test case for the need for the hook-hijacking is in https://bugs.launchpad.net/qemu/+bug/1245924 That BIOS will boot OK either with this overriding of both hooks, or with a simple "global memory region to ignore bad accesses of all types", so it doesn't provide evidence either way, unfortunately. Signed-off-by: Peter Maydell Signed-off-by: Aleksandar Markovic Reviewed-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Herv=C3=A9 Poussineau Message-Id: <20190802160458.25681-2-peter.maydell@linaro.org> --- hw/mips/mips_jazz.c | 54 +++++++++++++++++++++++++++++++++++++++++++++----= ---- 1 file changed, 46 insertions(+), 8 deletions(-) diff --git a/hw/mips/mips_jazz.c b/hw/mips/mips_jazz.c index 388c15c..1a8e847 100644 --- a/hw/mips/mips_jazz.c +++ b/hw/mips/mips_jazz.c @@ -123,6 +123,28 @@ static void mips_jazz_do_unassigned_access(CPUState *c= pu, hwaddr addr, (*real_do_unassigned_access)(cpu, addr, is_write, is_exec, opaque, siz= e); } =20 +static void (*real_do_transaction_failed)(CPUState *cpu, hwaddr physaddr, + vaddr addr, unsigned size, + MMUAccessType access_type, + int mmu_idx, MemTxAttrs attrs, + MemTxResult response, + uintptr_t retaddr); + +static void mips_jazz_do_transaction_failed(CPUState *cs, hwaddr physaddr, + vaddr addr, unsigned size, + MMUAccessType access_type, + int mmu_idx, MemTxAttrs attrs, + MemTxResult response, + uintptr_t retaddr) +{ + if (access_type !=3D MMU_INST_FETCH) { + /* ignore invalid access (ie do not raise exception) */ + return; + } + (*real_do_transaction_failed)(cs, physaddr, addr, size, access_type, + mmu_idx, attrs, response, retaddr); +} + static void mips_jazz_init(MachineState *machine, enum jazz_model_e jazz_model) { @@ -157,16 +179,32 @@ static void mips_jazz_init(MachineState *machine, env =3D &cpu->env; qemu_register_reset(main_cpu_reset, cpu); =20 - /* Chipset returns 0 in invalid reads and do not raise data exceptions. + /* + * Chipset returns 0 in invalid reads and do not raise data exceptions. * However, we can't simply add a global memory region to catch - * everything, as memory core directly call unassigned_mem_read/write - * on some invalid accesses, which call do_unassigned_access on the - * CPU, which raise an exception. - * Handle that case by hijacking the do_unassigned_access method on - * the CPU, and do not raise exceptions for data access. */ + * everything, as this would make all accesses including instruction + * accesses be ignored and not raise exceptions. + * So instead we hijack either the do_unassigned_access method or + * the do_transaction_failed method on the CPU, and do not raise excep= tions + * for data access. + * + * NOTE: this behaviour of raising exceptions for bad instruction + * fetches but not bad data accesses was added in commit 54e755588cf1e9 + * to restore behaviour broken by c658b94f6e8c206, but it is not clear + * whether the real hardware behaves this way. It is possible that + * real hardware ignores bad instruction fetches as well -- if so then + * we could replace this hijacking of CPU methods with a simple global + * memory region that catches all memory accesses, as we do on Malta. + */ cc =3D CPU_GET_CLASS(cpu); - real_do_unassigned_access =3D cc->do_unassigned_access; - cc->do_unassigned_access =3D mips_jazz_do_unassigned_access; + if (cc->do_unassigned_access) { + real_do_unassigned_access =3D cc->do_unassigned_access; + cc->do_unassigned_access =3D mips_jazz_do_unassigned_access; + } + if (cc->do_transaction_failed) { + real_do_transaction_failed =3D cc->do_transaction_failed; + cc->do_transaction_failed =3D mips_jazz_do_transaction_failed; + } =20 /* allocate RAM */ memory_region_allocate_system_memory(ram, NULL, "mips_jazz.ram", --=20 2.7.4 From nobody Wed Nov 12 03:43:49 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1568306094; cv=none; d=zoho.com; s=zohoarc; b=SgqU+g8vzgclpCsNhYAdZZ9db3HR+krHNZPbazstddCCEBTdaN4x0yjbdHi0c/fuFv45UfoCprk81LuxqIUvajFYlLgeDdw7LbZ/4+fknhUNXYrtwOoESij4yfsZf0PJN3FYN/qNByQCCxkS107vLTfF7WEU+Efn59HkOTmhJ9w= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1568306094; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=Ue75jF59X6FAs2ypw289ENFKwZqu7RHleWhAZr4pUb0=; b=YoqKKoGfqxMhz68rflzUQakYiVtRFP4s/W8A5/O8KKVuJuYsxvoh2e5XhiJRmqEsdvOFA8umKO1WT0dDDNw+p34/g6c4tkR6X922i5OyxAp4Kq3DvAs1yPoTrxbxSNH6bfnvzdPZN5JcU2lv06lR0+tPu/Fr7iMpIfzKl/1T7bQ= ARC-Authentication-Results: i=1; mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (209.51.188.17 [209.51.188.17]) by mx.zohomail.com with SMTPS id 15683060938091010.4671450942925; Thu, 12 Sep 2019 09:34:53 -0700 (PDT) Received: from localhost ([::1]:36962 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i8S3R-0007xF-Tg for importer@patchew.org; Thu, 12 Sep 2019 12:34:45 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:57193) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i8S0g-0005p6-Bn for qemu-devel@nongnu.org; Thu, 12 Sep 2019 12:31:55 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1i8S0e-0006Jy-SE for qemu-devel@nongnu.org; Thu, 12 Sep 2019 12:31:54 -0400 Received: from mx2.rt-rk.com ([89.216.37.149]:37119 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1i8S0e-00061u-H0 for qemu-devel@nongnu.org; Thu, 12 Sep 2019 12:31:52 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id B1E781A218D; Thu, 12 Sep 2019 18:30:46 +0200 (CEST) Received: from rtrkw774-lin.domain.local (rtrkw774-lin.domain.local [10.10.13.43]) by mail.rt-rk.com (Postfix) with ESMTPSA id 866081A1E75; Thu, 12 Sep 2019 18:30:46 +0200 (CEST) X-Virus-Scanned: amavisd-new at rt-rk.com From: Aleksandar Markovic To: qemu-devel@nongnu.org Date: Thu, 12 Sep 2019 18:30:38 +0200 Message-Id: <1568305840-12550-3-git-send-email-aleksandar.markovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1568305840-12550-1-git-send-email-aleksandar.markovic@rt-rk.com> References: <1568305840-12550-1-git-send-email-aleksandar.markovic@rt-rk.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 89.216.37.149 Subject: [Qemu-devel] [PULL 2/4] target/mips: Switch to do_transaction_failed() hook X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, amarkovic@wavecomp.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" From: Peter Maydell Switch the MIPS target from the old unassigned_access hook to the new do_transaction_failed hook. Unlike the old hook, do_transaction_failed is only ever called from the TCG memory access paths, so there is no need for the "ignore this if we're using KVM" hack that we were previously using to work around the way unassigned_access was called for all kinds of memory accesses to unassigned physical addresses. The MIPS target does not ever do direct memory reads by physical address (via either ldl_phys etc or address_space_ldl etc), so the only memory accesses this affects are the 'normal' guest loads and stores, which will be handled by the new hook; their behaviour is unchanged. Signed-off-by: Peter Maydell Signed-off-by: Aleksandar Markovic Reviewed-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Herv=C3=A9 Poussineau Message-Id: <20190802160458.25681-3-peter.maydell@linaro.org> --- target/mips/cpu.c | 2 +- target/mips/internal.h | 8 +++++--- target/mips/op_helper.c | 24 ++++++++---------------- 3 files changed, 14 insertions(+), 20 deletions(-) diff --git a/target/mips/cpu.c b/target/mips/cpu.c index 3ffa342..bbcf7ca 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -202,7 +202,7 @@ static void mips_cpu_class_init(ObjectClass *c, void *d= ata) cc->gdb_read_register =3D mips_cpu_gdb_read_register; cc->gdb_write_register =3D mips_cpu_gdb_write_register; #ifndef CONFIG_USER_ONLY - cc->do_unassigned_access =3D mips_cpu_unassigned_access; + cc->do_transaction_failed =3D mips_cpu_do_transaction_failed; cc->do_unaligned_access =3D mips_cpu_do_unaligned_access; cc->get_phys_page_debug =3D mips_cpu_get_phys_page_debug; cc->vmsd =3D &vmstate_mips_cpu; diff --git a/target/mips/internal.h b/target/mips/internal.h index ae29b57..685e8d6 100644 --- a/target/mips/internal.h +++ b/target/mips/internal.h @@ -139,9 +139,11 @@ void r4k_helper_tlbinv(CPUMIPSState *env); void r4k_helper_tlbinvf(CPUMIPSState *env); void r4k_invalidate_tlb(CPUMIPSState *env, int idx, int use_extra); =20 -void mips_cpu_unassigned_access(CPUState *cpu, hwaddr addr, - bool is_write, bool is_exec, int unused, - unsigned size); +void mips_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, + vaddr addr, unsigned size, + MMUAccessType access_type, + int mmu_idx, MemTxAttrs attrs, + MemTxResult response, uintptr_t retadd= r); hwaddr cpu_mips_translate_address(CPUMIPSState *env, target_ulong address, int rw); #endif diff --git a/target/mips/op_helper.c b/target/mips/op_helper.c index 01b9e78..4de6465 100644 --- a/target/mips/op_helper.c +++ b/target/mips/op_helper.c @@ -2668,27 +2668,19 @@ void mips_cpu_do_unaligned_access(CPUState *cs, vad= dr addr, do_raise_exception_err(env, excp, error_code, retaddr); } =20 -void mips_cpu_unassigned_access(CPUState *cs, hwaddr addr, - bool is_write, bool is_exec, int unused, - unsigned size) +void mips_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, + vaddr addr, unsigned size, + MMUAccessType access_type, + int mmu_idx, MemTxAttrs attrs, + MemTxResult response, uintptr_t retadd= r) { MIPSCPU *cpu =3D MIPS_CPU(cs); CPUMIPSState *env =3D &cpu->env; =20 - /* - * Raising an exception with KVM enabled will crash because it won't b= e from - * the main execution loop so the longjmp won't have a matching setjmp. - * Until we can trigger a bus error exception through KVM lets just ig= nore - * the access. - */ - if (kvm_enabled()) { - return; - } - - if (is_exec) { - raise_exception(env, EXCP_IBE); + if (access_type =3D=3D MMU_INST_FETCH) { + do_raise_exception(env, EXCP_IBE, retaddr); } else { - raise_exception(env, EXCP_DBE); + do_raise_exception(env, EXCP_DBE, retaddr); } } #endif /* !CONFIG_USER_ONLY */ --=20 2.7.4 From nobody Wed Nov 12 03:43:49 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; 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Thu, 12 Sep 2019 18:30:46 +0200 (CEST) X-Virus-Scanned: amavisd-new at rt-rk.com From: Aleksandar Markovic To: qemu-devel@nongnu.org Date: Thu, 12 Sep 2019 18:30:39 +0200 Message-Id: <1568305840-12550-4-git-send-email-aleksandar.markovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1568305840-12550-1-git-send-email-aleksandar.markovic@rt-rk.com> References: <1568305840-12550-1-git-send-email-aleksandar.markovic@rt-rk.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 89.216.37.149 Subject: [Qemu-devel] [PULL 3/4] hw/mips/mips_jazz: Remove no-longer-necessary override of do_unassigned_access X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, amarkovic@wavecomp.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" From: Peter Maydell Now that the MIPS CPU implementation uses the new do_transaction_failed hook, we can remove the old code that handled the do_unassigned_access hook. Signed-off-by: Peter Maydell Signed-off-by: Aleksandar Markovic Reviewed-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Herv=C3=A9 Poussineau Message-Id: <20190802160458.25681-4-peter.maydell@linaro.org> --- hw/mips/mips_jazz.c | 27 ++++----------------------- 1 file changed, 4 insertions(+), 23 deletions(-) diff --git a/hw/mips/mips_jazz.c b/hw/mips/mips_jazz.c index 1a8e847..c967b97 100644 --- a/hw/mips/mips_jazz.c +++ b/hw/mips/mips_jazz.c @@ -111,18 +111,6 @@ static const MemoryRegionOps dma_dummy_ops =3D { #define MAGNUM_BIOS_SIZE_MAX 0x7e000 #define MAGNUM_BIOS_SIZE (BIOS_SIZE < MAGNUM_BIOS_SIZE_MAX ? BIOS_SIZE : M= AGNUM_BIOS_SIZE_MAX) =20 -static CPUUnassignedAccess real_do_unassigned_access; -static void mips_jazz_do_unassigned_access(CPUState *cpu, hwaddr addr, - bool is_write, bool is_exec, - int opaque, unsigned size) -{ - if (!is_exec) { - /* ignore invalid access (ie do not raise exception) */ - return; - } - (*real_do_unassigned_access)(cpu, addr, is_write, is_exec, opaque, siz= e); -} - static void (*real_do_transaction_failed)(CPUState *cpu, hwaddr physaddr, vaddr addr, unsigned size, MMUAccessType access_type, @@ -184,9 +172,8 @@ static void mips_jazz_init(MachineState *machine, * However, we can't simply add a global memory region to catch * everything, as this would make all accesses including instruction * accesses be ignored and not raise exceptions. - * So instead we hijack either the do_unassigned_access method or - * the do_transaction_failed method on the CPU, and do not raise excep= tions - * for data access. + * So instead we hijack the do_transaction_failed method on the CPU, a= nd + * do not raise exceptions for data access. * * NOTE: this behaviour of raising exceptions for bad instruction * fetches but not bad data accesses was added in commit 54e755588cf1e9 @@ -197,14 +184,8 @@ static void mips_jazz_init(MachineState *machine, * memory region that catches all memory accesses, as we do on Malta. */ cc =3D CPU_GET_CLASS(cpu); - if (cc->do_unassigned_access) { - real_do_unassigned_access =3D cc->do_unassigned_access; - cc->do_unassigned_access =3D mips_jazz_do_unassigned_access; - } - if (cc->do_transaction_failed) { - real_do_transaction_failed =3D cc->do_transaction_failed; - cc->do_transaction_failed =3D mips_jazz_do_transaction_failed; - } + real_do_transaction_failed =3D cc->do_transaction_failed; + cc->do_transaction_failed =3D mips_jazz_do_transaction_failed; =20 /* allocate RAM */ memory_region_allocate_system_memory(ram, NULL, "mips_jazz.ram", --=20 2.7.4 From nobody Wed Nov 12 03:43:49 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; 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Thu, 12 Sep 2019 18:30:46 +0200 (CEST) X-Virus-Scanned: amavisd-new at rt-rk.com From: Aleksandar Markovic To: qemu-devel@nongnu.org Date: Thu, 12 Sep 2019 18:30:40 +0200 Message-Id: <1568305840-12550-5-git-send-email-aleksandar.markovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1568305840-12550-1-git-send-email-aleksandar.markovic@rt-rk.com> References: <1568305840-12550-1-git-send-email-aleksandar.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 89.216.37.149 Subject: [Qemu-devel] [PULL 4/4] target/mips: gdbstub: Revert commit 8e0b373 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, amarkovic@wavecomp.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Libo Zhou Multiple reports from users were received regarding failures of packet 'g' communication with gdb for some MIPS configurations. It was found out (by bisecting) that the problematic commit is 8e0b373. Revert that commit until a better solution is developed. Suggested-by: Aleksandar Markovic Signed-off-by: Libo Zhou Signed-off-by: Aleksandar Markovic Reviewed-by: Aleksandar Markovic Message-Id: <1568207966-25202-1-git-send-email-aleksandar.markovic@rt-rk.co= m> --- target/mips/gdbstub.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/target/mips/gdbstub.c b/target/mips/gdbstub.c index ebcc98b..bbb2544 100644 --- a/target/mips/gdbstub.c +++ b/target/mips/gdbstub.c @@ -38,7 +38,7 @@ int mips_cpu_gdb_read_register(CPUState *cs, uint8_t *mem= _buf, int n) return gdb_get_regl(mem_buf, (int32_t)env->active_fpu.fcr0); default: if (env->CP0_Status & (1 << CP0St_FR)) { - return gdb_get_reg64(mem_buf, + return gdb_get_regl(mem_buf, env->active_fpu.fpr[n - 38].d); } else { return gdb_get_regl(mem_buf, @@ -99,7 +99,6 @@ int mips_cpu_gdb_write_register(CPUState *cs, uint8_t *me= m_buf, int n) break; default: if (env->CP0_Status & (1 << CP0St_FR)) { - uint64_t tmp =3D ldq_p(mem_buf); env->active_fpu.fpr[n - 38].d =3D tmp; } else { env->active_fpu.fpr[n - 38].w[FP_ENDIAN_IDX] =3D tmp; --=20 2.7.4