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X-Received-From: 2607:f8b0:4864:20::541 Subject: [Qemu-devel] [PATCH v7 29/30] riscv: sifive_u: Remove handcrafted clock nodes for UART and ethernet X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" In the past we did not have a model for PRCI, hence two handcrafted clock nodes ("/soc/ethclk" and "/soc/uartclk") were created for the purpose of supplying hard-coded clock frequencies. But now since we have added the PRCI support in QEMU, we don't need them any more. Signed-off-by: Bin Meng Reviewed-by: Alistair Francis --- Changes in v7: None Changes in v6: None Changes in v5: None Changes in v4: - new patch to remove handcrafted clock nodes for UART and ethernet Changes in v3: None Changes in v2: None hw/riscv/sifive_u.c | 24 +----------------------- include/hw/riscv/sifive_u.h | 3 +-- 2 files changed, 2 insertions(+), 25 deletions(-) diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index a7225f9..f14217c 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -87,8 +87,7 @@ static void create_fdt(SiFiveUState *s, const struct Memm= apEntry *memmap, uint32_t *cells; char *nodename; char ethclk_names[] =3D "pclk\0hclk"; - uint32_t plic_phandle, prci_phandle, ethclk_phandle, phandle =3D 1; - uint32_t uartclk_phandle; + uint32_t plic_phandle, prci_phandle, phandle =3D 1; uint32_t hfclk_phandle, rtcclk_phandle, phy_phandle; =20 fdt =3D s->fdt =3D create_device_tree(&s->fdt_size); @@ -248,17 +247,6 @@ static void create_fdt(SiFiveUState *s, const struct M= emmapEntry *memmap, g_free(cells); g_free(nodename); =20 - ethclk_phandle =3D phandle++; - nodename =3D g_strdup_printf("/soc/ethclk"); - qemu_fdt_add_subnode(fdt, nodename); - qemu_fdt_setprop_string(fdt, nodename, "compatible", "fixed-clock"); - qemu_fdt_setprop_cell(fdt, nodename, "#clock-cells", 0x0); - qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency", - SIFIVE_U_GEM_CLOCK_FREQ); - qemu_fdt_setprop_cell(fdt, nodename, "phandle", ethclk_phandle); - ethclk_phandle =3D qemu_fdt_get_phandle(fdt, nodename); - g_free(nodename); - phy_phandle =3D phandle++; nodename =3D g_strdup_printf("/soc/ethernet@%lx", (long)memmap[SIFIVE_U_GEM].base); @@ -292,16 +280,6 @@ static void create_fdt(SiFiveUState *s, const struct M= emmapEntry *memmap, qemu_fdt_setprop_cell(fdt, nodename, "reg", 0x0); g_free(nodename); =20 - uartclk_phandle =3D phandle++; - nodename =3D g_strdup_printf("/soc/uartclk"); - qemu_fdt_add_subnode(fdt, nodename); - qemu_fdt_setprop_string(fdt, nodename, "compatible", "fixed-clock"); - qemu_fdt_setprop_cell(fdt, nodename, "#clock-cells", 0x0); - qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency", 3686400); - qemu_fdt_setprop_cell(fdt, nodename, "phandle", uartclk_phandle); - uartclk_phandle =3D qemu_fdt_get_phandle(fdt, nodename); - g_free(nodename); - nodename =3D g_strdup_printf("/soc/serial@%lx", (long)memmap[SIFIVE_U_UART0].base); qemu_fdt_add_subnode(fdt, nodename); diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h index d2b9d99..3bb87cb 100644 --- a/include/hw/riscv/sifive_u.h +++ b/include/hw/riscv/sifive_u.h @@ -76,8 +76,7 @@ enum { enum { SIFIVE_U_CLOCK_FREQ =3D 1000000000, SIFIVE_U_HFCLK_FREQ =3D 33333333, - SIFIVE_U_RTCCLK_FREQ =3D 1000000, - SIFIVE_U_GEM_CLOCK_FREQ =3D 125000000 + SIFIVE_U_RTCCLK_FREQ =3D 1000000 }; =20 #define SIFIVE_U_MANAGEMENT_CPU_COUNT 1 --=20 2.7.4