From nobody Tue Feb 10 17:35:03 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1567075998; cv=none; d=zoho.com; s=zohoarc; b=PvwAKka6nv7ZZ8u69aHVEE8sPrgbK+D0d+IrjSJcaYvL5iRoU1dQ/fX0I5zkKXgFCTSr7MPUM0MrVDWDcHHe26Fj4dgjOY8Vke6PfBvq/uFb1oLvLSzlStcw7GeTc+UgUgrzTEtAZ1qubvgNapX0WUssumbTvo4Hw+JxmjZ1n/0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1567075998; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=+lnzXWPnlg+p1ygki8Ih4s3u4UST6zwz9E6oxr3Qf4s=; b=f6H4Cz7JbRNQ1AN0NxV4Ww28LloLgJnoc8pWNHJi5Y42cm2yKm3tyZZkb/t9Mzr0AQZ6tIp0NjkXpPwn/NMvxirmbRdc1YYlEZCNd42NztSZA7pesXtf35m95eVqQB4pyMvX5AE9p7MQyBYDEeS4s5ztjPIFvGt8XfBgd7IBd4Q= ARC-Authentication-Results: i=1; mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1567075998141896.2892483486619; Thu, 29 Aug 2019 03:53:18 -0700 (PDT) Received: from localhost ([::1]:48010 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i3I3I-0000L0-OW for importer@patchew.org; Thu, 29 Aug 2019 06:53:16 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:47503) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i3Hco-0005YM-FQ for qemu-devel@nongnu.org; Thu, 29 Aug 2019 06:25:56 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1i3Hcm-00064i-CB for qemu-devel@nongnu.org; Thu, 29 Aug 2019 06:25:54 -0400 Received: from mx2.rt-rk.com ([89.216.37.149]:45740 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1i3Hcl-0005jK-Pp for qemu-devel@nongnu.org; Thu, 29 Aug 2019 06:25:52 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id A490B1A21A8; Thu, 29 Aug 2019 12:25:25 +0200 (CEST) Received: from rtrkw774-lin.domain.local (rtrkw774-lin.domain.local [10.10.13.43]) by mail.rt-rk.com (Postfix) with ESMTPSA id 6CEAF1A220F; Thu, 29 Aug 2019 12:25:25 +0200 (CEST) X-Virus-Scanned: amavisd-new at rt-rk.com From: Aleksandar Markovic To: qemu-devel@nongnu.org Date: Thu, 29 Aug 2019 12:25:09 +0200 Message-Id: <1567074313-22998-28-git-send-email-aleksandar.markovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1567074313-22998-1-git-send-email-aleksandar.markovic@rt-rk.com> References: <1567074313-22998-1-git-send-email-aleksandar.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 89.216.37.149 Subject: [Qemu-devel] [PULL 27/31] target/mips: Clean up handling of CP0 register 28 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, amarkovic@wavecomp.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Aleksandar Markovic Clean up handling of CP0 register 28. Reviewed-by: Aleksandar Rikalo Signed-off-by: Aleksandar Markovic Message-Id: <1567009614-12438-28-git-send-email-aleksandar.markovic@rt-rk.c= om> --- target/mips/cpu.h | 24 +++++++++++-------- target/mips/translate.c | 64 ++++++++++++++++++++++++---------------------= ---- 2 files changed, 46 insertions(+), 42 deletions(-) diff --git a/target/mips/cpu.h b/target/mips/cpu.h index 40b7cc6..de9e850 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -233,12 +233,12 @@ typedef struct mips_def_t mips_def_t; * * 0 DataLo DataHi ErrorEPC DESAVE * 1 TagLo TagHi - * 2 DataLo DataHi KScratch - * 3 TagLo TagHi KScratch - * 4 DataLo DataHi KScratch - * 5 TagLo TagHi KScratch - * 6 DataLo DataHi KScratch - * 7 TagLo TagHi KScratch + * 2 DataLo1 DataHi KScratch + * 3 TagLo1 TagHi KScratch + * 4 DataLo2 DataHi KScratch + * 5 TagLo2 TagHi KScratch + * 6 DataLo3 DataHi KScratch + * 7 TagLo3 TagHi KScratch * */ #define CP0_REGISTER_00 0 @@ -427,10 +427,14 @@ typedef struct mips_def_t mips_def_t; /* CP0 Register 27 */ #define CP0_REG27__CACHERR 0 /* CP0 Register 28 */ -#define CP0_REG28__ITAGLO 0 -#define CP0_REG28__IDATALO 1 -#define CP0_REG28__DTAGLO 2 -#define CP0_REG28__DDATALO 3 +#define CP0_REG28__TAGLO 0 +#define CP0_REG28__DATALO 1 +#define CP0_REG28__TAGLO1 2 +#define CP0_REG28__DATALO1 3 +#define CP0_REG28__TAGLO2 4 +#define CP0_REG28__DATALO2 5 +#define CP0_REG28__TAGLO3 6 +#define CP0_REG28__DATALO3 7 /* CP0 Register 29 */ #define CP0_REG29__IDATAHI 1 #define CP0_REG29__DDATAHI 3 diff --git a/target/mips/translate.c b/target/mips/translate.c index c969c25..032e3b0 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -7476,10 +7476,10 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, i= nt reg, int sel) break; case CP0_REGISTER_28: switch (sel) { - case 0: - case 2: - case 4: - case 6: + case CP0_REG28__TAGLO: + case CP0_REG28__TAGLO1: + case CP0_REG28__TAGLO2: + case CP0_REG28__TAGLO3: { TCGv_i64 tmp =3D tcg_temp_new_i64(); tcg_gen_ld_i64(tmp, cpu_env, offsetof(CPUMIPSState, CP0_Ta= gLo)); @@ -7488,10 +7488,10 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, i= nt reg, int sel) } register_name =3D "TagLo"; break; - case 1: - case 3: - case 5: - case 7: + case CP0_REG28__DATALO: + case CP0_REG28__DATALO1: + case CP0_REG28__DATALO2: + case CP0_REG28__DATALO3: gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_DataLo)); register_name =3D "DataLo"; break; @@ -8231,17 +8231,17 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, i= nt reg, int sel) break; case CP0_REGISTER_28: switch (sel) { - case 0: - case 2: - case 4: - case 6: + case CP0_REG28__TAGLO: + case CP0_REG28__TAGLO1: + case CP0_REG28__TAGLO2: + case CP0_REG28__TAGLO3: gen_helper_mtc0_taglo(cpu_env, arg); register_name =3D "TagLo"; break; - case 1: - case 3: - case 5: - case 7: + case CP0_REG28__DATALO: + case CP0_REG28__DATALO1: + case CP0_REG28__DATALO2: + case CP0_REG28__DATALO3: gen_helper_mtc0_datalo(cpu_env, arg); register_name =3D "DataLo"; break; @@ -8959,17 +8959,17 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, = int reg, int sel) break; case CP0_REGISTER_28: switch (sel) { - case 0: - case 2: - case 4: - case 6: + case CP0_REG28__TAGLO: + case CP0_REG28__TAGLO1: + case CP0_REG28__TAGLO2: + case CP0_REG28__TAGLO3: gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_TagLo)); register_name =3D "TagLo"; break; - case 1: - case 3: - case 5: - case 7: + case CP0_REG28__DATALO: + case CP0_REG28__DATALO1: + case CP0_REG28__DATALO2: + case CP0_REG28__DATALO3: gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_DataLo)); register_name =3D "DataLo"; break; @@ -9695,17 +9695,17 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, = int reg, int sel) break; case CP0_REGISTER_28: switch (sel) { - case 0: - case 2: - case 4: - case 6: + case CP0_REG28__TAGLO: + case CP0_REG28__TAGLO1: + case CP0_REG28__TAGLO2: + case CP0_REG28__TAGLO3: gen_helper_mtc0_taglo(cpu_env, arg); register_name =3D "TagLo"; break; - case 1: - case 3: - case 5: - case 7: + case CP0_REG28__DATALO: + case CP0_REG28__DATALO1: + case CP0_REG28__DATALO2: + case CP0_REG28__DATALO3: gen_helper_mtc0_datalo(cpu_env, arg); register_name =3D "DataLo"; break; --=20 2.7.4