From nobody Tue Feb 10 17:35:03 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1567075178; cv=none; d=zoho.com; s=zohoarc; b=UosxbtczaD+lTJX/hX+pAU9GEsJ6xTK9rD2AOlDpLgmOAeytO29/8tOoWbYIx9PBmj0hRt7/LkNXC5bbzdCVsT/X4Debtg2314rqd30GNmr+ExxVjNA8+0cmU8X7lpLaIpYy7qPdN+0cX4c8QrXxdHAJlwqyFEh2AGayiPbo+Nc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1567075178; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=npqfjxH4EBFMOA9GTWHP+9ijEhmFCctppz80buIhvkM=; b=T5bSDnYezt7K4DCMImNJ/Ano+wsta3ikhqZ1Te2Rv4AVOojpObd+c/QZiD2aaPnbeMc2qqMlj0GvyMc8xcToKxGILZksQDDztvyiVsZ9TDTCKIvG+xJp9C3JQpv/yYpi6TUcGh4r8lVbI59SU1vofl0LUGNLzl4glWadWpZ1Hak= ARC-Authentication-Results: i=1; mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1567075178832166.04651946699994; Thu, 29 Aug 2019 03:39:38 -0700 (PDT) Received: from localhost ([::1]:47868 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i3Hq0-0001yU-CI for importer@patchew.org; Thu, 29 Aug 2019 06:39:32 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:47330) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i3Hcd-0005RI-NH for qemu-devel@nongnu.org; Thu, 29 Aug 2019 06:25:47 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1i3Hcb-0005kf-NM for qemu-devel@nongnu.org; Thu, 29 Aug 2019 06:25:43 -0400 Received: from mx2.rt-rk.com ([89.216.37.149]:45362 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1i3Hca-0005Lb-JT for qemu-devel@nongnu.org; Thu, 29 Aug 2019 06:25:41 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id 1505D1A21BE; Thu, 29 Aug 2019 12:25:25 +0200 (CEST) Received: from rtrkw774-lin.domain.local (rtrkw774-lin.domain.local [10.10.13.43]) by mail.rt-rk.com (Postfix) with ESMTPSA id DC4B71A21E3; Thu, 29 Aug 2019 12:25:24 +0200 (CEST) X-Virus-Scanned: amavisd-new at rt-rk.com From: Aleksandar Markovic To: qemu-devel@nongnu.org Date: Thu, 29 Aug 2019 12:24:55 +0200 Message-Id: <1567074313-22998-14-git-send-email-aleksandar.markovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1567074313-22998-1-git-send-email-aleksandar.markovic@rt-rk.com> References: <1567074313-22998-1-git-send-email-aleksandar.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 89.216.37.149 Subject: [Qemu-devel] [PULL 13/31] target/mips: Clean up handling of CP0 register 12 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, amarkovic@wavecomp.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Aleksandar Markovic Clean up handling of CP0 register 12. Reviewed-by: Aleksandar Rikalo Signed-off-by: Aleksandar Markovic Message-Id: <1567009614-12438-14-git-send-email-aleksandar.markovic@rt-rk.c= om> --- target/mips/cpu.h | 3 +++ target/mips/translate.c | 32 ++++++++++++++++---------------- 2 files changed, 19 insertions(+), 16 deletions(-) diff --git a/target/mips/cpu.h b/target/mips/cpu.h index 3797bdc..061effb 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -350,6 +350,9 @@ typedef struct mips_def_t mips_def_t; #define CP0_REG12__STATUS 0 #define CP0_REG12__INTCTL 1 #define CP0_REG12__SRSCTL 2 +#define CP0_REG12__SRSMAP 3 +#define CP0_REG12__VIEW_IPL 4 +#define CP0_REG12__SRSMAP2 5 #define CP0_REG12__GUESTCTL0 6 #define CP0_REG12__GTOFFSET 7 /* CP0 Register 13 */ diff --git a/target/mips/translate.c b/target/mips/translate.c index b5d5994..fb9c719 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -7177,21 +7177,21 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, i= nt reg, int sel) break; case CP0_REGISTER_12: switch (sel) { - case 0: + case CP0_REG12__STATUS: gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Status)); register_name =3D "Status"; break; - case 1: + case CP0_REG12__INTCTL: check_insn(ctx, ISA_MIPS32R2); gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_IntCtl)); register_name =3D "IntCtl"; break; - case 2: + case CP0_REG12__SRSCTL: check_insn(ctx, ISA_MIPS32R2); gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSCtl)); register_name =3D "SRSCtl"; break; - case 3: + case CP0_REG12__SRSMAP: check_insn(ctx, ISA_MIPS32R2); gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSMap)); register_name =3D "SRSMap"; @@ -7893,7 +7893,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int= reg, int sel) break; case CP0_REGISTER_12: switch (sel) { - case 0: + case CP0_REG12__STATUS: save_cpu_state(ctx, 1); gen_helper_mtc0_status(cpu_env, arg); /* DISAS_STOP isn't good enough here, hflags may have changed.= */ @@ -7901,21 +7901,21 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, i= nt reg, int sel) ctx->base.is_jmp =3D DISAS_EXIT; register_name =3D "Status"; break; - case 1: + case CP0_REG12__INTCTL: check_insn(ctx, ISA_MIPS32R2); gen_helper_mtc0_intctl(cpu_env, arg); /* Stop translation as we may have switched the execution mode= */ ctx->base.is_jmp =3D DISAS_STOP; register_name =3D "IntCtl"; break; - case 2: + case CP0_REG12__SRSCTL: check_insn(ctx, ISA_MIPS32R2); gen_helper_mtc0_srsctl(cpu_env, arg); /* Stop translation as we may have switched the execution mode= */ ctx->base.is_jmp =3D DISAS_STOP; register_name =3D "SRSCtl"; break; - case 3: + case CP0_REG12__SRSMAP: check_insn(ctx, ISA_MIPS32R2); gen_mtc0_store32(arg, offsetof(CPUMIPSState, CP0_SRSMap)); /* Stop translation as we may have switched the execution mode= */ @@ -8652,21 +8652,21 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, = int reg, int sel) break; case CP0_REGISTER_12: switch (sel) { - case 0: + case CP0_REG12__STATUS: gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Status)); register_name =3D "Status"; break; - case 1: + case CP0_REG12__INTCTL: check_insn(ctx, ISA_MIPS32R2); gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_IntCtl)); register_name =3D "IntCtl"; break; - case 2: + case CP0_REG12__SRSCTL: check_insn(ctx, ISA_MIPS32R2); gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSCtl)); register_name =3D "SRSCtl"; break; - case 3: + case CP0_REG12__SRSMAP: check_insn(ctx, ISA_MIPS32R2); gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSMap)); register_name =3D "SRSMap"; @@ -9356,7 +9356,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, in= t reg, int sel) break; case CP0_REGISTER_12: switch (sel) { - case 0: + case CP0_REG12__STATUS: save_cpu_state(ctx, 1); gen_helper_mtc0_status(cpu_env, arg); /* DISAS_STOP isn't good enough here, hflags may have changed.= */ @@ -9364,21 +9364,21 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, = int reg, int sel) ctx->base.is_jmp =3D DISAS_EXIT; register_name =3D "Status"; break; - case 1: + case CP0_REG12__INTCTL: check_insn(ctx, ISA_MIPS32R2); gen_helper_mtc0_intctl(cpu_env, arg); /* Stop translation as we may have switched the execution mode= */ ctx->base.is_jmp =3D DISAS_STOP; register_name =3D "IntCtl"; break; - case 2: + case CP0_REG12__SRSCTL: check_insn(ctx, ISA_MIPS32R2); gen_helper_mtc0_srsctl(cpu_env, arg); /* Stop translation as we may have switched the execution mode= */ ctx->base.is_jmp =3D DISAS_STOP; register_name =3D "SRSCtl"; break; - case 3: + case CP0_REG12__SRSMAP: check_insn(ctx, ISA_MIPS32R2); gen_mtc0_store32(arg, offsetof(CPUMIPSState, CP0_SRSMap)); /* Stop translation as we may have switched the execution mode= */ --=20 2.7.4