From nobody Tue Feb 10 08:03:19 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1567011343; cv=none; d=zoho.com; s=zohoarc; b=IU43HCqDZ08Hd1nFNWry0MHqRUxlNVYOVDlIqGZqiwkTorq/VCAMgZL8Xek3RS1GzAOr9lshrB32CXPprXTu0LJ133RfrEt358W7W/QerlIOlfy6LkHZTH3Tth8rstCa04TeSI9KT72yXXHiMY396bWx1yqRzUjRVOAIKGtHYzU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1567011343; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=7ee7YgRYd7czB7G4aj2TfdPBDLrJZ0VNfuJrEtgbUYE=; b=aMGcRgjBIChsnlSTkn9R8nSu0aDMLpCYnwRkYWXLw3SCPSdoarUDHcO9qxEsITf6gz/iTV8SMXeTmlaBHESgGytcOVvO+cxgSEWAHTapGDNOjuaV/m5c8rTss2jaTE9b2ykmmVEKXn3sLrYZe5jiz2Lf9HJxN5JEkP7/zUR6+Gk= ARC-Authentication-Results: i=1; mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1567011343493895.4328210251338; Wed, 28 Aug 2019 09:55:43 -0700 (PDT) Received: from localhost ([::1]:38712 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i31ET-0001Ja-Q8 for importer@patchew.org; Wed, 28 Aug 2019 12:55:41 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:34694) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i30n1-0007AX-Cf for qemu-devel@nongnu.org; Wed, 28 Aug 2019 12:27:21 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1i30my-00081z-Nk for qemu-devel@nongnu.org; Wed, 28 Aug 2019 12:27:18 -0400 Received: from mx2.rt-rk.com ([89.216.37.149]:55609 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1i30my-0007oY-40 for qemu-devel@nongnu.org; Wed, 28 Aug 2019 12:27:16 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id 7DD7B1A22D3; Wed, 28 Aug 2019 18:27:00 +0200 (CEST) Received: from rtrkw774-lin.domain.local (rtrkw774-lin.domain.local [10.10.13.43]) by mail.rt-rk.com (Postfix) with ESMTPSA id 2EECF1A22A9; Wed, 28 Aug 2019 18:27:00 +0200 (CEST) X-Virus-Scanned: amavisd-new at rt-rk.com From: Aleksandar Markovic To: qemu-devel@nongnu.org Date: Wed, 28 Aug 2019 18:26:40 +0200 Message-Id: <1567009614-12438-17-git-send-email-aleksandar.markovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1567009614-12438-1-git-send-email-aleksandar.markovic@rt-rk.com> References: <1567009614-12438-1-git-send-email-aleksandar.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 89.216.37.149 Subject: [Qemu-devel] [PATCH v2 16/30] target/mips: Clean up handling of CP0 register 15 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: arikalo@wavecomp.com, amarkovic@wavecomp.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Aleksandar Markovic Clean up handling of CP0 register 15. Signed-off-by: Aleksandar Markovic --- target/mips/cpu.h | 1 + target/mips/translate.c | 20 ++++++++++---------- 2 files changed, 11 insertions(+), 10 deletions(-) diff --git a/target/mips/cpu.h b/target/mips/cpu.h index 8e6376a..f709a92 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -369,6 +369,7 @@ typedef struct mips_def_t mips_def_t; #define CP0_REG15__EBASE 1 #define CP0_REG15__CDMMBASE 2 #define CP0_REG15__CMGCRBASE 3 +#define CP0_REG15__BEVVA 4 /* CP0 Register 16 */ #define CP0_REG16__CONFIG 0 #define CP0_REG16__CONFIG1 1 diff --git a/target/mips/translate.c b/target/mips/translate.c index 7644dda..a0a2d43 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -7271,17 +7271,17 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, i= nt reg, int sel) break; case CP0_REGISTER_15: switch (sel) { - case 0: + case CP0_REG15__PRID: gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PRid)); register_name =3D "PRid"; break; - case 1: + case CP0_REG15__EBASE: check_insn(ctx, ISA_MIPS32R2); tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_EBase)); tcg_gen_ext32s_tl(arg, arg); register_name =3D "EBase"; break; - case 3: + case CP0_REG15__CMGCRBASE: check_insn(ctx, ISA_MIPS32R2); CP0_CHECK(ctx->cmgcr); tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_CMGCRBa= se)); @@ -8009,11 +8009,11 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, i= nt reg, int sel) break; case CP0_REGISTER_15: switch (sel) { - case 0: + case CP0_REG15__PRID: /* ignored */ register_name =3D "PRid"; break; - case 1: + case CP0_REG15__EBASE: check_insn(ctx, ISA_MIPS32R2); gen_helper_mtc0_ebase(cpu_env, arg); register_name =3D "EBase"; @@ -8759,16 +8759,16 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, = int reg, int sel) break; case CP0_REGISTER_15: switch (sel) { - case 0: + case CP0_REG15__PRID: gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PRid)); register_name =3D "PRid"; break; - case 1: + case CP0_REG15__EBASE: check_insn(ctx, ISA_MIPS32R2); tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_EBase)); register_name =3D "EBase"; break; - case 3: + case CP0_REG15__CMGCRBASE: check_insn(ctx, ISA_MIPS32R2); CP0_CHECK(ctx->cmgcr); tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_CMGCRBa= se)); @@ -9486,11 +9486,11 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, = int reg, int sel) break; case CP0_REGISTER_15: switch (sel) { - case 0: + case CP0_REG15__PRID: /* ignored */ register_name =3D "PRid"; break; - case 1: + case CP0_REG15__EBASE: check_insn(ctx, ISA_MIPS32R2); gen_helper_mtc0_ebase(cpu_env, arg); register_name =3D "EBase"; --=20 2.7.4