From nobody Tue Feb 10 11:14:31 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1567010433; cv=none; d=zoho.com; s=zohoarc; b=k0ehOvhLRA6hdW+baGsFt4q0odNfVV6Iy0NHtu1thhIM4xTd6rVW1dxejSFNlX5iKn8lgPrLQ+qLMZk4/gtHG9BB2YscXCOixGx2hMlKBHN1iDNODeLngUr0pP4t3N6BcGHa0yfG6S94Lv4ECvRpzFgiZjpmmyhpPQX6xqL0DQI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1567010433; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=wjNHiyvGu/iCOkyL30yG/pNalO0/MFmC3uGyMpe53Yw=; b=nfQa1YtJ5C4INDO64OgKC0g3E3AP0cnic2O5E+5Cdyv61ggvfFWh3WAsHmuZcte/pWcuvcMK1EYpSP2dg7wgG889hBCeJKKKhSV7oY8fmRYVBO+KG1dHFpLF4U9Lm/W8Fl7alXfoKzM6oo1incs+qUpuxF9Wg/gyaOWbboDC9jg= ARC-Authentication-Results: i=1; mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 156701043391740.84511015682608; Wed, 28 Aug 2019 09:40:33 -0700 (PDT) Received: from localhost ([::1]:38456 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i30zk-0002td-Iv for importer@patchew.org; Wed, 28 Aug 2019 12:40:28 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:34595) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i30my-00076L-M6 for qemu-devel@nongnu.org; Wed, 28 Aug 2019 12:27:18 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1i30mx-000801-3S for qemu-devel@nongnu.org; Wed, 28 Aug 2019 12:27:16 -0400 Received: from mx2.rt-rk.com ([89.216.37.149]:55321 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1i30mw-0007mP-QG for qemu-devel@nongnu.org; Wed, 28 Aug 2019 12:27:14 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id 47A881A22C4; Wed, 28 Aug 2019 18:27:00 +0200 (CEST) Received: from rtrkw774-lin.domain.local (rtrkw774-lin.domain.local [10.10.13.43]) by mail.rt-rk.com (Postfix) with ESMTPSA id 05EAF1A22BC; Wed, 28 Aug 2019 18:27:00 +0200 (CEST) X-Virus-Scanned: amavisd-new at rt-rk.com From: Aleksandar Markovic To: qemu-devel@nongnu.org Date: Wed, 28 Aug 2019 18:26:35 +0200 Message-Id: <1567009614-12438-12-git-send-email-aleksandar.markovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1567009614-12438-1-git-send-email-aleksandar.markovic@rt-rk.com> References: <1567009614-12438-1-git-send-email-aleksandar.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 89.216.37.149 Subject: [Qemu-devel] [PATCH v2 11/30] target/mips: Clean up handling of CP0 register 10 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: arikalo@wavecomp.com, amarkovic@wavecomp.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Aleksandar Markovic Clean up handling of CP0 register 10. Signed-off-by: Aleksandar Markovic --- target/mips/cpu.h | 1 + target/mips/translate.c | 8 ++++---- 2 files changed, 5 insertions(+), 4 deletions(-) diff --git a/target/mips/cpu.h b/target/mips/cpu.h index 68a2104..42f3c77 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -344,6 +344,7 @@ typedef struct mips_def_t mips_def_t; #define CP0_REG10__ENTRYHI 0 #define CP0_REG10__GUESTCTL1 4 #define CP0_REG10__GUESTCTL2 5 +#define CP0_REG10__GUESTCTL3 6 /* CP0 Register 11 */ #define CP0_REG11__COMPARE 0 #define CP0_REG11__GUESTCTL0EXT 4 diff --git a/target/mips/translate.c b/target/mips/translate.c index 33a882c..1a97072 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -7203,7 +7203,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int= reg, int sel) break; case CP0_REGISTER_10: switch (sel) { - case 0: + case CP0_REG10__ENTRYHI: tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_EntryHi= )); tcg_gen_ext32s_tl(arg, arg); register_name =3D "EntryHi"; @@ -7925,7 +7925,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int= reg, int sel) break; case CP0_REGISTER_10: switch (sel) { - case 0: + case CP0_REG10__ENTRYHI: gen_helper_mtc0_entryhi(cpu_env, arg); register_name =3D "EntryHi"; break; @@ -8693,7 +8693,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, in= t reg, int sel) break; case CP0_REGISTER_10: switch (sel) { - case 0: + case CP0_REG10__ENTRYHI: tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_EntryHi= )); register_name =3D "EntryHi"; break; @@ -9400,7 +9400,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, in= t reg, int sel) break; case CP0_REGISTER_10: switch (sel) { - case 0: + case CP0_REG10__ENTRYHI: gen_helper_mtc0_entryhi(cpu_env, arg); register_name =3D "EntryHi"; break; --=20 2.7.4