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X-Received-From: 2607:f8b0:4864:20::643 Subject: [Qemu-devel] [PATCH v6 09/30] riscv: sifive: Rename sifive_prci.{c, h} to sifive_e_prci.{c, h} X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Current SiFive PRCI model only works with sifive_e machine, as it only emulates registers or PRCI block in the FE310 SoC. Rename the file name to make it clear that it is for sifive_e. This also prefix "sifive_e"/"SIFIVE_E" for all macros, variables and functions. Signed-off-by: Bin Meng Reviewed-by: Chih-Min Chao Reviewed-by: Alistair Francis --- Changes in v6: None Changes in v5: None Changes in v4: - prefix all macros/variables/functions with SIFIVE_E/sifive_e in the sifive_e_prci driver Changes in v3: None Changes in v2: None hw/riscv/Makefile.objs | 2 +- hw/riscv/sifive_e.c | 4 +- hw/riscv/{sifive_prci.c =3D> sifive_e_prci.c} | 79 ++++++++++++++---------= ------ include/hw/riscv/sifive_e_prci.h | 69 +++++++++++++++++++++++++ include/hw/riscv/sifive_prci.h | 69 ------------------------- 5 files changed, 111 insertions(+), 112 deletions(-) rename hw/riscv/{sifive_prci.c =3D> sifive_e_prci.c} (51%) create mode 100644 include/hw/riscv/sifive_e_prci.h delete mode 100644 include/hw/riscv/sifive_prci.h diff --git a/hw/riscv/Makefile.objs b/hw/riscv/Makefile.objs index eb9d4f9..c859697 100644 --- a/hw/riscv/Makefile.objs +++ b/hw/riscv/Makefile.objs @@ -2,9 +2,9 @@ obj-y +=3D boot.o obj-$(CONFIG_SPIKE) +=3D riscv_htif.o obj-$(CONFIG_HART) +=3D riscv_hart.o obj-$(CONFIG_SIFIVE_E) +=3D sifive_e.o +obj-$(CONFIG_SIFIVE_E) +=3D sifive_e_prci.o obj-$(CONFIG_SIFIVE) +=3D sifive_clint.o obj-$(CONFIG_SIFIVE) +=3D sifive_gpio.o -obj-$(CONFIG_SIFIVE) +=3D sifive_prci.o obj-$(CONFIG_SIFIVE) +=3D sifive_plic.o obj-$(CONFIG_SIFIVE) +=3D sifive_test.o obj-$(CONFIG_SIFIVE_U) +=3D sifive_u.o diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c index 2a499d8..2d67670 100644 --- a/hw/riscv/sifive_e.c +++ b/hw/riscv/sifive_e.c @@ -41,9 +41,9 @@ #include "hw/riscv/riscv_hart.h" #include "hw/riscv/sifive_plic.h" #include "hw/riscv/sifive_clint.h" -#include "hw/riscv/sifive_prci.h" #include "hw/riscv/sifive_uart.h" #include "hw/riscv/sifive_e.h" +#include "hw/riscv/sifive_e_prci.h" #include "hw/riscv/boot.h" #include "chardev/char.h" #include "sysemu/arch_init.h" @@ -174,7 +174,7 @@ static void riscv_sifive_e_soc_realize(DeviceState *dev= , Error **errp) SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE); sifive_mmio_emulate(sys_mem, "riscv.sifive.e.aon", memmap[SIFIVE_E_AON].base, memmap[SIFIVE_E_AON].size); - sifive_prci_create(memmap[SIFIVE_E_PRCI].base); + sifive_e_prci_create(memmap[SIFIVE_E_PRCI].base); =20 /* GPIO */ =20 diff --git a/hw/riscv/sifive_prci.c b/hw/riscv/sifive_e_prci.c similarity index 51% rename from hw/riscv/sifive_prci.c rename to hw/riscv/sifive_e_prci.c index 1957dcd..c514032 100644 --- a/hw/riscv/sifive_prci.c +++ b/hw/riscv/sifive_e_prci.c @@ -1,5 +1,5 @@ /* - * QEMU SiFive PRCI (Power, Reset, Clock, Interrupt) + * QEMU SiFive E PRCI (Power, Reset, Clock, Interrupt) * * Copyright (c) 2017 SiFive, Inc. * @@ -22,19 +22,19 @@ #include "hw/sysbus.h" #include "qemu/log.h" #include "qemu/module.h" -#include "hw/riscv/sifive_prci.h" +#include "hw/riscv/sifive_e_prci.h" =20 -static uint64_t sifive_prci_read(void *opaque, hwaddr addr, unsigned int s= ize) +static uint64_t sifive_e_prci_read(void *opaque, hwaddr addr, unsigned int= size) { - SiFivePRCIState *s =3D opaque; + SiFiveEPRCIState *s =3D opaque; switch (addr) { - case SIFIVE_PRCI_HFROSCCFG: + case SIFIVE_E_PRCI_HFROSCCFG: return s->hfrosccfg; - case SIFIVE_PRCI_HFXOSCCFG: + case SIFIVE_E_PRCI_HFXOSCCFG: return s->hfxosccfg; - case SIFIVE_PRCI_PLLCFG: + case SIFIVE_E_PRCI_PLLCFG: return s->pllcfg; - case SIFIVE_PRCI_PLLOUTDIV: + case SIFIVE_E_PRCI_PLLOUTDIV: return s->plloutdiv; } qemu_log_mask(LOG_GUEST_ERROR, "%s: read: addr=3D0x%x\n", @@ -42,27 +42,27 @@ static uint64_t sifive_prci_read(void *opaque, hwaddr a= ddr, unsigned int size) return 0; } =20 -static void sifive_prci_write(void *opaque, hwaddr addr, - uint64_t val64, unsigned int size) +static void sifive_e_prci_write(void *opaque, hwaddr addr, + uint64_t val64, unsigned int size) { - SiFivePRCIState *s =3D opaque; + SiFiveEPRCIState *s =3D opaque; switch (addr) { - case SIFIVE_PRCI_HFROSCCFG: + case SIFIVE_E_PRCI_HFROSCCFG: s->hfrosccfg =3D (uint32_t) val64; /* OSC stays ready */ - s->hfrosccfg |=3D SIFIVE_PRCI_HFROSCCFG_RDY; + s->hfrosccfg |=3D SIFIVE_E_PRCI_HFROSCCFG_RDY; break; - case SIFIVE_PRCI_HFXOSCCFG: + case SIFIVE_E_PRCI_HFXOSCCFG: s->hfxosccfg =3D (uint32_t) val64; /* OSC stays ready */ - s->hfxosccfg |=3D SIFIVE_PRCI_HFXOSCCFG_RDY; + s->hfxosccfg |=3D SIFIVE_E_PRCI_HFXOSCCFG_RDY; break; - case SIFIVE_PRCI_PLLCFG: + case SIFIVE_E_PRCI_PLLCFG: s->pllcfg =3D (uint32_t) val64; /* PLL stays locked */ - s->pllcfg |=3D SIFIVE_PRCI_PLLCFG_LOCK; + s->pllcfg |=3D SIFIVE_E_PRCI_PLLCFG_LOCK; break; - case SIFIVE_PRCI_PLLOUTDIV: + case SIFIVE_E_PRCI_PLLOUTDIV: s->plloutdiv =3D (uint32_t) val64; break; default: @@ -71,9 +71,9 @@ static void sifive_prci_write(void *opaque, hwaddr addr, } } =20 -static const MemoryRegionOps sifive_prci_ops =3D { - .read =3D sifive_prci_read, - .write =3D sifive_prci_write, +static const MemoryRegionOps sifive_e_prci_ops =3D { + .read =3D sifive_e_prci_read, + .write =3D sifive_e_prci_write, .endianness =3D DEVICE_NATIVE_ENDIAN, .valid =3D { .min_access_size =3D 4, @@ -81,43 +81,42 @@ static const MemoryRegionOps sifive_prci_ops =3D { } }; =20 -static void sifive_prci_init(Object *obj) +static void sifive_e_prci_init(Object *obj) { - SiFivePRCIState *s =3D SIFIVE_PRCI(obj); + SiFiveEPRCIState *s =3D SIFIVE_E_PRCI(obj); =20 - memory_region_init_io(&s->mmio, obj, &sifive_prci_ops, s, - TYPE_SIFIVE_PRCI, 0x8000); + memory_region_init_io(&s->mmio, obj, &sifive_e_prci_ops, s, + TYPE_SIFIVE_E_PRCI, 0x8000); sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio); =20 - s->hfrosccfg =3D (SIFIVE_PRCI_HFROSCCFG_RDY | SIFIVE_PRCI_HFROSCCFG_EN= ); - s->hfxosccfg =3D (SIFIVE_PRCI_HFROSCCFG_RDY | SIFIVE_PRCI_HFROSCCFG_EN= ); - s->pllcfg =3D (SIFIVE_PRCI_PLLCFG_REFSEL | SIFIVE_PRCI_PLLCFG_BYPASS | - SIFIVE_PRCI_PLLCFG_LOCK); - s->plloutdiv =3D SIFIVE_PRCI_PLLOUTDIV_DIV1; - + s->hfrosccfg =3D (SIFIVE_E_PRCI_HFROSCCFG_RDY | SIFIVE_E_PRCI_HFROSCCF= G_EN); + s->hfxosccfg =3D (SIFIVE_E_PRCI_HFROSCCFG_RDY | SIFIVE_E_PRCI_HFROSCCF= G_EN); + s->pllcfg =3D (SIFIVE_E_PRCI_PLLCFG_REFSEL | SIFIVE_E_PRCI_PLLCFG_BYPA= SS | + SIFIVE_E_PRCI_PLLCFG_LOCK); + s->plloutdiv =3D SIFIVE_E_PRCI_PLLOUTDIV_DIV1; } =20 -static const TypeInfo sifive_prci_info =3D { - .name =3D TYPE_SIFIVE_PRCI, +static const TypeInfo sifive_e_prci_info =3D { + .name =3D TYPE_SIFIVE_E_PRCI, .parent =3D TYPE_SYS_BUS_DEVICE, - .instance_size =3D sizeof(SiFivePRCIState), - .instance_init =3D sifive_prci_init, + .instance_size =3D sizeof(SiFiveEPRCIState), + .instance_init =3D sifive_e_prci_init, }; =20 -static void sifive_prci_register_types(void) +static void sifive_e_prci_register_types(void) { - type_register_static(&sifive_prci_info); + type_register_static(&sifive_e_prci_info); } =20 -type_init(sifive_prci_register_types) +type_init(sifive_e_prci_register_types) =20 =20 /* * Create PRCI device. */ -DeviceState *sifive_prci_create(hwaddr addr) +DeviceState *sifive_e_prci_create(hwaddr addr) { - DeviceState *dev =3D qdev_create(NULL, TYPE_SIFIVE_PRCI); + DeviceState *dev =3D qdev_create(NULL, TYPE_SIFIVE_E_PRCI); qdev_init_nofail(dev); sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, addr); return dev; diff --git a/include/hw/riscv/sifive_e_prci.h b/include/hw/riscv/sifive_e_p= rci.h new file mode 100644 index 0000000..c4b76aa --- /dev/null +++ b/include/hw/riscv/sifive_e_prci.h @@ -0,0 +1,69 @@ +/* + * QEMU SiFive E PRCI (Power, Reset, Clock, Interrupt) interface + * + * Copyright (c) 2017 SiFive, Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License f= or + * more details. + * + * You should have received a copy of the GNU General Public License along= with + * this program. If not, see . + */ + +#ifndef HW_SIFIVE_E_PRCI_H +#define HW_SIFIVE_E_PRCI_H + +enum { + SIFIVE_E_PRCI_HFROSCCFG =3D 0x0, + SIFIVE_E_PRCI_HFXOSCCFG =3D 0x4, + SIFIVE_E_PRCI_PLLCFG =3D 0x8, + SIFIVE_E_PRCI_PLLOUTDIV =3D 0xC +}; + +enum { + SIFIVE_E_PRCI_HFROSCCFG_RDY =3D (1 << 31), + SIFIVE_E_PRCI_HFROSCCFG_EN =3D (1 << 30) +}; + +enum { + SIFIVE_E_PRCI_HFXOSCCFG_RDY =3D (1 << 31), + SIFIVE_E_PRCI_HFXOSCCFG_EN =3D (1 << 30) +}; + +enum { + SIFIVE_E_PRCI_PLLCFG_PLLSEL =3D (1 << 16), + SIFIVE_E_PRCI_PLLCFG_REFSEL =3D (1 << 17), + SIFIVE_E_PRCI_PLLCFG_BYPASS =3D (1 << 18), + SIFIVE_E_PRCI_PLLCFG_LOCK =3D (1 << 31) +}; + +enum { + SIFIVE_E_PRCI_PLLOUTDIV_DIV1 =3D (1 << 8) +}; + +#define TYPE_SIFIVE_E_PRCI "riscv.sifive.e.prci" + +#define SIFIVE_E_PRCI(obj) \ + OBJECT_CHECK(SiFiveEPRCIState, (obj), TYPE_SIFIVE_E_PRCI) + +typedef struct SiFiveEPRCIState { + /*< private >*/ + SysBusDevice parent_obj; + + /*< public >*/ + MemoryRegion mmio; + uint32_t hfrosccfg; + uint32_t hfxosccfg; + uint32_t pllcfg; + uint32_t plloutdiv; +} SiFiveEPRCIState; + +DeviceState *sifive_e_prci_create(hwaddr addr); + +#endif diff --git a/include/hw/riscv/sifive_prci.h b/include/hw/riscv/sifive_prci.h deleted file mode 100644 index bd51c4a..0000000 --- a/include/hw/riscv/sifive_prci.h +++ /dev/null @@ -1,69 +0,0 @@ -/* - * QEMU SiFive PRCI (Power, Reset, Clock, Interrupt) interface - * - * Copyright (c) 2017 SiFive, Inc. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2 or later, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License f= or - * more details. - * - * You should have received a copy of the GNU General Public License along= with - * this program. If not, see . - */ - -#ifndef HW_SIFIVE_PRCI_H -#define HW_SIFIVE_PRCI_H - -enum { - SIFIVE_PRCI_HFROSCCFG =3D 0x0, - SIFIVE_PRCI_HFXOSCCFG =3D 0x4, - SIFIVE_PRCI_PLLCFG =3D 0x8, - SIFIVE_PRCI_PLLOUTDIV =3D 0xC -}; - -enum { - SIFIVE_PRCI_HFROSCCFG_RDY =3D (1 << 31), - SIFIVE_PRCI_HFROSCCFG_EN =3D (1 << 30) -}; - -enum { - SIFIVE_PRCI_HFXOSCCFG_RDY =3D (1 << 31), - SIFIVE_PRCI_HFXOSCCFG_EN =3D (1 << 30) -}; - -enum { - SIFIVE_PRCI_PLLCFG_PLLSEL =3D (1 << 16), - SIFIVE_PRCI_PLLCFG_REFSEL =3D (1 << 17), - SIFIVE_PRCI_PLLCFG_BYPASS =3D (1 << 18), - SIFIVE_PRCI_PLLCFG_LOCK =3D (1 << 31) -}; - -enum { - SIFIVE_PRCI_PLLOUTDIV_DIV1 =3D (1 << 8) -}; - -#define TYPE_SIFIVE_PRCI "riscv.sifive.prci" - -#define SIFIVE_PRCI(obj) \ - OBJECT_CHECK(SiFivePRCIState, (obj), TYPE_SIFIVE_PRCI) - -typedef struct SiFivePRCIState { - /*< private >*/ - SysBusDevice parent_obj; - - /*< public >*/ - MemoryRegion mmio; - uint32_t hfrosccfg; - uint32_t hfxosccfg; - uint32_t pllcfg; - uint32_t plloutdiv; -} SiFivePRCIState; - -DeviceState *sifive_prci_create(hwaddr addr); - -#endif --=20 2.7.4