From nobody Tue Feb 10 20:48:09 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1566475661; cv=none; d=zoho.com; s=zohoarc; b=UVzuhRqHDbtxfYWfLnZbElnSY3fnY0SqoUoDl6iYbYd+ud2sJQpxwuUIMwwtL/dJx6SMyS2o0blmW/+tYdGN/njBwytUTE5+CSoWgBvksG+bYY/qDaJkFyoh1MmD3FNTIsYtWSXqoZR2tAOZugQX3gIb//qgKypmPwzVPMRmneI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1566475661; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=gUOI03wssN7TRY0YbPfqH1Sd5ll6KfIi7ubxBUfLNig=; b=gVxqWdVeMmdWNHgzWjblvly7caMeSQlSzSHOdFWl65mw6YVwN+qt/wUyvYE6QEdT4/0LTDca3nagSVPU9P2ScEO0s/c46tfjJ17FsFm0qKQrcQYHFiJqB2lYdSg686C2+isvTIb8zzW9XDke+agIGfnDzP8bDqM14nIuoDVU2l0= ARC-Authentication-Results: i=1; mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1566475661476829.8265203873653; Thu, 22 Aug 2019 05:07:41 -0700 (PDT) Received: from localhost ([::1]:41742 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i0lsS-0007sc-F9 for importer@patchew.org; Thu, 22 Aug 2019 08:07:40 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:60222) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i0lPO-0005FE-Fw for qemu-devel@nongnu.org; Thu, 22 Aug 2019 07:37:40 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1i0lPJ-00087d-QK for qemu-devel@nongnu.org; Thu, 22 Aug 2019 07:37:38 -0400 Received: from mx2.rt-rk.com ([89.216.37.149]:49986 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1i0lPI-0007sS-K3 for qemu-devel@nongnu.org; Thu, 22 Aug 2019 07:37:33 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id 5882D1A2077; Thu, 22 Aug 2019 13:35:59 +0200 (CEST) Received: from rtrkw774-lin.domain.local (rtrkw774-lin.domain.local [10.10.13.43]) by mail.rt-rk.com (Postfix) with ESMTPSA id 1C9A31A20CC; Thu, 22 Aug 2019 13:35:59 +0200 (CEST) X-Virus-Scanned: amavisd-new at rt-rk.com From: Aleksandar Markovic To: qemu-devel@nongnu.org Date: Thu, 22 Aug 2019 13:35:47 +0200 Message-Id: <1566473750-17743-24-git-send-email-aleksandar.markovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1566473750-17743-1-git-send-email-aleksandar.markovic@rt-rk.com> References: <1566473750-17743-1-git-send-email-aleksandar.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 89.216.37.149 Subject: [Qemu-devel] [PATCH 23/26] target/mips: Clean up handling of CP0 register 28 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: aurelien@aurel32.net, amarkovic@wavecomp.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Aleksandar Markovic Clean up handling of CP0 register 28. Signed-off-by: Aleksandar Markovic --- target/mips/cpu.h | 24 +++++++++++-------- target/mips/translate.c | 64 ++++++++++++++++++++++++---------------------= ---- 2 files changed, 46 insertions(+), 42 deletions(-) diff --git a/target/mips/cpu.h b/target/mips/cpu.h index 80c896b..55ada8c 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -235,12 +235,12 @@ typedef struct mips_def_t mips_def_t; * * 0 DataLo DataHi ErrorEPC DESAVE * 1 TagLo TagHi - * 2 DataLo DataHi KScratch - * 3 TagLo TagHi KScratch - * 4 DataLo DataHi KScratch - * 5 TagLo TagHi KScratch - * 6 DataLo DataHi KScratch - * 7 TagLo TagHi KScratch + * 2 DataLo1 DataHi KScratch + * 3 TagLo1 TagHi KScratch + * 4 DataLo2 DataHi KScratch + * 5 TagLo2 TagHi KScratch + * 6 DataLo3 DataHi KScratch + * 7 TagLo3 TagHi KScratch * */ #define CP0_REGISTER_00 0 @@ -423,10 +423,14 @@ typedef struct mips_def_t mips_def_t; /* CP0 Register 27 */ #define CP0_REG27__CACHERR 0 /* CP0 Register 28 */ -#define CP0_REG28__ITAGLO 0 -#define CP0_REG28__IDATALO 1 -#define CP0_REG28__DTAGLO 2 -#define CP0_REG28__DDATALO 3 +#define CP0_REG28__TAGLO 0 +#define CP0_REG28__DATALO 1 +#define CP0_REG28__TAGLO1 2 +#define CP0_REG28__DATALO1 3 +#define CP0_REG28__TAGLO2 4 +#define CP0_REG28__DATALO2 5 +#define CP0_REG28__TAGLO3 6 +#define CP0_REG28__DATALO3 7 /* CP0 Register 29 */ #define CP0_REG29__IDATAHI 1 #define CP0_REG29__DDATAHI 3 diff --git a/target/mips/translate.c b/target/mips/translate.c index 936c51c..6f5eed7 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -7523,10 +7523,10 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, i= nt reg, int sel) break; case CP0_REGISTER_28: switch (sel) { - case 0: - case 2: - case 4: - case 6: + case CP0_REG28__TAGLO: + case CP0_REG28__TAGLO1: + case CP0_REG28__TAGLO2: + case CP0_REG28__TAGLO3: { TCGv_i64 tmp =3D tcg_temp_new_i64(); tcg_gen_ld_i64(tmp, cpu_env, offsetof(CPUMIPSState, CP0_Ta= gLo)); @@ -7535,10 +7535,10 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, i= nt reg, int sel) } register_name =3D "TagLo"; break; - case 1: - case 3: - case 5: - case 7: + case CP0_REG28__DATALO: + case CP0_REG28__DATALO1: + case CP0_REG28__DATALO2: + case CP0_REG28__DATALO3: gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_DataLo)); register_name =3D "DataLo"; break; @@ -8282,17 +8282,17 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, i= nt reg, int sel) break; case CP0_REGISTER_28: switch (sel) { - case 0: - case 2: - case 4: - case 6: + case CP0_REG28__TAGLO: + case CP0_REG28__TAGLO1: + case CP0_REG28__TAGLO2: + case CP0_REG28__TAGLO3: gen_helper_mtc0_taglo(cpu_env, arg); register_name =3D "TagLo"; break; - case 1: - case 3: - case 5: - case 7: + case CP0_REG28__DATALO: + case CP0_REG28__DATALO1: + case CP0_REG28__DATALO2: + case CP0_REG28__DATALO3: gen_helper_mtc0_datalo(cpu_env, arg); register_name =3D "DataLo"; break; @@ -9018,17 +9018,17 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, = int reg, int sel) break; case CP0_REGISTER_28: switch (sel) { - case 0: - case 2: - case 4: - case 6: + case CP0_REG28__TAGLO: + case CP0_REG28__TAGLO1: + case CP0_REG28__TAGLO2: + case CP0_REG28__TAGLO3: gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_TagLo)); register_name =3D "TagLo"; break; - case 1: - case 3: - case 5: - case 7: + case CP0_REG28__DATALO: + case CP0_REG28__DATALO1: + case CP0_REG28__DATALO2: + case CP0_REG28__DATALO3: gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_DataLo)); register_name =3D "DataLo"; break; @@ -9758,17 +9758,17 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, = int reg, int sel) break; case CP0_REGISTER_28: switch (sel) { - case 0: - case 2: - case 4: - case 6: + case CP0_REG28__TAGLO: + case CP0_REG28__TAGLO1: + case CP0_REG28__TAGLO2: + case CP0_REG28__TAGLO3: gen_helper_mtc0_taglo(cpu_env, arg); register_name =3D "TagLo"; break; - case 1: - case 3: - case 5: - case 7: + case CP0_REG28__DATALO: + case CP0_REG28__DATALO1: + case CP0_REG28__DATALO2: + case CP0_REG28__DATALO3: gen_helper_mtc0_datalo(cpu_env, arg); register_name =3D "DataLo"; break; --=20 2.7.4