From nobody Tue Feb 10 02:00:43 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1566475201; cv=none; d=zoho.com; s=zohoarc; b=mknjlv/5JAtnoAMjFHhchxW5EEWd96LzX3UHRAhaxf8ibmdVwsfwgCqLDIaXTCnwkoP2BJSKU8+M7YzJP787iL8eXMh1R1u38a7JSoq0M74A5C91potvY5ZKBRHLHZXo6BcMQkc3wTHudn/zz8vU9XHhYRl9tRaQXvBnLTkgHU0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1566475201; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=zabDMeE5mr+ckhq5V2zzeDgkuzpDU8XCtYL2E1W3wpw=; b=OX43/Iat3+EDEBCb+REE1cLG5nnG7YoDFuE8dFMjTOz+evNklTIxXRcVArBI1OouZ5eH2iBCs70kwtAYl5LOCwhON0BqAzTb8ndjm6IHS+nkMPGIMqa8kuUxBZQ2TpXjtxpfJxqYeZfJFTNhllrAwDAcnsWmSbo1UiGf4Hvdka0= ARC-Authentication-Results: i=1; mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 156647520141127.008209005077106; Thu, 22 Aug 2019 05:00:01 -0700 (PDT) Received: from localhost ([::1]:41522 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i0ll1-0007Lb-Rs for importer@patchew.org; Thu, 22 Aug 2019 07:59:59 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:60160) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i0lPM-0005B0-7G for qemu-devel@nongnu.org; Thu, 22 Aug 2019 07:37:38 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1i0lPJ-00086l-1f for qemu-devel@nongnu.org; Thu, 22 Aug 2019 07:37:35 -0400 Received: from mx2.rt-rk.com ([89.216.37.149]:48296 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1i0lPI-0007lI-GU for qemu-devel@nongnu.org; Thu, 22 Aug 2019 07:37:32 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id 11C241A20A0; Thu, 22 Aug 2019 13:35:59 +0200 (CEST) Received: from rtrkw774-lin.domain.local (rtrkw774-lin.domain.local [10.10.13.43]) by mail.rt-rk.com (Postfix) with ESMTPSA id D23801A20AB; Thu, 22 Aug 2019 13:35:58 +0200 (CEST) X-Virus-Scanned: amavisd-new at rt-rk.com From: Aleksandar Markovic To: qemu-devel@nongnu.org Date: Thu, 22 Aug 2019 13:35:41 +0200 Message-Id: <1566473750-17743-18-git-send-email-aleksandar.markovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1566473750-17743-1-git-send-email-aleksandar.markovic@rt-rk.com> References: <1566473750-17743-1-git-send-email-aleksandar.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 89.216.37.149 Subject: [Qemu-devel] [PATCH 17/26] target/mips: Clean up handling of CP0 register 20 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: aurelien@aurel32.net, amarkovic@wavecomp.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Aleksandar Markovic Clean up handling of CP0 register 20. Signed-off-by: Aleksandar Markovic --- target/mips/translate.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/target/mips/translate.c b/target/mips/translate.c index 40df031..175f6dc 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -7388,7 +7388,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int= reg, int sel) break; case CP0_REGISTER_20: switch (sel) { - case 0: + case CP0_REG20__XCONTEXT: #if defined(TARGET_MIPS64) check_insn(ctx, ISA_MIPS3); tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_XContex= t)); @@ -8127,7 +8127,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int= reg, int sel) break; case CP0_REGISTER_20: switch (sel) { - case 0: + case CP0_REG20__XCONTEXT: #if defined(TARGET_MIPS64) check_insn(ctx, ISA_MIPS3); gen_helper_mtc0_xcontext(cpu_env, arg); @@ -8872,7 +8872,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, in= t reg, int sel) break; case CP0_REGISTER_20: switch (sel) { - case 0: + case CP0_REG20__XCONTEXT: check_insn(ctx, ISA_MIPS3); tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_XContex= t)); register_name =3D "XContext"; @@ -9593,7 +9593,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, in= t reg, int sel) break; case CP0_REGISTER_20: switch (sel) { - case 0: + case CP0_REG20__XCONTEXT: check_insn(ctx, ISA_MIPS3); gen_helper_mtc0_xcontext(cpu_env, arg); register_name =3D "XContext"; --=20 2.7.4