From nobody Tue Feb 10 05:39:54 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1566475266; cv=none; d=zoho.com; s=zohoarc; b=ft6dT5G9j57r21JMBCkGPlddCdfBZ1hasM7zbffMFA7uglZZv+l4ntimnsMb/Enr6/Zo85SKL1BjFCJfKwNQF6RfTnckTLpaHDw0u3T5jKV3kKP4Sb5jIH2UeRyKwsESVdFYv6gQ2xKybIMTaxBXyDuOTzYBz7PHzPzL8FBaW1g= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1566475266; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=KeAPvyF8EHs4QAUsPrw3Dqn2q1x6x3kSTeUJ211EQCg=; b=BXjxU/7iGL/5RLPVN1PTcMaTlqP7uMTUaNco4M9qY7549583+6UOmBllJYDC9+pOKWqgjYTYH7UPqL0tLTt5dGsGWjB4O+MGpJOJ9hS/j9eSQiNRT0p0oW1nIqcjOGVjOQzR/0GMWrE4rznQyv4CJxT/cgEGzfuDXb24TrFrCYQ= ARC-Authentication-Results: i=1; mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 156647526670556.86020559433109; Thu, 22 Aug 2019 05:01:06 -0700 (PDT) Received: from localhost ([::1]:41532 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i0lm3-0008Rf-Qd for importer@patchew.org; Thu, 22 Aug 2019 08:01:03 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:60066) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i0lPH-00051f-89 for qemu-devel@nongnu.org; Thu, 22 Aug 2019 07:37:34 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1i0lP9-0007xV-3E for qemu-devel@nongnu.org; Thu, 22 Aug 2019 07:37:30 -0400 Received: from mx2.rt-rk.com ([89.216.37.149]:48211 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1i0lP8-0007ik-BR for qemu-devel@nongnu.org; Thu, 22 Aug 2019 07:37:22 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id B46691A2073; Thu, 22 Aug 2019 13:35:58 +0200 (CEST) Received: from rtrkw774-lin.domain.local (rtrkw774-lin.domain.local [10.10.13.43]) by mail.rt-rk.com (Postfix) with ESMTPSA id 87C241A2044; Thu, 22 Aug 2019 13:35:58 +0200 (CEST) X-Virus-Scanned: amavisd-new at rt-rk.com From: Aleksandar Markovic To: qemu-devel@nongnu.org Date: Thu, 22 Aug 2019 13:35:35 +0200 Message-Id: <1566473750-17743-12-git-send-email-aleksandar.markovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1566473750-17743-1-git-send-email-aleksandar.markovic@rt-rk.com> References: <1566473750-17743-1-git-send-email-aleksandar.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 89.216.37.149 Subject: [Qemu-devel] [PATCH 11/26] target/mips: Clean up handling of CP0 register 12 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: aurelien@aurel32.net, amarkovic@wavecomp.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Aleksandar Markovic Clean up handling of CP0 register 12. Signed-off-by: Aleksandar Markovic --- target/mips/cpu.h | 3 +++ target/mips/translate.c | 32 ++++++++++++++++---------------- 2 files changed, 19 insertions(+), 16 deletions(-) diff --git a/target/mips/cpu.h b/target/mips/cpu.h index 5e08b78..d61b8c0 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -349,6 +349,9 @@ typedef struct mips_def_t mips_def_t; #define CP0_REG12__STATUS 0 #define CP0_REG12__INTCTL 1 #define CP0_REG12__SRSCTL 2 +#define CP0_REG12__SRSMAP 3 +#define CP0_REG12__VIEW_IPL 4 +#define CP0_REG12__SRSMAP2 5 #define CP0_REG12__GUESTCTL0 6 #define CP0_REG12__GTOFFSET 7 /* CP0 Register 13 */ diff --git a/target/mips/translate.c b/target/mips/translate.c index 87257d7..642c108 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -7224,21 +7224,21 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, i= nt reg, int sel) break; case CP0_REGISTER_12: switch (sel) { - case 0: + case CP0_REG12__STATUS: gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Status)); register_name =3D "Status"; break; - case 1: + case CP0_REG12__INTCTL: check_insn(ctx, ISA_MIPS32R2); gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_IntCtl)); register_name =3D "IntCtl"; break; - case 2: + case CP0_REG12__SRSCTL: check_insn(ctx, ISA_MIPS32R2); gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSCtl)); register_name =3D "SRSCtl"; break; - case 3: + case CP0_REG12__SRSMAP: check_insn(ctx, ISA_MIPS32R2); gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSMap)); register_name =3D "SRSMap"; @@ -7944,7 +7944,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int= reg, int sel) break; case CP0_REGISTER_12: switch (sel) { - case 0: + case CP0_REG12__STATUS: save_cpu_state(ctx, 1); gen_helper_mtc0_status(cpu_env, arg); /* DISAS_STOP isn't good enough here, hflags may have changed.= */ @@ -7952,21 +7952,21 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, i= nt reg, int sel) ctx->base.is_jmp =3D DISAS_EXIT; register_name =3D "Status"; break; - case 1: + case CP0_REG12__INTCTL: check_insn(ctx, ISA_MIPS32R2); gen_helper_mtc0_intctl(cpu_env, arg); /* Stop translation as we may have switched the execution mode= */ ctx->base.is_jmp =3D DISAS_STOP; register_name =3D "IntCtl"; break; - case 2: + case CP0_REG12__SRSCTL: check_insn(ctx, ISA_MIPS32R2); gen_helper_mtc0_srsctl(cpu_env, arg); /* Stop translation as we may have switched the execution mode= */ ctx->base.is_jmp =3D DISAS_STOP; register_name =3D "SRSCtl"; break; - case 3: + case CP0_REG12__SRSMAP: check_insn(ctx, ISA_MIPS32R2); gen_mtc0_store32(arg, offsetof(CPUMIPSState, CP0_SRSMap)); /* Stop translation as we may have switched the execution mode= */ @@ -8711,21 +8711,21 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, = int reg, int sel) break; case CP0_REGISTER_12: switch (sel) { - case 0: + case CP0_REG12__STATUS: gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Status)); register_name =3D "Status"; break; - case 1: + case CP0_REG12__INTCTL: check_insn(ctx, ISA_MIPS32R2); gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_IntCtl)); register_name =3D "IntCtl"; break; - case 2: + case CP0_REG12__SRSCTL: check_insn(ctx, ISA_MIPS32R2); gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSCtl)); register_name =3D "SRSCtl"; break; - case 3: + case CP0_REG12__SRSMAP: check_insn(ctx, ISA_MIPS32R2); gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSMap)); register_name =3D "SRSMap"; @@ -9419,7 +9419,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, in= t reg, int sel) break; case CP0_REGISTER_12: switch (sel) { - case 0: + case CP0_REG12__STATUS: save_cpu_state(ctx, 1); gen_helper_mtc0_status(cpu_env, arg); /* DISAS_STOP isn't good enough here, hflags may have changed.= */ @@ -9427,21 +9427,21 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, = int reg, int sel) ctx->base.is_jmp =3D DISAS_EXIT; register_name =3D "Status"; break; - case 1: + case CP0_REG12__INTCTL: check_insn(ctx, ISA_MIPS32R2); gen_helper_mtc0_intctl(cpu_env, arg); /* Stop translation as we may have switched the execution mode= */ ctx->base.is_jmp =3D DISAS_STOP; register_name =3D "IntCtl"; break; - case 2: + case CP0_REG12__SRSCTL: check_insn(ctx, ISA_MIPS32R2); gen_helper_mtc0_srsctl(cpu_env, arg); /* Stop translation as we may have switched the execution mode= */ ctx->base.is_jmp =3D DISAS_STOP; register_name =3D "SRSCtl"; break; - case 3: + case CP0_REG12__SRSMAP: check_insn(ctx, ISA_MIPS32R2); gen_mtc0_store32(arg, offsetof(CPUMIPSState, CP0_SRSMap)); /* Stop translation as we may have switched the execution mode= */ --=20 2.7.4