From nobody Tue May 7 19:36:37 2024 Delivered-To: importer@patchew.org Received-SPF: temperror (zoho.com: Error in retrieving data from DNS) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=temperror (zoho.com: Error in retrieving data from DNS) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1566473983; cv=none; d=zoho.com; s=zohoarc; b=Da425rKo36/BV+NwdulbNUtP+l+fLXb1Hadf2WWzcCqAHykJxloFcCFKZw47bR5tP+NzGrnNp8IkICm0TFQXhZ5VPKmmZe9tnqfHrhakGMOrbk1kcOdU6kelD54ztOq0iVgoBkDA5Ig4FcpUmBMkflaAzW4d3YlKmJYwmF62Ln4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1566473983; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=sKkqB+Q4o9tk01AA77UwegqsmkSLo7WOmNU1AaY5qVQ=; b=XVCC+4gGJLuAP1Yz/hq8e1/h5Pt700eja7NzBNvrgOGpqPD44AZ58U+6lK9Ss8DnXEjEmgrBOO4vw+Je3Oak9Uo3hFI7jRc5rG+83IxrI/dkzxnZE7TGxOJ5/CZ+mSi6zIX42M/+uMntZt4Si9KaguoCxG+Xjw0fBf1cQ4XsNI8= ARC-Authentication-Results: i=1; mx.zoho.com; spf=temperror (zoho.com: Error in retrieving data from DNS) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (209.51.188.17 [209.51.188.17]) by mx.zohomail.com with SMTPS id 1566473983987391.11097408696185; Thu, 22 Aug 2019 04:39:43 -0700 (PDT) Received: from localhost ([::1]:41286 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i0lRA-00070a-DF for importer@patchew.org; Thu, 22 Aug 2019 07:39:28 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:59838) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i0lP7-0004i6-2J for qemu-devel@nongnu.org; Thu, 22 Aug 2019 07:37:24 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1i0lOs-0007is-Rh for qemu-devel@nongnu.org; Thu, 22 Aug 2019 07:37:13 -0400 Received: from mx2.rt-rk.com ([89.216.37.149]:36709 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1i0lOs-0006xM-2V for qemu-devel@nongnu.org; Thu, 22 Aug 2019 07:37:06 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id 3C0B31A2046; Thu, 22 Aug 2019 13:35:58 +0200 (CEST) Received: from rtrkw774-lin.domain.local (rtrkw774-lin.domain.local [10.10.13.43]) by mail.rt-rk.com (Postfix) with ESMTPSA id 195661A203D; Thu, 22 Aug 2019 13:35:58 +0200 (CEST) X-Virus-Scanned: amavisd-new at rt-rk.com From: Aleksandar Markovic To: qemu-devel@nongnu.org Date: Thu, 22 Aug 2019 13:35:25 +0200 Message-Id: <1566473750-17743-2-git-send-email-aleksandar.markovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1566473750-17743-1-git-send-email-aleksandar.markovic@rt-rk.com> References: <1566473750-17743-1-git-send-email-aleksandar.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 89.216.37.149 Subject: [Qemu-devel] [PATCH 01/26] target/mips: Clean up handling of CP0 register 0 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: aurelien@aurel32.net, amarkovic@wavecomp.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Aleksandar Markovic Clean up handling of CP0 register 0. Signed-off-by: Aleksandar Markovic --- target/mips/cpu.h | 3 +++ target/mips/translate.c | 40 ++++++++++++++++++++-------------------- 2 files changed, 23 insertions(+), 20 deletions(-) diff --git a/target/mips/cpu.h b/target/mips/cpu.h index eda8350..e2f6844 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -279,6 +279,9 @@ typedef struct mips_def_t mips_def_t; =20 /* CP0 Register 00 */ #define CP0_REG00__INDEX 0 +#define CP0_REG00__MVPCONTROL 1 +#define CP0_REG00__MVPCONF0 2 +#define CP0_REG00__MVPCONF1 3 #define CP0_REG00__VPCONTROL 4 /* CP0 Register 01 */ /* CP0 Register 02 */ diff --git a/target/mips/translate.c b/target/mips/translate.c index fe4a05c..06a1646 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -6853,26 +6853,26 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, i= nt reg, int sel) switch (reg) { case CP0_REGISTER_00: switch (sel) { - case 0: + case CP0_REG00__INDEX: gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Index)); register_name =3D "Index"; break; - case 1: + case CP0_REG00__MVPCONTROL: CP0_CHECK(ctx->insn_flags & ASE_MT); gen_helper_mfc0_mvpcontrol(arg, cpu_env); register_name =3D "MVPControl"; break; - case 2: + case CP0_REG00__MVPCONF0: CP0_CHECK(ctx->insn_flags & ASE_MT); gen_helper_mfc0_mvpconf0(arg, cpu_env); register_name =3D "MVPConf0"; break; - case 3: + case CP0_REG00__MVPCONF1: CP0_CHECK(ctx->insn_flags & ASE_MT); gen_helper_mfc0_mvpconf1(arg, cpu_env); register_name =3D "MVPConf1"; break; - case 4: + case CP0_REG00__VPCONTROL: CP0_CHECK(ctx->vp); gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_VPControl)); register_name =3D "VPControl"; @@ -7621,26 +7621,26 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, i= nt reg, int sel) switch (reg) { case CP0_REGISTER_00: switch (sel) { - case 0: + case CP0_REG00__INDEX: gen_helper_mtc0_index(cpu_env, arg); register_name =3D "Index"; break; - case 1: + case CP0_REG00__MVPCONTROL: CP0_CHECK(ctx->insn_flags & ASE_MT); gen_helper_mtc0_mvpcontrol(cpu_env, arg); register_name =3D "MVPControl"; break; - case 2: + case CP0_REG00__MVPCONF0: CP0_CHECK(ctx->insn_flags & ASE_MT); /* ignored */ register_name =3D "MVPConf0"; break; - case 3: + case CP0_REG00__MVPCONF1: CP0_CHECK(ctx->insn_flags & ASE_MT); /* ignored */ register_name =3D "MVPConf1"; break; - case 4: + case CP0_REG00__VPCONTROL: CP0_CHECK(ctx->vp); /* ignored */ register_name =3D "VPControl"; @@ -8373,26 +8373,26 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, = int reg, int sel) switch (reg) { case CP0_REGISTER_00: switch (sel) { - case 0: + case CP0_REG00__INDEX: gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Index)); register_name =3D "Index"; break; - case 1: + case CP0_REG00__MVPCONTROL: CP0_CHECK(ctx->insn_flags & ASE_MT); gen_helper_mfc0_mvpcontrol(arg, cpu_env); register_name =3D "MVPControl"; break; - case 2: + case CP0_REG00__MVPCONF0: CP0_CHECK(ctx->insn_flags & ASE_MT); gen_helper_mfc0_mvpconf0(arg, cpu_env); register_name =3D "MVPConf0"; break; - case 3: + case CP0_REG00__MVPCONF1: CP0_CHECK(ctx->insn_flags & ASE_MT); gen_helper_mfc0_mvpconf1(arg, cpu_env); register_name =3D "MVPConf1"; break; - case 4: + case CP0_REG00__VPCONTROL: CP0_CHECK(ctx->vp); gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_VPControl)); register_name =3D "VPControl"; @@ -9095,26 +9095,26 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, = int reg, int sel) switch (reg) { case CP0_REGISTER_00: switch (sel) { - case 0: + case CP0_REG00__INDEX: gen_helper_mtc0_index(cpu_env, arg); register_name =3D "Index"; break; - case 1: + case CP0_REG00__MVPCONTROL: CP0_CHECK(ctx->insn_flags & ASE_MT); gen_helper_mtc0_mvpcontrol(cpu_env, arg); register_name =3D "MVPControl"; break; - case 2: + case CP0_REG00__MVPCONF0: CP0_CHECK(ctx->insn_flags & ASE_MT); /* ignored */ register_name =3D "MVPConf0"; break; - case 3: + case CP0_REG00__MVPCONF1: CP0_CHECK(ctx->insn_flags & ASE_MT); /* ignored */ register_name =3D "MVPConf1"; break; - case 4: + case CP0_REG00__VPCONTROL: CP0_CHECK(ctx->vp); /* ignored */ register_name =3D "VPControl"; --=20 2.7.4 From nobody Tue May 7 19:36:37 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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Thu, 22 Aug 2019 07:37:05 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id 4DF0C1A2066; Thu, 22 Aug 2019 13:35:58 +0200 (CEST) Received: from rtrkw774-lin.domain.local (rtrkw774-lin.domain.local [10.10.13.43]) by mail.rt-rk.com (Postfix) with ESMTPSA id 237C61A2044; Thu, 22 Aug 2019 13:35:58 +0200 (CEST) X-Virus-Scanned: amavisd-new at rt-rk.com From: Aleksandar Markovic To: qemu-devel@nongnu.org Date: Thu, 22 Aug 2019 13:35:26 +0200 Message-Id: <1566473750-17743-3-git-send-email-aleksandar.markovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1566473750-17743-1-git-send-email-aleksandar.markovic@rt-rk.com> References: <1566473750-17743-1-git-send-email-aleksandar.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 89.216.37.149 Subject: [Qemu-devel] [PATCH 02/26] target/mips: Clean up handling of CP0 register 1 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: aurelien@aurel32.net, amarkovic@wavecomp.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Aleksandar Markovic Clean up handling of CP0 register 1. Signed-off-by: Aleksandar Markovic --- target/mips/cpu.h | 8 +++++++ target/mips/translate.c | 64 ++++++++++++++++++++++++---------------------= ---- 2 files changed, 40 insertions(+), 32 deletions(-) diff --git a/target/mips/cpu.h b/target/mips/cpu.h index e2f6844..597afa8 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -284,6 +284,14 @@ typedef struct mips_def_t mips_def_t; #define CP0_REG00__MVPCONF1 3 #define CP0_REG00__VPCONTROL 4 /* CP0 Register 01 */ +#define CP0_REG01__RANDOM 0 +#define CP0_REG01__VPECONTROL 1 +#define CP0_REG01__VPECONF0 2 +#define CP0_REG01__VPECONF1 3 +#define CP0_REG01__YQMASK 4 +#define CP0_REG01__VPESCHEDULE 5 +#define CP0_REG01__VPESCHEFBACK 6 +#define CP0_REG01__VPEOPT 7 /* CP0 Register 02 */ #define CP0_REG02__ENTRYLO0 0 /* CP0 Register 03 */ diff --git a/target/mips/translate.c b/target/mips/translate.c index 06a1646..e350545 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -6883,42 +6883,42 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, i= nt reg, int sel) break; case CP0_REGISTER_01: switch (sel) { - case 0: + case CP0_REG01__RANDOM: CP0_CHECK(!(ctx->insn_flags & ISA_MIPS32R6)); gen_helper_mfc0_random(arg, cpu_env); register_name =3D "Random"; break; - case 1: + case CP0_REG01__VPECONTROL: CP0_CHECK(ctx->insn_flags & ASE_MT); gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_VPEControl)); register_name =3D "VPEControl"; break; - case 2: + case CP0_REG01__VPECONF0: CP0_CHECK(ctx->insn_flags & ASE_MT); gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_VPEConf0)); register_name =3D "VPEConf0"; break; - case 3: + case CP0_REG01__VPECONF1: CP0_CHECK(ctx->insn_flags & ASE_MT); gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_VPEConf1)); register_name =3D "VPEConf1"; break; - case 4: + case CP0_REG01__YQMASK: CP0_CHECK(ctx->insn_flags & ASE_MT); gen_mfc0_load64(arg, offsetof(CPUMIPSState, CP0_YQMask)); register_name =3D "YQMask"; break; - case 5: + case CP0_REG01__VPESCHEDULE: CP0_CHECK(ctx->insn_flags & ASE_MT); gen_mfc0_load64(arg, offsetof(CPUMIPSState, CP0_VPESchedule)); register_name =3D "VPESchedule"; break; - case 6: + case CP0_REG01__VPESCHEFBACK: CP0_CHECK(ctx->insn_flags & ASE_MT); gen_mfc0_load64(arg, offsetof(CPUMIPSState, CP0_VPEScheFBack)); register_name =3D "VPEScheFBack"; break; - case 7: + case CP0_REG01__VPEOPT: CP0_CHECK(ctx->insn_flags & ASE_MT); gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_VPEOpt)); register_name =3D "VPEOpt"; @@ -7651,43 +7651,43 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, i= nt reg, int sel) break; case CP0_REGISTER_01: switch (sel) { - case 0: + case CP0_REG01__RANDOM: /* ignored */ register_name =3D "Random"; break; - case 1: + case CP0_REG01__VPECONTROL: CP0_CHECK(ctx->insn_flags & ASE_MT); gen_helper_mtc0_vpecontrol(cpu_env, arg); register_name =3D "VPEControl"; break; - case 2: + case CP0_REG01__VPECONF0: CP0_CHECK(ctx->insn_flags & ASE_MT); gen_helper_mtc0_vpeconf0(cpu_env, arg); register_name =3D "VPEConf0"; break; - case 3: + case CP0_REG01__VPECONF1: CP0_CHECK(ctx->insn_flags & ASE_MT); gen_helper_mtc0_vpeconf1(cpu_env, arg); register_name =3D "VPEConf1"; break; - case 4: + case CP0_REG01__YQMASK: CP0_CHECK(ctx->insn_flags & ASE_MT); gen_helper_mtc0_yqmask(cpu_env, arg); register_name =3D "YQMask"; break; - case 5: + case CP0_REG01__VPESCHEDULE: CP0_CHECK(ctx->insn_flags & ASE_MT); tcg_gen_st_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_VPESchedule)); register_name =3D "VPESchedule"; break; - case 6: + case CP0_REG01__VPESCHEFBACK: CP0_CHECK(ctx->insn_flags & ASE_MT); tcg_gen_st_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_VPEScheFBack)); register_name =3D "VPEScheFBack"; break; - case 7: + case CP0_REG01__VPEOPT: CP0_CHECK(ctx->insn_flags & ASE_MT); gen_helper_mtc0_vpeopt(cpu_env, arg); register_name =3D "VPEOpt"; @@ -8403,42 +8403,42 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, = int reg, int sel) break; case CP0_REGISTER_01: switch (sel) { - case 0: + case CP0_REG01__RANDOM: CP0_CHECK(!(ctx->insn_flags & ISA_MIPS32R6)); gen_helper_mfc0_random(arg, cpu_env); register_name =3D "Random"; break; - case 1: + case CP0_REG01__VPECONTROL: CP0_CHECK(ctx->insn_flags & ASE_MT); gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_VPEControl)); register_name =3D "VPEControl"; break; - case 2: + case CP0_REG01__VPECONF0: CP0_CHECK(ctx->insn_flags & ASE_MT); gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_VPEConf0)); register_name =3D "VPEConf0"; break; - case 3: + case CP0_REG01__VPECONF1: CP0_CHECK(ctx->insn_flags & ASE_MT); gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_VPEConf1)); register_name =3D "VPEConf1"; break; - case 4: + case CP0_REG01__YQMASK: CP0_CHECK(ctx->insn_flags & ASE_MT); tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_YQMask)= ); register_name =3D "YQMask"; break; - case 5: + case CP0_REG01__VPESCHEDULE: CP0_CHECK(ctx->insn_flags & ASE_MT); tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_VPESche= dule)); register_name =3D "VPESchedule"; break; - case 6: + case CP0_REG01__VPESCHEFBACK: CP0_CHECK(ctx->insn_flags & ASE_MT); tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_VPESche= FBack)); register_name =3D "VPEScheFBack"; break; - case 7: + case CP0_REG01__VPEOPT: CP0_CHECK(ctx->insn_flags & ASE_MT); gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_VPEOpt)); register_name =3D "VPEOpt"; @@ -9125,41 +9125,41 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, = int reg, int sel) break; case CP0_REGISTER_01: switch (sel) { - case 0: + case CP0_REG01__RANDOM: /* ignored */ register_name =3D "Random"; break; - case 1: + case CP0_REG01__VPECONTROL: CP0_CHECK(ctx->insn_flags & ASE_MT); gen_helper_mtc0_vpecontrol(cpu_env, arg); register_name =3D "VPEControl"; break; - case 2: + case CP0_REG01__VPECONF0: CP0_CHECK(ctx->insn_flags & ASE_MT); gen_helper_mtc0_vpeconf0(cpu_env, arg); register_name =3D "VPEConf0"; break; - case 3: + case CP0_REG01__VPECONF1: CP0_CHECK(ctx->insn_flags & ASE_MT); gen_helper_mtc0_vpeconf1(cpu_env, arg); register_name =3D "VPEConf1"; break; - case 4: + case CP0_REG01__YQMASK: CP0_CHECK(ctx->insn_flags & ASE_MT); gen_helper_mtc0_yqmask(cpu_env, arg); register_name =3D "YQMask"; break; - case 5: + case CP0_REG01__VPESCHEDULE: CP0_CHECK(ctx->insn_flags & ASE_MT); tcg_gen_st_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_VPESche= dule)); register_name =3D "VPESchedule"; break; - case 6: + case CP0_REG01__VPESCHEFBACK: CP0_CHECK(ctx->insn_flags & ASE_MT); tcg_gen_st_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_VPESche= FBack)); register_name =3D "VPEScheFBack"; break; - case 7: + case CP0_REG01__VPEOPT: CP0_CHECK(ctx->insn_flags & ASE_MT); gen_helper_mtc0_vpeopt(cpu_env, arg); register_name =3D "VPEOpt"; --=20 2.7.4 From nobody Tue May 7 19:36:37 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1566474537; cv=none; d=zoho.com; s=zohoarc; b=V34NdsDqXDXEj1ls86rvIaQ5TuU11HYFiISJW779jpzD3fBQJQdj3btzT8lCZDlMebqLFne1pD5Q5osPllFkN+mUVTqE3xBXpfGsCjGAu+Tko9uFhlSWWReyxQHLQZmko1Jm12t2oUk7Wr3e6VVMD9sty7FRS8GWoKcmLhLuDYc= ARC-Message-Signature: i=1; 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Thu, 22 Aug 2019 07:37:29 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1i0lOr-0007hU-KZ for qemu-devel@nongnu.org; Thu, 22 Aug 2019 07:37:16 -0400 Received: from mx2.rt-rk.com ([89.216.37.149]:36801 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1i0lOq-0006xW-Vo for qemu-devel@nongnu.org; Thu, 22 Aug 2019 07:37:05 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id 644381A2059; Thu, 22 Aug 2019 13:35:58 +0200 (CEST) Received: from rtrkw774-lin.domain.local (rtrkw774-lin.domain.local [10.10.13.43]) by mail.rt-rk.com (Postfix) with ESMTPSA id 2F8D41A204B; Thu, 22 Aug 2019 13:35:58 +0200 (CEST) X-Virus-Scanned: amavisd-new at rt-rk.com From: Aleksandar Markovic To: qemu-devel@nongnu.org Date: Thu, 22 Aug 2019 13:35:27 +0200 Message-Id: <1566473750-17743-4-git-send-email-aleksandar.markovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1566473750-17743-1-git-send-email-aleksandar.markovic@rt-rk.com> References: <1566473750-17743-1-git-send-email-aleksandar.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 89.216.37.149 Subject: [Qemu-devel] [PATCH 03/26] target/mips: Clean up handling of CP0 register 2 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: aurelien@aurel32.net, amarkovic@wavecomp.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Aleksandar Markovic Clean up handling of CP0 register 2. Signed-off-by: Aleksandar Markovic --- target/mips/cpu.h | 7 ++++++ target/mips/translate.c | 64 ++++++++++++++++++++++++---------------------= ---- 2 files changed, 39 insertions(+), 32 deletions(-) diff --git a/target/mips/cpu.h b/target/mips/cpu.h index 597afa8..eebdc9f 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -294,6 +294,13 @@ typedef struct mips_def_t mips_def_t; #define CP0_REG01__VPEOPT 7 /* CP0 Register 02 */ #define CP0_REG02__ENTRYLO0 0 +#define CP0_REG02__TCSTATUS 1 +#define CP0_REG02__TCBIND 2 +#define CP0_REG02__TCRESTART 3 +#define CP0_REG02__TCHALT 4 +#define CP0_REG02__TCCONTEXT 5 +#define CP0_REG02__TCSCHEDULE 6 +#define CP0_REG02__TCSCHEFBACK 7 /* CP0 Register 03 */ #define CP0_REG03__ENTRYLO1 0 #define CP0_REG03__GLOBALNUM 1 diff --git a/target/mips/translate.c b/target/mips/translate.c index e350545..6e65312 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -6929,7 +6929,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int= reg, int sel) break; case CP0_REGISTER_02: switch (sel) { - case 0: + case CP0_REG02__ENTRYLO0: { TCGv_i64 tmp =3D tcg_temp_new_i64(); tcg_gen_ld_i64(tmp, cpu_env, @@ -6946,37 +6946,37 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, i= nt reg, int sel) } register_name =3D "EntryLo0"; break; - case 1: + case CP0_REG02__TCSTATUS: CP0_CHECK(ctx->insn_flags & ASE_MT); gen_helper_mfc0_tcstatus(arg, cpu_env); register_name =3D "TCStatus"; break; - case 2: + case CP0_REG02__TCBIND: CP0_CHECK(ctx->insn_flags & ASE_MT); gen_helper_mfc0_tcbind(arg, cpu_env); register_name =3D "TCBind"; break; - case 3: + case CP0_REG02__TCRESTART: CP0_CHECK(ctx->insn_flags & ASE_MT); gen_helper_mfc0_tcrestart(arg, cpu_env); register_name =3D "TCRestart"; break; - case 4: + case CP0_REG02__TCHALT: CP0_CHECK(ctx->insn_flags & ASE_MT); gen_helper_mfc0_tchalt(arg, cpu_env); register_name =3D "TCHalt"; break; - case 5: + case CP0_REG02__TCCONTEXT: CP0_CHECK(ctx->insn_flags & ASE_MT); gen_helper_mfc0_tccontext(arg, cpu_env); register_name =3D "TCContext"; break; - case 6: + case CP0_REG02__TCSCHEDULE: CP0_CHECK(ctx->insn_flags & ASE_MT); gen_helper_mfc0_tcschedule(arg, cpu_env); register_name =3D "TCSchedule"; break; - case 7: + case CP0_REG02__TCSCHEFBACK: CP0_CHECK(ctx->insn_flags & ASE_MT); gen_helper_mfc0_tcschefback(arg, cpu_env); register_name =3D "TCScheFBack"; @@ -7698,41 +7698,41 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, i= nt reg, int sel) break; case CP0_REGISTER_02: switch (sel) { - case 0: + case CP0_REG02__ENTRYLO0: gen_helper_mtc0_entrylo0(cpu_env, arg); register_name =3D "EntryLo0"; break; - case 1: + case CP0_REG02__TCSTATUS: CP0_CHECK(ctx->insn_flags & ASE_MT); gen_helper_mtc0_tcstatus(cpu_env, arg); register_name =3D "TCStatus"; break; - case 2: + case CP0_REG02__TCBIND: CP0_CHECK(ctx->insn_flags & ASE_MT); gen_helper_mtc0_tcbind(cpu_env, arg); register_name =3D "TCBind"; break; - case 3: + case CP0_REG02__TCRESTART: CP0_CHECK(ctx->insn_flags & ASE_MT); gen_helper_mtc0_tcrestart(cpu_env, arg); register_name =3D "TCRestart"; break; - case 4: + case CP0_REG02__TCHALT: CP0_CHECK(ctx->insn_flags & ASE_MT); gen_helper_mtc0_tchalt(cpu_env, arg); register_name =3D "TCHalt"; break; - case 5: + case CP0_REG02__TCCONTEXT: CP0_CHECK(ctx->insn_flags & ASE_MT); gen_helper_mtc0_tccontext(cpu_env, arg); register_name =3D "TCContext"; break; - case 6: + case CP0_REG02__TCSCHEDULE: CP0_CHECK(ctx->insn_flags & ASE_MT); gen_helper_mtc0_tcschedule(cpu_env, arg); register_name =3D "TCSchedule"; break; - case 7: + case CP0_REG02__TCSCHEFBACK: CP0_CHECK(ctx->insn_flags & ASE_MT); gen_helper_mtc0_tcschefback(cpu_env, arg); register_name =3D "TCScheFBack"; @@ -8449,41 +8449,41 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, = int reg, int sel) break; case CP0_REGISTER_02: switch (sel) { - case 0: + case CP0_REG02__ENTRYLO0: tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_EntryLo= 0)); register_name =3D "EntryLo0"; break; - case 1: + case CP0_REG02__TCSTATUS: CP0_CHECK(ctx->insn_flags & ASE_MT); gen_helper_mfc0_tcstatus(arg, cpu_env); register_name =3D "TCStatus"; break; - case 2: + case CP0_REG02__TCBIND: CP0_CHECK(ctx->insn_flags & ASE_MT); gen_helper_mfc0_tcbind(arg, cpu_env); register_name =3D "TCBind"; break; - case 3: + case CP0_REG02__TCRESTART: CP0_CHECK(ctx->insn_flags & ASE_MT); gen_helper_dmfc0_tcrestart(arg, cpu_env); register_name =3D "TCRestart"; break; - case 4: + case CP0_REG02__TCHALT: CP0_CHECK(ctx->insn_flags & ASE_MT); gen_helper_dmfc0_tchalt(arg, cpu_env); register_name =3D "TCHalt"; break; - case 5: + case CP0_REG02__TCCONTEXT: CP0_CHECK(ctx->insn_flags & ASE_MT); gen_helper_dmfc0_tccontext(arg, cpu_env); register_name =3D "TCContext"; break; - case 6: + case CP0_REG02__TCSCHEDULE: CP0_CHECK(ctx->insn_flags & ASE_MT); gen_helper_dmfc0_tcschedule(arg, cpu_env); register_name =3D "TCSchedule"; break; - case 7: + case CP0_REG02__TCSCHEFBACK: CP0_CHECK(ctx->insn_flags & ASE_MT); gen_helper_dmfc0_tcschefback(arg, cpu_env); register_name =3D "TCScheFBack"; @@ -9170,41 +9170,41 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, = int reg, int sel) break; case CP0_REGISTER_02: switch (sel) { - case 0: + case CP0_REG02__ENTRYLO0: gen_helper_dmtc0_entrylo0(cpu_env, arg); register_name =3D "EntryLo0"; break; - case 1: + case CP0_REG02__TCSTATUS: CP0_CHECK(ctx->insn_flags & ASE_MT); gen_helper_mtc0_tcstatus(cpu_env, arg); register_name =3D "TCStatus"; break; - case 2: + case CP0_REG02__TCBIND: CP0_CHECK(ctx->insn_flags & ASE_MT); gen_helper_mtc0_tcbind(cpu_env, arg); register_name =3D "TCBind"; break; - case 3: + case CP0_REG02__TCRESTART: CP0_CHECK(ctx->insn_flags & ASE_MT); gen_helper_mtc0_tcrestart(cpu_env, arg); register_name =3D "TCRestart"; break; - case 4: + case CP0_REG02__TCHALT: CP0_CHECK(ctx->insn_flags & ASE_MT); gen_helper_mtc0_tchalt(cpu_env, arg); register_name =3D "TCHalt"; break; - case 5: + case CP0_REG02__TCCONTEXT: CP0_CHECK(ctx->insn_flags & ASE_MT); gen_helper_mtc0_tccontext(cpu_env, arg); register_name =3D "TCContext"; break; - case 6: + case CP0_REG02__TCSCHEDULE: CP0_CHECK(ctx->insn_flags & ASE_MT); gen_helper_mtc0_tcschedule(cpu_env, arg); register_name =3D "TCSchedule"; break; - case 7: + case CP0_REG02__TCSCHEFBACK: CP0_CHECK(ctx->insn_flags & ASE_MT); gen_helper_mtc0_tcschefback(cpu_env, arg); register_name =3D "TCScheFBack"; --=20 2.7.4 From nobody Tue May 7 19:36:37 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1566474446; cv=none; d=zoho.com; s=zohoarc; b=PPD2Zs1hsuegUXLgVS4nlJsmpG5f7yz9ERrweJUxRTQ8gKPm1c3KYC36npB0+Izk/kyQbx8KZm1fI0I27zC9qC71iUIzyelE0/LD1/VUwYZqSxp+l2tcpbiuBNTi5WYLgCETewW1Zg7ZJoHzXdAgqRwF1KlTiSsomONiLpA5ezg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; 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Thu, 22 Aug 2019 07:37:26 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1i0lOs-0007id-R9 for qemu-devel@nongnu.org; Thu, 22 Aug 2019 07:37:13 -0400 Received: from mx2.rt-rk.com ([89.216.37.149]:36843 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1i0lOs-0006xi-27 for qemu-devel@nongnu.org; Thu, 22 Aug 2019 07:37:06 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id 689E71A2095; Thu, 22 Aug 2019 13:35:58 +0200 (CEST) Received: from rtrkw774-lin.domain.local (rtrkw774-lin.domain.local [10.10.13.43]) by mail.rt-rk.com (Postfix) with ESMTPSA id 37D1F1A1513; Thu, 22 Aug 2019 13:35:58 +0200 (CEST) X-Virus-Scanned: amavisd-new at rt-rk.com From: Aleksandar Markovic To: qemu-devel@nongnu.org Date: Thu, 22 Aug 2019 13:35:28 +0200 Message-Id: <1566473750-17743-5-git-send-email-aleksandar.markovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1566473750-17743-1-git-send-email-aleksandar.markovic@rt-rk.com> References: <1566473750-17743-1-git-send-email-aleksandar.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 89.216.37.149 Subject: [Qemu-devel] [PATCH 04/26] target/mips: Clean up handling of CP0 register 5 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: aurelien@aurel32.net, amarkovic@wavecomp.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Aleksandar Markovic Clean up handling of CP0 register 5. Signed-off-by: Aleksandar Markovic --- target/mips/cpu.h | 6 +++++ target/mips/translate.c | 64 ++++++++++++++++++++++++---------------------= ---- 2 files changed, 38 insertions(+), 32 deletions(-) diff --git a/target/mips/cpu.h b/target/mips/cpu.h index eebdc9f..2ab388b 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -312,6 +312,12 @@ typedef struct mips_def_t mips_def_t; /* CP0 Register 05 */ #define CP0_REG05__PAGEMASK 0 #define CP0_REG05__PAGEGRAIN 1 +#define CP0_REG05__SEGCTL0 2 +#define CP0_REG05__SEGCTL1 3 +#define CP0_REG05__SEGCTL2 4 +#define CP0_REG05__PWBASE 5 +#define CP0_REG05__PWFIELD 6 +#define CP0_REG05__PWSIZE 7 /* CP0 Register 06 */ #define CP0_REG06__WIRED 0 /* CP0 Register 07 */ diff --git a/target/mips/translate.c b/target/mips/translate.c index 6e65312..9d1e315 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -7042,44 +7042,44 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, i= nt reg, int sel) break; case CP0_REGISTER_05: switch (sel) { - case 0: + case CP0_REG05__PAGEMASK: gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PageMask)); register_name =3D "PageMask"; break; - case 1: + case CP0_REG05__PAGEGRAIN: check_insn(ctx, ISA_MIPS32R2); gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PageGrain)); register_name =3D "PageGrain"; break; - case 2: + case CP0_REG05__SEGCTL0: CP0_CHECK(ctx->sc); tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_SegCtl0= )); tcg_gen_ext32s_tl(arg, arg); register_name =3D "SegCtl0"; break; - case 3: + case CP0_REG05__SEGCTL1: CP0_CHECK(ctx->sc); tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_SegCtl1= )); tcg_gen_ext32s_tl(arg, arg); register_name =3D "SegCtl1"; break; - case 4: + case CP0_REG05__SEGCTL2: CP0_CHECK(ctx->sc); tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_SegCtl2= )); tcg_gen_ext32s_tl(arg, arg); register_name =3D "SegCtl2"; break; - case 5: + case CP0_REG05__PWBASE: check_pw(ctx); gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PWBase)); register_name =3D "PWBase"; break; - case 6: + case CP0_REG05__PWFIELD: check_pw(ctx); gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PWField)); register_name =3D "PWField"; break; - case 7: + case CP0_REG05__PWSIZE: check_pw(ctx); gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PWSize)); register_name =3D "PWSize"; @@ -7783,42 +7783,42 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, i= nt reg, int sel) break; case CP0_REGISTER_05: switch (sel) { - case 0: + case CP0_REG05__PAGEMASK: gen_helper_mtc0_pagemask(cpu_env, arg); register_name =3D "PageMask"; break; - case 1: + case CP0_REG05__PAGEGRAIN: check_insn(ctx, ISA_MIPS32R2); gen_helper_mtc0_pagegrain(cpu_env, arg); register_name =3D "PageGrain"; ctx->base.is_jmp =3D DISAS_STOP; break; - case 2: + case CP0_REG05__SEGCTL0: CP0_CHECK(ctx->sc); gen_helper_mtc0_segctl0(cpu_env, arg); register_name =3D "SegCtl0"; break; - case 3: + case CP0_REG05__SEGCTL1: CP0_CHECK(ctx->sc); gen_helper_mtc0_segctl1(cpu_env, arg); register_name =3D "SegCtl1"; break; - case 4: + case CP0_REG05__SEGCTL2: CP0_CHECK(ctx->sc); gen_helper_mtc0_segctl2(cpu_env, arg); register_name =3D "SegCtl2"; break; - case 5: + case CP0_REG05__PWBASE: check_pw(ctx); gen_mtc0_store32(arg, offsetof(CPUMIPSState, CP0_PWBase)); register_name =3D "PWBase"; break; - case 6: + case CP0_REG05__PWFIELD: check_pw(ctx); gen_helper_mtc0_pwfield(cpu_env, arg); register_name =3D "PWField"; break; - case 7: + case CP0_REG05__PWSIZE: check_pw(ctx); gen_helper_mtc0_pwsize(cpu_env, arg); register_name =3D "PWSize"; @@ -8534,41 +8534,41 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, = int reg, int sel) break; case CP0_REGISTER_05: switch (sel) { - case 0: + case CP0_REG05__PAGEMASK: gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PageMask)); register_name =3D "PageMask"; break; - case 1: + case CP0_REG05__PAGEGRAIN: check_insn(ctx, ISA_MIPS32R2); gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PageGrain)); register_name =3D "PageGrain"; break; - case 2: + case CP0_REG05__SEGCTL0: CP0_CHECK(ctx->sc); tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_SegCtl0= )); register_name =3D "SegCtl0"; break; - case 3: + case CP0_REG05__SEGCTL1: CP0_CHECK(ctx->sc); tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_SegCtl1= )); register_name =3D "SegCtl1"; break; - case 4: + case CP0_REG05__SEGCTL2: CP0_CHECK(ctx->sc); tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_SegCtl2= )); register_name =3D "SegCtl2"; break; - case 5: + case CP0_REG05__PWBASE: check_pw(ctx); tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_PWBase)= ); register_name =3D "PWBase"; break; - case 6: + case CP0_REG05__PWFIELD: check_pw(ctx); tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_PWField= )); register_name =3D "PWField"; break; - case 7: + case CP0_REG05__PWSIZE: check_pw(ctx); tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_PWSize)= ); register_name =3D "PWSize"; @@ -9255,41 +9255,41 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, = int reg, int sel) break; case CP0_REGISTER_05: switch (sel) { - case 0: + case CP0_REG05__PAGEMASK: gen_helper_mtc0_pagemask(cpu_env, arg); register_name =3D "PageMask"; break; - case 1: + case CP0_REG05__PAGEGRAIN: check_insn(ctx, ISA_MIPS32R2); gen_helper_mtc0_pagegrain(cpu_env, arg); register_name =3D "PageGrain"; break; - case 2: + case CP0_REG05__SEGCTL0: CP0_CHECK(ctx->sc); gen_helper_mtc0_segctl0(cpu_env, arg); register_name =3D "SegCtl0"; break; - case 3: + case CP0_REG05__SEGCTL1: CP0_CHECK(ctx->sc); gen_helper_mtc0_segctl1(cpu_env, arg); register_name =3D "SegCtl1"; break; - case 4: + case CP0_REG05__SEGCTL2: CP0_CHECK(ctx->sc); gen_helper_mtc0_segctl2(cpu_env, arg); register_name =3D "SegCtl2"; break; - case 5: + case CP0_REG05__PWBASE: check_pw(ctx); tcg_gen_st_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_PWBase)= ); register_name =3D "PWBase"; break; - case 6: + case CP0_REG05__PWFIELD: check_pw(ctx); gen_helper_mtc0_pwfield(cpu_env, arg); register_name =3D "PWField"; break; - case 7: + case CP0_REG05__PWSIZE: check_pw(ctx); gen_helper_mtc0_pwsize(cpu_env, arg); register_name =3D "PWSize"; --=20 2.7.4 From nobody Tue May 7 19:36:37 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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Thu, 22 Aug 2019 07:37:22 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id 7A9221A2070; Thu, 22 Aug 2019 13:35:58 +0200 (CEST) Received: from rtrkw774-lin.domain.local (rtrkw774-lin.domain.local [10.10.13.43]) by mail.rt-rk.com (Postfix) with ESMTPSA id 42F5B1A2053; Thu, 22 Aug 2019 13:35:58 +0200 (CEST) X-Virus-Scanned: amavisd-new at rt-rk.com From: Aleksandar Markovic To: qemu-devel@nongnu.org Date: Thu, 22 Aug 2019 13:35:29 +0200 Message-Id: <1566473750-17743-6-git-send-email-aleksandar.markovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1566473750-17743-1-git-send-email-aleksandar.markovic@rt-rk.com> References: <1566473750-17743-1-git-send-email-aleksandar.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 89.216.37.149 Subject: [Qemu-devel] [PATCH 05/26] target/mips: Clean up handling of CP0 register 6 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: aurelien@aurel32.net, amarkovic@wavecomp.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Aleksandar Markovic Clean up handling of CP0 register 6. Signed-off-by: Aleksandar Markovic --- target/mips/cpu.h | 6 ++++++ target/mips/translate.c | 56 ++++++++++++++++++++++++---------------------= ---- 2 files changed, 34 insertions(+), 28 deletions(-) diff --git a/target/mips/cpu.h b/target/mips/cpu.h index 2ab388b..c865b51 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -320,6 +320,12 @@ typedef struct mips_def_t mips_def_t; #define CP0_REG05__PWSIZE 7 /* CP0 Register 06 */ #define CP0_REG06__WIRED 0 +#define CP0_REG06__SRSCONF0 1 +#define CP0_REG06__SRSCONF1 2 +#define CP0_REG06__SRSCONF2 3 +#define CP0_REG06__SRSCONF3 4 +#define CP0_REG06__SRSCONF4 5 +#define CP0_REG06__PWCTL 6 /* CP0 Register 07 */ #define CP0_REG07__HWRENA 0 /* CP0 Register 08 */ diff --git a/target/mips/translate.c b/target/mips/translate.c index 9d1e315..cdcc1cc 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -7090,36 +7090,36 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, i= nt reg, int sel) break; case CP0_REGISTER_06: switch (sel) { - case 0: + case CP0_REG06__WIRED: gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Wired)); register_name =3D "Wired"; break; - case 1: + case CP0_REG06__SRSCONF0: check_insn(ctx, ISA_MIPS32R2); gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf0)); register_name =3D "SRSConf0"; break; - case 2: + case CP0_REG06__SRSCONF1: check_insn(ctx, ISA_MIPS32R2); gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf1)); register_name =3D "SRSConf1"; break; - case 3: + case CP0_REG06__SRSCONF2: check_insn(ctx, ISA_MIPS32R2); gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf2)); register_name =3D "SRSConf2"; break; - case 4: + case CP0_REG06__SRSCONF3: check_insn(ctx, ISA_MIPS32R2); gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf3)); register_name =3D "SRSConf3"; break; - case 5: + case CP0_REG06__SRSCONF4: check_insn(ctx, ISA_MIPS32R2); gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf4)); register_name =3D "SRSConf4"; break; - case 6: + case CP0_REG06__PWCTL: check_pw(ctx); gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PWCtl)); register_name =3D "PWCtl"; @@ -7829,36 +7829,36 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, i= nt reg, int sel) break; case CP0_REGISTER_06: switch (sel) { - case 0: + case CP0_REG06__WIRED: gen_helper_mtc0_wired(cpu_env, arg); register_name =3D "Wired"; break; - case 1: + case CP0_REG06__SRSCONF0: check_insn(ctx, ISA_MIPS32R2); gen_helper_mtc0_srsconf0(cpu_env, arg); register_name =3D "SRSConf0"; break; - case 2: + case CP0_REG06__SRSCONF1: check_insn(ctx, ISA_MIPS32R2); gen_helper_mtc0_srsconf1(cpu_env, arg); register_name =3D "SRSConf1"; break; - case 3: + case CP0_REG06__SRSCONF2: check_insn(ctx, ISA_MIPS32R2); gen_helper_mtc0_srsconf2(cpu_env, arg); register_name =3D "SRSConf2"; break; - case 4: + case CP0_REG06__SRSCONF3: check_insn(ctx, ISA_MIPS32R2); gen_helper_mtc0_srsconf3(cpu_env, arg); register_name =3D "SRSConf3"; break; - case 5: + case CP0_REG06__SRSCONF4: check_insn(ctx, ISA_MIPS32R2); gen_helper_mtc0_srsconf4(cpu_env, arg); register_name =3D "SRSConf4"; break; - case 6: + case CP0_REG06__PWCTL: check_pw(ctx); gen_helper_mtc0_pwctl(cpu_env, arg); register_name =3D "PWCtl"; @@ -8579,36 +8579,36 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, = int reg, int sel) break; case CP0_REGISTER_06: switch (sel) { - case 0: + case CP0_REG06__WIRED: gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Wired)); register_name =3D "Wired"; break; - case 1: + case CP0_REG06__SRSCONF0: check_insn(ctx, ISA_MIPS32R2); gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf0)); register_name =3D "SRSConf0"; break; - case 2: + case CP0_REG06__SRSCONF1: check_insn(ctx, ISA_MIPS32R2); gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf1)); register_name =3D "SRSConf1"; break; - case 3: + case CP0_REG06__SRSCONF2: check_insn(ctx, ISA_MIPS32R2); gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf2)); register_name =3D "SRSConf2"; break; - case 4: + case CP0_REG06__SRSCONF3: check_insn(ctx, ISA_MIPS32R2); gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf3)); register_name =3D "SRSConf3"; break; - case 5: + case CP0_REG06__SRSCONF4: check_insn(ctx, ISA_MIPS32R2); gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf4)); register_name =3D "SRSConf4"; break; - case 6: + case CP0_REG06__PWCTL: check_pw(ctx); gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PWCtl)); register_name =3D "PWCtl"; @@ -9300,36 +9300,36 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, = int reg, int sel) break; case CP0_REGISTER_06: switch (sel) { - case 0: + case CP0_REG06__WIRED: gen_helper_mtc0_wired(cpu_env, arg); register_name =3D "Wired"; break; - case 1: + case CP0_REG06__SRSCONF0: check_insn(ctx, ISA_MIPS32R2); gen_helper_mtc0_srsconf0(cpu_env, arg); register_name =3D "SRSConf0"; break; - case 2: + case CP0_REG06__SRSCONF1: check_insn(ctx, ISA_MIPS32R2); gen_helper_mtc0_srsconf1(cpu_env, arg); register_name =3D "SRSConf1"; break; - case 3: + case CP0_REG06__SRSCONF2: check_insn(ctx, ISA_MIPS32R2); gen_helper_mtc0_srsconf2(cpu_env, arg); register_name =3D "SRSConf2"; break; - case 4: + case CP0_REG06__SRSCONF3: check_insn(ctx, ISA_MIPS32R2); gen_helper_mtc0_srsconf3(cpu_env, arg); register_name =3D "SRSConf3"; break; - case 5: + case CP0_REG06__SRSCONF4: check_insn(ctx, ISA_MIPS32R2); gen_helper_mtc0_srsconf4(cpu_env, arg); register_name =3D "SRSConf4"; break; - case 6: + case CP0_REG06__PWCTL: check_pw(ctx); gen_helper_mtc0_pwctl(cpu_env, arg); register_name =3D "PWCtl"; --=20 2.7.4 From nobody Tue May 7 19:36:37 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1566474419; cv=none; d=zoho.com; s=zohoarc; b=AC2AW6qSw/afNmnwAUzTbTAkHNnECYcYaP22uZCKjkdb8r8xRCjoNDpLT6FV96nNzTf6kUJ4skEf/b1ZttbEqUqojTOdcyHY6CghVRqQ7Fhx3nbMxZti0FQkSIjS1z20zehhgt+hkWD3UsPw0cze8pICv0s/UzF8NTIviBUUWpg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1566474419; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; 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Thu, 22 Aug 2019 07:37:21 -0400 Received: from mx2.rt-rk.com ([89.216.37.149]:48183 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1i0lOw-0007hq-Dt for qemu-devel@nongnu.org; Thu, 22 Aug 2019 07:37:12 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id 76F391A1513; Thu, 22 Aug 2019 13:35:58 +0200 (CEST) Received: from rtrkw774-lin.domain.local (rtrkw774-lin.domain.local [10.10.13.43]) by mail.rt-rk.com (Postfix) with ESMTPSA id 4B8721A203D; Thu, 22 Aug 2019 13:35:58 +0200 (CEST) X-Virus-Scanned: amavisd-new at rt-rk.com From: Aleksandar Markovic To: qemu-devel@nongnu.org Date: Thu, 22 Aug 2019 13:35:30 +0200 Message-Id: <1566473750-17743-7-git-send-email-aleksandar.markovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1566473750-17743-1-git-send-email-aleksandar.markovic@rt-rk.com> References: <1566473750-17743-1-git-send-email-aleksandar.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 89.216.37.149 Subject: [Qemu-devel] [PATCH 06/26] target/mips: Clean up handling of CP0 register 7 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: aurelien@aurel32.net, amarkovic@wavecomp.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Aleksandar Markovic Clean up handling of CP0 register 7. Signed-off-by: Aleksandar Markovic --- target/mips/translate.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/target/mips/translate.c b/target/mips/translate.c index cdcc1cc..abbb924 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -7130,7 +7130,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int= reg, int sel) break; case CP0_REGISTER_07: switch (sel) { - case 0: + case CP0_REG07__HWRENA: check_insn(ctx, ISA_MIPS32R2); gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_HWREna)); register_name =3D "HWREna"; @@ -7869,7 +7869,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int= reg, int sel) break; case CP0_REGISTER_07: switch (sel) { - case 0: + case CP0_REG07__HWRENA: check_insn(ctx, ISA_MIPS32R2); gen_helper_mtc0_hwrena(cpu_env, arg); ctx->base.is_jmp =3D DISAS_STOP; @@ -8619,7 +8619,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, in= t reg, int sel) break; case CP0_REGISTER_07: switch (sel) { - case 0: + case CP0_REG07__HWRENA: check_insn(ctx, ISA_MIPS32R2); gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_HWREna)); register_name =3D "HWREna"; @@ -9340,7 +9340,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, in= t reg, int sel) break; case CP0_REGISTER_07: switch (sel) { - case 0: + case CP0_REG07__HWRENA: check_insn(ctx, ISA_MIPS32R2); gen_helper_mtc0_hwrena(cpu_env, arg); ctx->base.is_jmp =3D DISAS_STOP; --=20 2.7.4 From nobody Tue May 7 19:36:37 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1566474207; cv=none; d=zoho.com; s=zohoarc; b=gjW+uajworlUOirynx09h3bbjnsmOs65BUzy+qc63beCjtqXvMEWdlsdwZWoCZ5+8H4hMuB50eyzV9vsh7gC3Iu9sHENKhcfKbsTSnSQdC7zmydu4dHBPqrpMTmzfAhbTaM+ca2LvCJXo2udJ7c2CDTIOA+OSh8x7gISWgBPAis= ARC-Message-Signature: i=1; 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Thu, 22 Aug 2019 07:43:26 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:59858) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i0lP7-0004io-EJ for qemu-devel@nongnu.org; Thu, 22 Aug 2019 07:37:24 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1i0lOv-0007lL-Cq for qemu-devel@nongnu.org; Thu, 22 Aug 2019 07:37:15 -0400 Received: from mx2.rt-rk.com ([89.216.37.149]:48184 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1i0lOt-0007hs-OO for qemu-devel@nongnu.org; Thu, 22 Aug 2019 07:37:08 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id 837F01A203D; Thu, 22 Aug 2019 13:35:58 +0200 (CEST) Received: from rtrkw774-lin.domain.local (rtrkw774-lin.domain.local [10.10.13.43]) by mail.rt-rk.com (Postfix) with ESMTPSA id 528E91A2068; Thu, 22 Aug 2019 13:35:58 +0200 (CEST) X-Virus-Scanned: amavisd-new at rt-rk.com From: Aleksandar Markovic To: qemu-devel@nongnu.org Date: Thu, 22 Aug 2019 13:35:31 +0200 Message-Id: <1566473750-17743-8-git-send-email-aleksandar.markovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1566473750-17743-1-git-send-email-aleksandar.markovic@rt-rk.com> References: <1566473750-17743-1-git-send-email-aleksandar.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 89.216.37.149 Subject: [Qemu-devel] [PATCH 07/26] target/mips: Clean up handling of CP0 register 8 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: aurelien@aurel32.net, amarkovic@wavecomp.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Aleksandar Markovic Clean up handling of CP0 register 8. Signed-off-by: Aleksandar Markovic --- target/mips/cpu.h | 1 + target/mips/translate.c | 32 ++++++++++++++++---------------- 2 files changed, 17 insertions(+), 16 deletions(-) diff --git a/target/mips/cpu.h b/target/mips/cpu.h index c865b51..c7fdf1d 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -332,6 +332,7 @@ typedef struct mips_def_t mips_def_t; #define CP0_REG08__BADVADDR 0 #define CP0_REG08__BADINSTR 1 #define CP0_REG08__BADINSTRP 2 +#define CP0_REG08__BADINSTRX 3 /* CP0 Register 09 */ #define CP0_REG09__COUNT 0 #define CP0_REG09__SAARI 6 diff --git a/target/mips/translate.c b/target/mips/translate.c index abbb924..c046a10 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -7141,22 +7141,22 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, i= nt reg, int sel) break; case CP0_REGISTER_08: switch (sel) { - case 0: + case CP0_REG08__BADVADDR: tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_BadVAdd= r)); tcg_gen_ext32s_tl(arg, arg); register_name =3D "BadVAddr"; break; - case 1: + case CP0_REG08__BADINSTR: CP0_CHECK(ctx->bi); gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_BadInstr)); register_name =3D "BadInstr"; break; - case 2: + case CP0_REG08__BADINSTRP: CP0_CHECK(ctx->bp); gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_BadInstrP)); register_name =3D "BadInstrP"; break; - case 3: + case CP0_REG08__BADINSTRX: CP0_CHECK(ctx->bi); gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_BadInstrX)); tcg_gen_andi_tl(arg, arg, ~0xffff); @@ -7881,19 +7881,19 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, i= nt reg, int sel) break; case CP0_REGISTER_08: switch (sel) { - case 0: + case CP0_REG08__BADVADDR: /* ignored */ register_name =3D "BadVAddr"; break; - case 1: + case CP0_REG08__BADINSTR: /* ignored */ register_name =3D "BadInstr"; break; - case 2: + case CP0_REG08__BADINSTRP: /* ignored */ register_name =3D "BadInstrP"; break; - case 3: + case CP0_REG08__BADINSTRX: /* ignored */ register_name =3D "BadInstrX"; break; @@ -8630,21 +8630,21 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, = int reg, int sel) break; case CP0_REGISTER_08: switch (sel) { - case 0: + case CP0_REG08__BADVADDR: tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_BadVAdd= r)); register_name =3D "BadVAddr"; break; - case 1: + case CP0_REG08__BADINSTR: CP0_CHECK(ctx->bi); gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_BadInstr)); register_name =3D "BadInstr"; break; - case 2: + case CP0_REG08__BADINSTRP: CP0_CHECK(ctx->bp); gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_BadInstrP)); register_name =3D "BadInstrP"; break; - case 3: + case CP0_REG08__BADINSTRX: CP0_CHECK(ctx->bi); gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_BadInstrX)); tcg_gen_andi_tl(arg, arg, ~0xffff); @@ -9352,19 +9352,19 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, = int reg, int sel) break; case CP0_REGISTER_08: switch (sel) { - case 0: + case CP0_REG08__BADVADDR: /* ignored */ register_name =3D "BadVAddr"; break; - case 1: + case CP0_REG08__BADINSTR: /* ignored */ register_name =3D "BadInstr"; break; - case 2: + case CP0_REG08__BADINSTRP: /* ignored */ register_name =3D "BadInstrP"; break; - case 3: + case CP0_REG08__BADINSTRX: /* ignored */ register_name =3D "BadInstrX"; break; --=20 2.7.4 From nobody Tue May 7 19:36:37 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1566474844; cv=none; d=zoho.com; s=zohoarc; b=h22qkTDG9xFNUOKdXqrKg5SuTFQ/iOQawG9lbvgOfZzAZBn21VQn5RBrhWCYKFHxqCzv+nw0vwqq0DO8YSC8vCy99RrQ/KwnGQTj4HwHonEmdjpWwtGRdodXfX7JpsFXSYq4XtX8ROvzBJlctbMs3JqVRMcq8E5HaevUC6BqeGg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1566474844; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; 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Thu, 22 Aug 2019 07:37:21 -0400 Received: from mx2.rt-rk.com ([89.216.37.149]:48185 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1i0lOw-0007hu-EM for qemu-devel@nongnu.org; Thu, 22 Aug 2019 07:37:12 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id 8B3561A2053; Thu, 22 Aug 2019 13:35:58 +0200 (CEST) Received: from rtrkw774-lin.domain.local (rtrkw774-lin.domain.local [10.10.13.43]) by mail.rt-rk.com (Postfix) with ESMTPSA id 5C6DA1A2080; Thu, 22 Aug 2019 13:35:58 +0200 (CEST) X-Virus-Scanned: amavisd-new at rt-rk.com From: Aleksandar Markovic To: qemu-devel@nongnu.org Date: Thu, 22 Aug 2019 13:35:32 +0200 Message-Id: <1566473750-17743-9-git-send-email-aleksandar.markovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1566473750-17743-1-git-send-email-aleksandar.markovic@rt-rk.com> References: <1566473750-17743-1-git-send-email-aleksandar.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 89.216.37.149 Subject: [Qemu-devel] [PATCH 08/26] target/mips: Clean up handling of CP0 register 9 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: aurelien@aurel32.net, amarkovic@wavecomp.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Aleksandar Markovic Clean up handling of CP0 register 9. Signed-off-by: Aleksandar Markovic --- target/mips/translate.c | 28 ++++++++++++++-------------- 1 file changed, 14 insertions(+), 14 deletions(-) diff --git a/target/mips/translate.c b/target/mips/translate.c index c046a10..f8baa95 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -6660,7 +6660,7 @@ static void gen_mfhc0(DisasContext *ctx, TCGv arg, in= t reg, int sel) break; case CP0_REGISTER_09: switch (sel) { - case 7: + case CP0_REG09__SAAR: CP0_CHECK(ctx->saar); gen_helper_mfhc0_saar(arg, cpu_env); register_name =3D "SAAR"; @@ -6761,7 +6761,7 @@ static void gen_mthc0(DisasContext *ctx, TCGv arg, in= t reg, int sel) break; case CP0_REGISTER_09: switch (sel) { - case 7: + case CP0_REG09__SAAR: CP0_CHECK(ctx->saar); gen_helper_mthc0_saar(cpu_env, arg); register_name =3D "SAAR"; @@ -7168,7 +7168,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int= reg, int sel) break; case CP0_REGISTER_09: switch (sel) { - case 0: + case CP0_REG09__COUNT: /* Mark as an IO operation because we read the time. */ if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { gen_io_start(); @@ -7186,12 +7186,12 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, i= nt reg, int sel) ctx->base.is_jmp =3D DISAS_EXIT; register_name =3D "Count"; break; - case 6: + case CP0_REG09__SAARI: CP0_CHECK(ctx->saar); gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SAARI)); register_name =3D "SAARI"; break; - case 7: + case CP0_REG09__SAAR: CP0_CHECK(ctx->saar); gen_helper_mfc0_saar(arg, cpu_env); register_name =3D "SAAR"; @@ -7903,16 +7903,16 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, i= nt reg, int sel) break; case CP0_REGISTER_09: switch (sel) { - case 0: + case CP0_REG09__COUNT: gen_helper_mtc0_count(cpu_env, arg); register_name =3D "Count"; break; - case 6: + case CP0_REG09__SAARI: CP0_CHECK(ctx->saar); gen_helper_mtc0_saari(cpu_env, arg); register_name =3D "SAARI"; break; - case 7: + case CP0_REG09__SAAR: CP0_CHECK(ctx->saar); gen_helper_mtc0_saar(cpu_env, arg); register_name =3D "SAAR"; @@ -8656,7 +8656,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, in= t reg, int sel) break; case CP0_REGISTER_09: switch (sel) { - case 0: + case CP0_REG09__COUNT: /* Mark as an IO operation because we read the time. */ if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { gen_io_start(); @@ -8674,12 +8674,12 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, = int reg, int sel) ctx->base.is_jmp =3D DISAS_EXIT; register_name =3D "Count"; break; - case 6: + case CP0_REG09__SAARI: CP0_CHECK(ctx->saar); gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SAARI)); register_name =3D "SAARI"; break; - case 7: + case CP0_REG09__SAAR: CP0_CHECK(ctx->saar); gen_helper_dmfc0_saar(arg, cpu_env); register_name =3D "SAAR"; @@ -9374,16 +9374,16 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, = int reg, int sel) break; case CP0_REGISTER_09: switch (sel) { - case 0: + case CP0_REG09__COUNT: gen_helper_mtc0_count(cpu_env, arg); register_name =3D "Count"; break; - case 6: + case CP0_REG09__SAARI: CP0_CHECK(ctx->saar); gen_helper_mtc0_saari(cpu_env, arg); register_name =3D "SAARI"; break; - case 7: + case CP0_REG09__SAAR: CP0_CHECK(ctx->saar); gen_helper_mtc0_saar(cpu_env, arg); register_name =3D "SAAR"; --=20 2.7.4 From nobody Tue May 7 19:36:37 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1566474061; cv=none; d=zoho.com; s=zohoarc; b=UuEtUwbsn4ZI44J7eMPGGZsvYxt4sUt+NTUICmQeNG4jpklW7VkiCo0SDticACrg0QNM+Lla2DXm+rR08X8sktOPPJB2gKnq8kqphWY69pPdoSD5Qe4dB2+7kTivVLLkKptRFKoiuWgyVZLymy7sNI1nfm3vWqHJKA5Xx0/uRcU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1566474061; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; 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Thu, 22 Aug 2019 07:37:15 -0400 Received: from mx2.rt-rk.com ([89.216.37.149]:48182 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1i0lOs-0007hm-O9 for qemu-devel@nongnu.org; Thu, 22 Aug 2019 07:37:06 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id 96F0A1A204B; Thu, 22 Aug 2019 13:35:58 +0200 (CEST) Received: from rtrkw774-lin.domain.local (rtrkw774-lin.domain.local [10.10.13.43]) by mail.rt-rk.com (Postfix) with ESMTPSA id 645391A2073; Thu, 22 Aug 2019 13:35:58 +0200 (CEST) X-Virus-Scanned: amavisd-new at rt-rk.com From: Aleksandar Markovic To: qemu-devel@nongnu.org Date: Thu, 22 Aug 2019 13:35:33 +0200 Message-Id: <1566473750-17743-10-git-send-email-aleksandar.markovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1566473750-17743-1-git-send-email-aleksandar.markovic@rt-rk.com> References: <1566473750-17743-1-git-send-email-aleksandar.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 89.216.37.149 Subject: [Qemu-devel] [PATCH 09/26] target/mips: Clean up handling of CP0 register 10 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: aurelien@aurel32.net, amarkovic@wavecomp.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Aleksandar Markovic Clean up handling of CP0 register 10. Signed-off-by: Aleksandar Markovic --- target/mips/cpu.h | 1 + target/mips/translate.c | 8 ++++---- 2 files changed, 5 insertions(+), 4 deletions(-) diff --git a/target/mips/cpu.h b/target/mips/cpu.h index c7fdf1d..5e08b78 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -341,6 +341,7 @@ typedef struct mips_def_t mips_def_t; #define CP0_REG10__ENTRYHI 0 #define CP0_REG10__GUESTCTL1 4 #define CP0_REG10__GUESTCTL2 5 +#define CP0_REG10__GUESTCTL3 6 /* CP0 Register 11 */ #define CP0_REG11__COMPARE 0 #define CP0_REG11__GUESTCTL0EXT 4 diff --git a/target/mips/translate.c b/target/mips/translate.c index f8baa95..b376103 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -7202,7 +7202,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int= reg, int sel) break; case CP0_REGISTER_10: switch (sel) { - case 0: + case CP0_REG10__ENTRYHI: tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_EntryHi= )); tcg_gen_ext32s_tl(arg, arg); register_name =3D "EntryHi"; @@ -7923,7 +7923,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int= reg, int sel) break; case CP0_REGISTER_10: switch (sel) { - case 0: + case CP0_REG10__ENTRYHI: gen_helper_mtc0_entryhi(cpu_env, arg); register_name =3D "EntryHi"; break; @@ -8690,7 +8690,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, in= t reg, int sel) break; case CP0_REGISTER_10: switch (sel) { - case 0: + case CP0_REG10__ENTRYHI: tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_EntryHi= )); register_name =3D "EntryHi"; break; @@ -9396,7 +9396,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, in= t reg, int sel) break; case CP0_REGISTER_10: switch (sel) { - case 0: + case CP0_REG10__ENTRYHI: gen_helper_mtc0_entryhi(cpu_env, arg); register_name =3D "EntryHi"; break; --=20 2.7.4 From nobody Tue May 7 19:36:38 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; 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Thu, 22 Aug 2019 13:35:58 +0200 (CEST) X-Virus-Scanned: amavisd-new at rt-rk.com From: Aleksandar Markovic To: qemu-devel@nongnu.org Date: Thu, 22 Aug 2019 13:35:34 +0200 Message-Id: <1566473750-17743-11-git-send-email-aleksandar.markovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1566473750-17743-1-git-send-email-aleksandar.markovic@rt-rk.com> References: <1566473750-17743-1-git-send-email-aleksandar.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 89.216.37.149 Subject: [Qemu-devel] [PATCH 10/26] target/mips: Clean up handling of CP0 register 11 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: aurelien@aurel32.net, amarkovic@wavecomp.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Aleksandar Markovic Clean up handling of CP0 register 11. Signed-off-by: Aleksandar Markovic --- target/mips/translate.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/target/mips/translate.c b/target/mips/translate.c index b376103..87257d7 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -7213,7 +7213,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int= reg, int sel) break; case CP0_REGISTER_11: switch (sel) { - case 0: + case CP0_REG11__COMPARE: gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Compare)); register_name =3D "Compare"; break; @@ -7933,7 +7933,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int= reg, int sel) break; case CP0_REGISTER_11: switch (sel) { - case 0: + case CP0_REG11__COMPARE: gen_helper_mtc0_compare(cpu_env, arg); register_name =3D "Compare"; break; @@ -8700,7 +8700,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, in= t reg, int sel) break; case CP0_REGISTER_11: switch (sel) { - case 0: + case CP0_REG11__COMPARE: gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Compare)); register_name =3D "Compare"; break; @@ -9406,7 +9406,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, in= t reg, int sel) break; case CP0_REGISTER_11: switch (sel) { - case 0: + case CP0_REG11__COMPARE: gen_helper_mtc0_compare(cpu_env, arg); register_name =3D "Compare"; break; --=20 2.7.4 From nobody Tue May 7 19:36:38 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1566475266; cv=none; d=zoho.com; s=zohoarc; b=ft6dT5G9j57r21JMBCkGPlddCdfBZ1hasM7zbffMFA7uglZZv+l4ntimnsMb/Enr6/Zo85SKL1BjFCJfKwNQF6RfTnckTLpaHDw0u3T5jKV3kKP4Sb5jIH2UeRyKwsESVdFYv6gQ2xKybIMTaxBXyDuOTzYBz7PHzPzL8FBaW1g= ARC-Message-Signature: i=1; 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Thu, 22 Aug 2019 07:37:34 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1i0lP9-0007xV-3E for qemu-devel@nongnu.org; Thu, 22 Aug 2019 07:37:30 -0400 Received: from mx2.rt-rk.com ([89.216.37.149]:48211 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1i0lP8-0007ik-BR for qemu-devel@nongnu.org; Thu, 22 Aug 2019 07:37:22 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id B46691A2073; Thu, 22 Aug 2019 13:35:58 +0200 (CEST) Received: from rtrkw774-lin.domain.local (rtrkw774-lin.domain.local [10.10.13.43]) by mail.rt-rk.com (Postfix) with ESMTPSA id 87C241A2044; Thu, 22 Aug 2019 13:35:58 +0200 (CEST) X-Virus-Scanned: amavisd-new at rt-rk.com From: Aleksandar Markovic To: qemu-devel@nongnu.org Date: Thu, 22 Aug 2019 13:35:35 +0200 Message-Id: <1566473750-17743-12-git-send-email-aleksandar.markovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1566473750-17743-1-git-send-email-aleksandar.markovic@rt-rk.com> References: <1566473750-17743-1-git-send-email-aleksandar.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 89.216.37.149 Subject: [Qemu-devel] [PATCH 11/26] target/mips: Clean up handling of CP0 register 12 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: aurelien@aurel32.net, amarkovic@wavecomp.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Aleksandar Markovic Clean up handling of CP0 register 12. Signed-off-by: Aleksandar Markovic --- target/mips/cpu.h | 3 +++ target/mips/translate.c | 32 ++++++++++++++++---------------- 2 files changed, 19 insertions(+), 16 deletions(-) diff --git a/target/mips/cpu.h b/target/mips/cpu.h index 5e08b78..d61b8c0 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -349,6 +349,9 @@ typedef struct mips_def_t mips_def_t; #define CP0_REG12__STATUS 0 #define CP0_REG12__INTCTL 1 #define CP0_REG12__SRSCTL 2 +#define CP0_REG12__SRSMAP 3 +#define CP0_REG12__VIEW_IPL 4 +#define CP0_REG12__SRSMAP2 5 #define CP0_REG12__GUESTCTL0 6 #define CP0_REG12__GTOFFSET 7 /* CP0 Register 13 */ diff --git a/target/mips/translate.c b/target/mips/translate.c index 87257d7..642c108 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -7224,21 +7224,21 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, i= nt reg, int sel) break; case CP0_REGISTER_12: switch (sel) { - case 0: + case CP0_REG12__STATUS: gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Status)); register_name =3D "Status"; break; - case 1: + case CP0_REG12__INTCTL: check_insn(ctx, ISA_MIPS32R2); gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_IntCtl)); register_name =3D "IntCtl"; break; - case 2: + case CP0_REG12__SRSCTL: check_insn(ctx, ISA_MIPS32R2); gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSCtl)); register_name =3D "SRSCtl"; break; - case 3: + case CP0_REG12__SRSMAP: check_insn(ctx, ISA_MIPS32R2); gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSMap)); register_name =3D "SRSMap"; @@ -7944,7 +7944,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int= reg, int sel) break; case CP0_REGISTER_12: switch (sel) { - case 0: + case CP0_REG12__STATUS: save_cpu_state(ctx, 1); gen_helper_mtc0_status(cpu_env, arg); /* DISAS_STOP isn't good enough here, hflags may have changed.= */ @@ -7952,21 +7952,21 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, i= nt reg, int sel) ctx->base.is_jmp =3D DISAS_EXIT; register_name =3D "Status"; break; - case 1: + case CP0_REG12__INTCTL: check_insn(ctx, ISA_MIPS32R2); gen_helper_mtc0_intctl(cpu_env, arg); /* Stop translation as we may have switched the execution mode= */ ctx->base.is_jmp =3D DISAS_STOP; register_name =3D "IntCtl"; break; - case 2: + case CP0_REG12__SRSCTL: check_insn(ctx, ISA_MIPS32R2); gen_helper_mtc0_srsctl(cpu_env, arg); /* Stop translation as we may have switched the execution mode= */ ctx->base.is_jmp =3D DISAS_STOP; register_name =3D "SRSCtl"; break; - case 3: + case CP0_REG12__SRSMAP: check_insn(ctx, ISA_MIPS32R2); gen_mtc0_store32(arg, offsetof(CPUMIPSState, CP0_SRSMap)); /* Stop translation as we may have switched the execution mode= */ @@ -8711,21 +8711,21 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, = int reg, int sel) break; case CP0_REGISTER_12: switch (sel) { - case 0: + case CP0_REG12__STATUS: gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Status)); register_name =3D "Status"; break; - case 1: + case CP0_REG12__INTCTL: check_insn(ctx, ISA_MIPS32R2); gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_IntCtl)); register_name =3D "IntCtl"; break; - case 2: + case CP0_REG12__SRSCTL: check_insn(ctx, ISA_MIPS32R2); gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSCtl)); register_name =3D "SRSCtl"; break; - case 3: + case CP0_REG12__SRSMAP: check_insn(ctx, ISA_MIPS32R2); gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSMap)); register_name =3D "SRSMap"; @@ -9419,7 +9419,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, in= t reg, int sel) break; case CP0_REGISTER_12: switch (sel) { - case 0: + case CP0_REG12__STATUS: save_cpu_state(ctx, 1); gen_helper_mtc0_status(cpu_env, arg); /* DISAS_STOP isn't good enough here, hflags may have changed.= */ @@ -9427,21 +9427,21 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, = int reg, int sel) ctx->base.is_jmp =3D DISAS_EXIT; register_name =3D "Status"; break; - case 1: + case CP0_REG12__INTCTL: check_insn(ctx, ISA_MIPS32R2); gen_helper_mtc0_intctl(cpu_env, arg); /* Stop translation as we may have switched the execution mode= */ ctx->base.is_jmp =3D DISAS_STOP; register_name =3D "IntCtl"; break; - case 2: + case CP0_REG12__SRSCTL: check_insn(ctx, ISA_MIPS32R2); gen_helper_mtc0_srsctl(cpu_env, arg); /* Stop translation as we may have switched the execution mode= */ ctx->base.is_jmp =3D DISAS_STOP; register_name =3D "SRSCtl"; break; - case 3: + case CP0_REG12__SRSMAP: check_insn(ctx, ISA_MIPS32R2); gen_mtc0_store32(arg, offsetof(CPUMIPSState, CP0_SRSMap)); /* Stop translation as we may have switched the execution mode= */ --=20 2.7.4 From nobody Tue May 7 19:36:38 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1566474257; cv=none; d=zoho.com; s=zohoarc; b=gJV/WZxGW+xobc/JoD37Cp/+4dqqFhKpZqoet84s4ApRIoGi2qu06PrtDhQYNuWM79sxnoZoH3ZybU/ArqTbjIJebx2TVi3IWakISZ9F+DuZG5MG275GCK9ZwuV9kHlUJpYWMo+a1QkwEt/3CTpuv+KknI5xrZOuE6xHO9Npi90= ARC-Message-Signature: i=1; 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Thu, 22 Aug 2019 07:37:29 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1i0lP3-0007rv-IS for qemu-devel@nongnu.org; Thu, 22 Aug 2019 07:37:21 -0400 Received: from mx2.rt-rk.com ([89.216.37.149]:48212 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1i0lOw-0007ii-GI for qemu-devel@nongnu.org; Thu, 22 Aug 2019 07:37:12 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id B64A51A2089; Thu, 22 Aug 2019 13:35:58 +0200 (CEST) Received: from rtrkw774-lin.domain.local (rtrkw774-lin.domain.local [10.10.13.43]) by mail.rt-rk.com (Postfix) with ESMTPSA id 929651A2077; Thu, 22 Aug 2019 13:35:58 +0200 (CEST) X-Virus-Scanned: amavisd-new at rt-rk.com From: Aleksandar Markovic To: qemu-devel@nongnu.org Date: Thu, 22 Aug 2019 13:35:36 +0200 Message-Id: <1566473750-17743-13-git-send-email-aleksandar.markovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1566473750-17743-1-git-send-email-aleksandar.markovic@rt-rk.com> References: <1566473750-17743-1-git-send-email-aleksandar.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 89.216.37.149 Subject: [Qemu-devel] [PATCH 12/26] target/mips: Clean up handling of CP0 register 15 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: aurelien@aurel32.net, amarkovic@wavecomp.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Aleksandar Markovic Clean up handling of CP0 register 15. Signed-off-by: Aleksandar Markovic --- target/mips/cpu.h | 1 + target/mips/translate.c | 20 ++++++++++---------- 2 files changed, 11 insertions(+), 10 deletions(-) diff --git a/target/mips/cpu.h b/target/mips/cpu.h index d61b8c0..3a8c560 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -363,6 +363,7 @@ typedef struct mips_def_t mips_def_t; #define CP0_REG15__EBASE 1 #define CP0_REG15__CDMMBASE 2 #define CP0_REG15__CMGCRBASE 3 +#define CP0_REG15__BEVVA 4 /* CP0 Register 16 */ #define CP0_REG16__CONFIG 0 #define CP0_REG16__CONFIG1 1 diff --git a/target/mips/translate.c b/target/mips/translate.c index 642c108..97a274a 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -7270,17 +7270,17 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, i= nt reg, int sel) break; case CP0_REGISTER_15: switch (sel) { - case 0: + case CP0_REG15__PRID: gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PRid)); register_name =3D "PRid"; break; - case 1: + case CP0_REG15__EBASE: check_insn(ctx, ISA_MIPS32R2); tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_EBase)); tcg_gen_ext32s_tl(arg, arg); register_name =3D "EBase"; break; - case 3: + case CP0_REG15__CMGCRBASE: check_insn(ctx, ISA_MIPS32R2); CP0_CHECK(ctx->cmgcr); tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_CMGCRBa= se)); @@ -8007,11 +8007,11 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, i= nt reg, int sel) break; case CP0_REGISTER_15: switch (sel) { - case 0: + case CP0_REG15__PRID: /* ignored */ register_name =3D "PRid"; break; - case 1: + case CP0_REG15__EBASE: check_insn(ctx, ISA_MIPS32R2); gen_helper_mtc0_ebase(cpu_env, arg); register_name =3D "EBase"; @@ -8756,16 +8756,16 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, = int reg, int sel) break; case CP0_REGISTER_15: switch (sel) { - case 0: + case CP0_REG15__PRID: gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PRid)); register_name =3D "PRid"; break; - case 1: + case CP0_REG15__EBASE: check_insn(ctx, ISA_MIPS32R2); tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_EBase)); register_name =3D "EBase"; break; - case 3: + case CP0_REG15__CMGCRBASE: check_insn(ctx, ISA_MIPS32R2); CP0_CHECK(ctx->cmgcr); tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_CMGCRBa= se)); @@ -9482,11 +9482,11 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, = int reg, int sel) break; case CP0_REGISTER_15: switch (sel) { - case 0: + case CP0_REG15__PRID: /* ignored */ register_name =3D "PRid"; break; - case 1: + case CP0_REG15__EBASE: check_insn(ctx, ISA_MIPS32R2); gen_helper_mtc0_ebase(cpu_env, arg); register_name =3D "EBase"; --=20 2.7.4 From nobody Tue May 7 19:36:38 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; 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Thu, 22 Aug 2019 04:53:16 -0700 (PDT) Received: from localhost ([::1]:41447 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i0leV-0007IW-22 for importer@patchew.org; Thu, 22 Aug 2019 07:53:15 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:59872) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i0lP7-0004jp-UG for qemu-devel@nongnu.org; Thu, 22 Aug 2019 07:37:30 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1i0lP3-0007rU-Ek for qemu-devel@nongnu.org; Thu, 22 Aug 2019 07:37:21 -0400 Received: from mx2.rt-rk.com ([89.216.37.149]:48216 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1i0lOw-0007iw-E5 for qemu-devel@nongnu.org; Thu, 22 Aug 2019 07:37:12 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id CD5521A20A4; Thu, 22 Aug 2019 13:35:58 +0200 (CEST) Received: from rtrkw774-lin.domain.local (rtrkw774-lin.domain.local [10.10.13.43]) by mail.rt-rk.com (Postfix) with ESMTPSA id 9C4E01A2080; Thu, 22 Aug 2019 13:35:58 +0200 (CEST) X-Virus-Scanned: amavisd-new at rt-rk.com From: Aleksandar Markovic To: qemu-devel@nongnu.org Date: Thu, 22 Aug 2019 13:35:37 +0200 Message-Id: <1566473750-17743-14-git-send-email-aleksandar.markovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1566473750-17743-1-git-send-email-aleksandar.markovic@rt-rk.com> References: <1566473750-17743-1-git-send-email-aleksandar.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 89.216.37.149 Subject: [Qemu-devel] [PATCH 13/26] target/mips: Clean up handling of CP0 register 16 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: aurelien@aurel32.net, amarkovic@wavecomp.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Aleksandar Markovic Clean up handling of CP0 register 16. Signed-off-by: Aleksandar Markovic --- target/mips/cpu.h | 3 ++- target/mips/translate.c | 60 ++++++++++++++++++++++++---------------------= ---- 2 files changed, 32 insertions(+), 31 deletions(-) diff --git a/target/mips/cpu.h b/target/mips/cpu.h index 3a8c560..625d364 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -371,7 +371,8 @@ typedef struct mips_def_t mips_def_t; #define CP0_REG16__CONFIG3 3 #define CP0_REG16__CONFIG4 4 #define CP0_REG16__CONFIG5 5 -#define CP0_REG00__CONFIG7 7 +#define CP0_REG16__CONFIG6 6 +#define CP0_REG16__CONFIG7 7 /* CP0 Register 17 */ #define CP0_REG17__LLADDR 0 #define CP0_REG17__MAAR 1 diff --git a/target/mips/translate.c b/target/mips/translate.c index 97a274a..7878fcb 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -7293,36 +7293,36 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, i= nt reg, int sel) break; case CP0_REGISTER_16: switch (sel) { - case 0: + case CP0_REG16__CONFIG: gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config0)); register_name =3D "Config"; break; - case 1: + case CP0_REG16__CONFIG1: gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config1)); register_name =3D "Config1"; break; - case 2: + case CP0_REG16__CONFIG2: gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config2)); register_name =3D "Config2"; break; - case 3: + case CP0_REG16__CONFIG3: gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config3)); register_name =3D "Config3"; break; - case 4: + case CP0_REG16__CONFIG4: gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config4)); register_name =3D "Config4"; break; - case 5: + case CP0_REG16__CONFIG5: gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config5)); register_name =3D "Config5"; break; /* 6,7 are implementation dependent */ - case 6: + case CP0_REG16__CONFIG6: gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config6)); register_name =3D "Config6"; break; - case 7: + case CP0_REG16__CONFIG7: gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config7)); register_name =3D "Config7"; break; @@ -8022,45 +8022,45 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, i= nt reg, int sel) break; case CP0_REGISTER_16: switch (sel) { - case 0: + case CP0_REG16__CONFIG: gen_helper_mtc0_config0(cpu_env, arg); register_name =3D "Config"; /* Stop translation as we may have switched the execution mode= */ ctx->base.is_jmp =3D DISAS_STOP; break; - case 1: + case CP0_REG16__CONFIG1: /* ignored, read only */ register_name =3D "Config1"; break; - case 2: + case CP0_REG16__CONFIG2: gen_helper_mtc0_config2(cpu_env, arg); register_name =3D "Config2"; /* Stop translation as we may have switched the execution mode= */ ctx->base.is_jmp =3D DISAS_STOP; break; - case 3: + case CP0_REG16__CONFIG3: gen_helper_mtc0_config3(cpu_env, arg); register_name =3D "Config3"; /* Stop translation as we may have switched the execution mode= */ ctx->base.is_jmp =3D DISAS_STOP; break; - case 4: + case CP0_REG16__CONFIG4: gen_helper_mtc0_config4(cpu_env, arg); register_name =3D "Config4"; ctx->base.is_jmp =3D DISAS_STOP; break; - case 5: + case CP0_REG16__CONFIG5: gen_helper_mtc0_config5(cpu_env, arg); register_name =3D "Config5"; /* Stop translation as we may have switched the execution mode= */ ctx->base.is_jmp =3D DISAS_STOP; break; /* 6,7 are implementation dependent */ - case 6: + case CP0_REG16__CONFIG6: /* ignored */ register_name =3D "Config6"; break; - case 7: + case CP0_REG16__CONFIG7: /* ignored */ register_name =3D "Config7"; break; @@ -8777,36 +8777,36 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, = int reg, int sel) break; case CP0_REGISTER_16: switch (sel) { - case 0: + case CP0_REG16__CONFIG: gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config0)); register_name =3D "Config"; break; - case 1: + case CP0_REG16__CONFIG1: gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config1)); register_name =3D "Config1"; break; - case 2: + case CP0_REG16__CONFIG2: gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config2)); register_name =3D "Config2"; break; - case 3: + case CP0_REG16__CONFIG3: gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config3)); register_name =3D "Config3"; break; - case 4: + case CP0_REG16__CONFIG4: gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config4)); register_name =3D "Config4"; break; - case 5: + case CP0_REG16__CONFIG5: gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config5)); register_name =3D "Config5"; break; /* 6,7 are implementation dependent */ - case 6: + case CP0_REG16__CONFIG6: gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config6)); register_name =3D "Config6"; break; - case 7: + case CP0_REG16__CONFIG7: gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config7)); register_name =3D "Config7"; break; @@ -9497,33 +9497,33 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, = int reg, int sel) break; case CP0_REGISTER_16: switch (sel) { - case 0: + case CP0_REG16__CONFIG: gen_helper_mtc0_config0(cpu_env, arg); register_name =3D "Config"; /* Stop translation as we may have switched the execution mode= */ ctx->base.is_jmp =3D DISAS_STOP; break; - case 1: + case CP0_REG16__CONFIG1: /* ignored, read only */ register_name =3D "Config1"; break; - case 2: + case CP0_REG16__CONFIG2: gen_helper_mtc0_config2(cpu_env, arg); register_name =3D "Config2"; /* Stop translation as we may have switched the execution mode= */ ctx->base.is_jmp =3D DISAS_STOP; break; - case 3: + case CP0_REG16__CONFIG3: gen_helper_mtc0_config3(cpu_env, arg); register_name =3D "Config3"; /* Stop translation as we may have switched the execution mode= */ ctx->base.is_jmp =3D DISAS_STOP; break; - case 4: + case CP0_REG16__CONFIG4: /* currently ignored */ register_name =3D "Config4"; break; - case 5: + case CP0_REG16__CONFIG5: gen_helper_mtc0_config5(cpu_env, arg); register_name =3D "Config5"; /* Stop translation as we may have switched the execution mode= */ --=20 2.7.4 From nobody Tue May 7 19:36:38 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; 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Thu, 22 Aug 2019 13:35:58 +0200 (CEST) X-Virus-Scanned: amavisd-new at rt-rk.com From: Aleksandar Markovic To: qemu-devel@nongnu.org Date: Thu, 22 Aug 2019 13:35:38 +0200 Message-Id: <1566473750-17743-15-git-send-email-aleksandar.markovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1566473750-17743-1-git-send-email-aleksandar.markovic@rt-rk.com> References: <1566473750-17743-1-git-send-email-aleksandar.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 89.216.37.149 Subject: [Qemu-devel] [PATCH 14/26] target/mips: Clean up handling of CP0 register 17 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: aurelien@aurel32.net, amarkovic@wavecomp.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Aleksandar Markovic Clean up handling of CP0 register 17. Signed-off-by: Aleksandar Markovic --- target/mips/translate.c | 32 ++++++++++++++++---------------- 1 file changed, 16 insertions(+), 16 deletions(-) diff --git a/target/mips/translate.c b/target/mips/translate.c index 7878fcb..51c8d29 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -6671,12 +6671,12 @@ static void gen_mfhc0(DisasContext *ctx, TCGv arg, = int reg, int sel) break; case CP0_REGISTER_17: switch (sel) { - case 0: + case CP0_REG17__LLADDR: gen_mfhc0_load64(arg, offsetof(CPUMIPSState, CP0_LLAddr), ctx->CP0_LLAddr_shift); register_name =3D "LLAddr"; break; - case 1: + case CP0_REG17__MAAR: CP0_CHECK(ctx->mrp); gen_helper_mfhc0_maar(arg, cpu_env); register_name =3D "MAAR"; @@ -6772,7 +6772,7 @@ static void gen_mthc0(DisasContext *ctx, TCGv arg, in= t reg, int sel) break; case CP0_REGISTER_17: switch (sel) { - case 0: + case CP0_REG17__LLADDR: /* * LLAddr is read-only (the only exception is bit 0 if LLB is * supported); the CP0_LLAddr_rw_bitmask does not seem to be @@ -6781,7 +6781,7 @@ static void gen_mthc0(DisasContext *ctx, TCGv arg, in= t reg, int sel) */ register_name =3D "LLAddr"; break; - case 1: + case CP0_REG17__MAAR: CP0_CHECK(ctx->mrp); gen_helper_mthc0_maar(cpu_env, arg); register_name =3D "MAAR"; @@ -7332,16 +7332,16 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, i= nt reg, int sel) break; case CP0_REGISTER_17: switch (sel) { - case 0: + case CP0_REG17__LLADDR: gen_helper_mfc0_lladdr(arg, cpu_env); register_name =3D "LLAddr"; break; - case 1: + case CP0_REG17__MAAR: CP0_CHECK(ctx->mrp); gen_helper_mfc0_maar(arg, cpu_env); register_name =3D "MAAR"; break; - case 2: + case CP0_REG17__MAARI: CP0_CHECK(ctx->mrp); gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_MAARI)); register_name =3D "MAARI"; @@ -8071,16 +8071,16 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, i= nt reg, int sel) break; case CP0_REGISTER_17: switch (sel) { - case 0: + case CP0_REG17__LLADDR: gen_helper_mtc0_lladdr(cpu_env, arg); register_name =3D "LLAddr"; break; - case 1: + case CP0_REG17__MAAR: CP0_CHECK(ctx->mrp); gen_helper_mtc0_maar(cpu_env, arg); register_name =3D "MAAR"; break; - case 2: + case CP0_REG17__MAARI: CP0_CHECK(ctx->mrp); gen_helper_mtc0_maari(cpu_env, arg); register_name =3D "MAARI"; @@ -8816,16 +8816,16 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, = int reg, int sel) break; case CP0_REGISTER_17: switch (sel) { - case 0: + case CP0_REG17__LLADDR: gen_helper_dmfc0_lladdr(arg, cpu_env); register_name =3D "LLAddr"; break; - case 1: + case CP0_REG17__MAAR: CP0_CHECK(ctx->mrp); gen_helper_dmfc0_maar(arg, cpu_env); register_name =3D "MAAR"; break; - case 2: + case CP0_REG17__MAARI: CP0_CHECK(ctx->mrp); gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_MAARI)); register_name =3D "MAARI"; @@ -9537,16 +9537,16 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, = int reg, int sel) break; case CP0_REGISTER_17: switch (sel) { - case 0: + case CP0_REG17__LLADDR: gen_helper_mtc0_lladdr(cpu_env, arg); register_name =3D "LLAddr"; break; - case 1: + case CP0_REG17__MAAR: CP0_CHECK(ctx->mrp); gen_helper_mtc0_maar(cpu_env, arg); register_name =3D "MAAR"; break; - case 2: + case CP0_REG17__MAARI: CP0_CHECK(ctx->mrp); gen_helper_mtc0_maari(cpu_env, arg); register_name =3D "MAARI"; --=20 2.7.4 From nobody Tue May 7 19:36:38 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1566475031; cv=none; d=zoho.com; s=zohoarc; b=iN7wxgxc2hBJyO/YLnMCdWUfDEng38IWNPCg7zE43xNR0NpjxICr8LJHmVhAlPxqK01LRshKAkO0muwcV0Tem0AskPhO+WJ77psT7Kf5R1h0fPW3xyzYZ2dLGquXvJK+4l74Bx7o3lxsm8M1KJ4nL8rGzMTJp1aim6XsRMFDkyE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1566475031; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; 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Thu, 22 Aug 2019 07:37:29 -0400 Received: from mx2.rt-rk.com ([89.216.37.149]:48245 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1i0lP7-0007kA-LQ for qemu-devel@nongnu.org; Thu, 22 Aug 2019 07:37:22 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id ED3901A2088; Thu, 22 Aug 2019 13:35:58 +0200 (CEST) Received: from rtrkw774-lin.domain.local (rtrkw774-lin.domain.local [10.10.13.43]) by mail.rt-rk.com (Postfix) with ESMTPSA id BD3951A20A0; Thu, 22 Aug 2019 13:35:58 +0200 (CEST) X-Virus-Scanned: amavisd-new at rt-rk.com From: Aleksandar Markovic To: qemu-devel@nongnu.org Date: Thu, 22 Aug 2019 13:35:39 +0200 Message-Id: <1566473750-17743-16-git-send-email-aleksandar.markovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1566473750-17743-1-git-send-email-aleksandar.markovic@rt-rk.com> References: <1566473750-17743-1-git-send-email-aleksandar.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 89.216.37.149 Subject: [Qemu-devel] [PATCH 15/26] target/mips: Clean up handling of CP0 register 18 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: aurelien@aurel32.net, amarkovic@wavecomp.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Aleksandar Markovic Clean up handling of CP0 register 18. Signed-off-by: Aleksandar Markovic --- target/mips/cpu.h | 20 +++++++++------- target/mips/translate.c | 64 ++++++++++++++++++++++++---------------------= ---- 2 files changed, 44 insertions(+), 40 deletions(-) diff --git a/target/mips/cpu.h b/target/mips/cpu.h index 625d364..b18c87b 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -194,14 +194,14 @@ typedef struct mips_def_t mips_def_t; * Register 16 Register 17 Register 18 Register 19 * ----------- ----------- ----------- ----------- * - * 0 Config LLAddr WatchLo WatchHi - * 1 Config1 MAAR WatchLo WatchHi - * 2 Config2 MAARI WatchLo WatchHi - * 3 Config3 WatchLo WatchHi - * 4 Config4 WatchLo WatchHi - * 5 Config5 WatchLo WatchHi - * 6 WatchLo WatchHi - * 7 WatchLo WatchHi + * 0 Config LLAddr WatchLo0 WatchHi + * 1 Config1 MAAR WatchLo1 WatchHi + * 2 Config2 MAARI WatchLo2 WatchHi + * 3 Config3 WatchLo3 WatchHi + * 4 Config4 WatchLo4 WatchHi + * 5 Config5 WatchLo5 WatchHi + * 6 WatchLo6 WatchHi + * 7 WatchLo7 WatchHi * * * Register 20 Register 21 Register 22 Register 23 @@ -382,6 +382,10 @@ typedef struct mips_def_t mips_def_t; #define CP0_REG18__WATCHLO1 1 #define CP0_REG18__WATCHLO2 2 #define CP0_REG18__WATCHLO3 3 +#define CP0_REG18__WATCHLO4 4 +#define CP0_REG18__WATCHLO5 5 +#define CP0_REG18__WATCHLO6 6 +#define CP0_REG18__WATCHLO7 7 /* CP0 Register 19 */ #define CP0_REG19__WATCHHI0 0 #define CP0_REG19__WATCHHI1 1 diff --git a/target/mips/translate.c b/target/mips/translate.c index 51c8d29..8c66db4 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -7352,14 +7352,14 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, i= nt reg, int sel) break; case CP0_REGISTER_18: switch (sel) { - case 0: - case 1: - case 2: - case 3: - case 4: - case 5: - case 6: - case 7: + case CP0_REG18__WATCHLO0: + case CP0_REG18__WATCHLO1: + case CP0_REG18__WATCHLO2: + case CP0_REG18__WATCHLO3: + case CP0_REG18__WATCHLO4: + case CP0_REG18__WATCHLO5: + case CP0_REG18__WATCHLO6: + case CP0_REG18__WATCHLO7: CP0_CHECK(ctx->CP0_Config1 & (1 << CP0C1_WR)); gen_helper_1e0i(mfc0_watchlo, arg, sel); register_name =3D "WatchLo"; @@ -8091,14 +8091,14 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, i= nt reg, int sel) break; case CP0_REGISTER_18: switch (sel) { - case 0: - case 1: - case 2: - case 3: - case 4: - case 5: - case 6: - case 7: + case CP0_REG18__WATCHLO0: + case CP0_REG18__WATCHLO1: + case CP0_REG18__WATCHLO2: + case CP0_REG18__WATCHLO3: + case CP0_REG18__WATCHLO4: + case CP0_REG18__WATCHLO5: + case CP0_REG18__WATCHLO6: + case CP0_REG18__WATCHLO7: CP0_CHECK(ctx->CP0_Config1 & (1 << CP0C1_WR)); gen_helper_0e1i(mtc0_watchlo, arg, sel); register_name =3D "WatchLo"; @@ -8836,14 +8836,14 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, = int reg, int sel) break; case CP0_REGISTER_18: switch (sel) { - case 0: - case 1: - case 2: - case 3: - case 4: - case 5: - case 6: - case 7: + case CP0_REG18__WATCHLO0: + case CP0_REG18__WATCHLO1: + case CP0_REG18__WATCHLO2: + case CP0_REG18__WATCHLO3: + case CP0_REG18__WATCHLO4: + case CP0_REG18__WATCHLO5: + case CP0_REG18__WATCHLO6: + case CP0_REG18__WATCHLO7: CP0_CHECK(ctx->CP0_Config1 & (1 << CP0C1_WR)); gen_helper_1e0i(dmfc0_watchlo, arg, sel); register_name =3D "WatchLo"; @@ -9557,14 +9557,14 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, = int reg, int sel) break; case CP0_REGISTER_18: switch (sel) { - case 0: - case 1: - case 2: - case 3: - case 4: - case 5: - case 6: - case 7: + case CP0_REG18__WATCHLO0: + case CP0_REG18__WATCHLO1: + case CP0_REG18__WATCHLO2: + case CP0_REG18__WATCHLO3: + case CP0_REG18__WATCHLO4: + case CP0_REG18__WATCHLO5: + case CP0_REG18__WATCHLO6: + case CP0_REG18__WATCHLO7: CP0_CHECK(ctx->CP0_Config1 & (1 << CP0C1_WR)); gen_helper_0e1i(mtc0_watchlo, arg, sel); register_name =3D "WatchLo"; --=20 2.7.4 From nobody Tue May 7 19:36:38 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; 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Thu, 22 Aug 2019 13:35:58 +0200 (CEST) X-Virus-Scanned: amavisd-new at rt-rk.com From: Aleksandar Markovic To: qemu-devel@nongnu.org Date: Thu, 22 Aug 2019 13:35:40 +0200 Message-Id: <1566473750-17743-17-git-send-email-aleksandar.markovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1566473750-17743-1-git-send-email-aleksandar.markovic@rt-rk.com> References: <1566473750-17743-1-git-send-email-aleksandar.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 89.216.37.149 Subject: [Qemu-devel] [PATCH 16/26] target/mips: Clean up handling of CP0 register 19 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: aurelien@aurel32.net, amarkovic@wavecomp.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Aleksandar Markovic Clean up handling of CP0 register 19. Signed-off-by: Aleksandar Markovic --- target/mips/cpu.h | 4 ++++ target/mips/translate.c | 64 ++++++++++++++++++++++++---------------------= ---- 2 files changed, 36 insertions(+), 32 deletions(-) diff --git a/target/mips/cpu.h b/target/mips/cpu.h index b18c87b..811986b 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -391,6 +391,10 @@ typedef struct mips_def_t mips_def_t; #define CP0_REG19__WATCHHI1 1 #define CP0_REG19__WATCHHI2 2 #define CP0_REG19__WATCHHI3 3 +#define CP0_REG19__WATCHHI4 4 +#define CP0_REG19__WATCHHI5 5 +#define CP0_REG19__WATCHHI6 6 +#define CP0_REG19__WATCHHI7 7 /* CP0 Register 20 */ #define CP0_REG20__XCONTEXT 0 /* CP0 Register 21 */ diff --git a/target/mips/translate.c b/target/mips/translate.c index 8c66db4..40df031 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -7370,14 +7370,14 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, i= nt reg, int sel) break; case CP0_REGISTER_19: switch (sel) { - case 0: - case 1: - case 2: - case 3: - case 4: - case 5: - case 6: - case 7: + case CP0_REG19__WATCHHI0: + case CP0_REG19__WATCHHI1: + case CP0_REG19__WATCHHI2: + case CP0_REG19__WATCHHI3: + case CP0_REG19__WATCHHI4: + case CP0_REG19__WATCHHI5: + case CP0_REG19__WATCHHI6: + case CP0_REG19__WATCHHI7: CP0_CHECK(ctx->CP0_Config1 & (1 << CP0C1_WR)); gen_helper_1e0i(mfc0_watchhi, arg, sel); register_name =3D "WatchHi"; @@ -8109,14 +8109,14 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, i= nt reg, int sel) break; case CP0_REGISTER_19: switch (sel) { - case 0: - case 1: - case 2: - case 3: - case 4: - case 5: - case 6: - case 7: + case CP0_REG19__WATCHHI0: + case CP0_REG19__WATCHHI1: + case CP0_REG19__WATCHHI2: + case CP0_REG19__WATCHHI3: + case CP0_REG19__WATCHHI4: + case CP0_REG19__WATCHHI5: + case CP0_REG19__WATCHHI6: + case CP0_REG19__WATCHHI7: CP0_CHECK(ctx->CP0_Config1 & (1 << CP0C1_WR)); gen_helper_0e1i(mtc0_watchhi, arg, sel); register_name =3D "WatchHi"; @@ -8854,14 +8854,14 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, = int reg, int sel) break; case CP0_REGISTER_19: switch (sel) { - case 0: - case 1: - case 2: - case 3: - case 4: - case 5: - case 6: - case 7: + case CP0_REG19__WATCHHI0: + case CP0_REG19__WATCHHI1: + case CP0_REG19__WATCHHI2: + case CP0_REG19__WATCHHI3: + case CP0_REG19__WATCHHI4: + case CP0_REG19__WATCHHI5: + case CP0_REG19__WATCHHI6: + case CP0_REG19__WATCHHI7: CP0_CHECK(ctx->CP0_Config1 & (1 << CP0C1_WR)); gen_helper_1e0i(dmfc0_watchhi, arg, sel); register_name =3D "WatchHi"; @@ -9575,14 +9575,14 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, = int reg, int sel) break; case CP0_REGISTER_19: switch (sel) { - case 0: - case 1: - case 2: - case 3: - case 4: - case 5: - case 6: - case 7: + case CP0_REG19__WATCHHI0: + case CP0_REG19__WATCHHI1: + case CP0_REG19__WATCHHI2: + case CP0_REG19__WATCHHI3: + case CP0_REG19__WATCHHI4: + case CP0_REG19__WATCHHI5: + case CP0_REG19__WATCHHI6: + case CP0_REG19__WATCHHI7: CP0_CHECK(ctx->CP0_Config1 & (1 << CP0C1_WR)); gen_helper_0e1i(mtc0_watchhi, arg, sel); register_name =3D "WatchHi"; --=20 2.7.4 From nobody Tue May 7 19:36:38 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; 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Thu, 22 Aug 2019 13:35:58 +0200 (CEST) X-Virus-Scanned: amavisd-new at rt-rk.com From: Aleksandar Markovic To: qemu-devel@nongnu.org Date: Thu, 22 Aug 2019 13:35:41 +0200 Message-Id: <1566473750-17743-18-git-send-email-aleksandar.markovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1566473750-17743-1-git-send-email-aleksandar.markovic@rt-rk.com> References: <1566473750-17743-1-git-send-email-aleksandar.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 89.216.37.149 Subject: [Qemu-devel] [PATCH 17/26] target/mips: Clean up handling of CP0 register 20 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: aurelien@aurel32.net, amarkovic@wavecomp.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Aleksandar Markovic Clean up handling of CP0 register 20. Signed-off-by: Aleksandar Markovic --- target/mips/translate.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/target/mips/translate.c b/target/mips/translate.c index 40df031..175f6dc 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -7388,7 +7388,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int= reg, int sel) break; case CP0_REGISTER_20: switch (sel) { - case 0: + case CP0_REG20__XCONTEXT: #if defined(TARGET_MIPS64) check_insn(ctx, ISA_MIPS3); tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_XContex= t)); @@ -8127,7 +8127,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int= reg, int sel) break; case CP0_REGISTER_20: switch (sel) { - case 0: + case CP0_REG20__XCONTEXT: #if defined(TARGET_MIPS64) check_insn(ctx, ISA_MIPS3); gen_helper_mtc0_xcontext(cpu_env, arg); @@ -8872,7 +8872,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, in= t reg, int sel) break; case CP0_REGISTER_20: switch (sel) { - case 0: + case CP0_REG20__XCONTEXT: check_insn(ctx, ISA_MIPS3); tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_XContex= t)); register_name =3D "XContext"; @@ -9593,7 +9593,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, in= t reg, int sel) break; case CP0_REGISTER_20: switch (sel) { - case 0: + case CP0_REG20__XCONTEXT: check_insn(ctx, ISA_MIPS3); gen_helper_mtc0_xcontext(cpu_env, arg); register_name =3D "XContext"; --=20 2.7.4 From nobody Tue May 7 19:36:38 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1566475613; cv=none; d=zoho.com; s=zohoarc; b=MfUBmCJsnjg8/C2VaC9ZDbCD2yb2gbwrI8hnPksE3fKolyqxlqb+Vif48yJo0jRnykpIWDhiViBZbd/7B5ukntdKQobAKJ/l8AkvLgAqZWAz0OR0WAesPMGxP6TuCBzCSrGqzvEaQHdbrJwzlYKtbggn08qdbtC0TI740Fs7aQM= ARC-Message-Signature: i=1; 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Thu, 22 Aug 2019 07:37:41 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1i0lPI-00086Y-Tq for qemu-devel@nongnu.org; Thu, 22 Aug 2019 07:37:37 -0400 Received: from mx2.rt-rk.com ([89.216.37.149]:48297 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1i0lPI-0007lJ-84 for qemu-devel@nongnu.org; Thu, 22 Aug 2019 07:37:32 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id 1FF091A20AB; Thu, 22 Aug 2019 13:35:59 +0200 (CEST) Received: from rtrkw774-lin.domain.local (rtrkw774-lin.domain.local [10.10.13.43]) by mail.rt-rk.com (Postfix) with ESMTPSA id DA90F1A20A9; Thu, 22 Aug 2019 13:35:58 +0200 (CEST) X-Virus-Scanned: amavisd-new at rt-rk.com From: Aleksandar Markovic To: qemu-devel@nongnu.org Date: Thu, 22 Aug 2019 13:35:42 +0200 Message-Id: <1566473750-17743-19-git-send-email-aleksandar.markovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1566473750-17743-1-git-send-email-aleksandar.markovic@rt-rk.com> References: <1566473750-17743-1-git-send-email-aleksandar.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 89.216.37.149 Subject: [Qemu-devel] [PATCH 18/26] target/mips: Clean up handling of CP0 register 23 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: aurelien@aurel32.net, amarkovic@wavecomp.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Aleksandar Markovic Clean up handling of CP0 register 23. Signed-off-by: Aleksandar Markovic --- target/mips/cpu.h | 6 +++ target/mips/translate.c | 126 +++++++++++++++++++++++++++++++-------------= ---- 2 files changed, 89 insertions(+), 43 deletions(-) diff --git a/target/mips/cpu.h b/target/mips/cpu.h index 811986b..c14afcd 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -401,6 +401,12 @@ typedef struct mips_def_t mips_def_t; /* CP0 Register 22 */ /* CP0 Register 23 */ #define CP0_REG23__DEBUG 0 +#define CP0_REG23__TRACECONTROL 1 +#define CP0_REG23__TRACECONTROL2 2 +#define CP0_REG23__USERTRACEDATA1 3 +#define CP0_REG23__TRACEIBPC 4 +#define CP0_REG23__TRACEDBPC 5 +#define CP0_REG23__DEBUG2 6 /* CP0 Register 24 */ #define CP0_REG24__DEPC 0 /* CP0 Register 25 */ diff --git a/target/mips/translate.c b/target/mips/translate.c index 175f6dc..4272948 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -7418,25 +7418,34 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, i= nt reg, int sel) break; case CP0_REGISTER_23: switch (sel) { - case 0: + case CP0_REG23__DEBUG: gen_helper_mfc0_debug(arg, cpu_env); /* EJTAG support */ register_name =3D "Debug"; break; - case 1: -// gen_helper_mfc0_tracecontrol(arg); /* PDtrace support */ + case CP0_REG23__TRACECONTROL: + /* PDtrace support */ + /* gen_helper_mfc0_tracecontrol(arg); */ register_name =3D "TraceControl"; goto cp0_unimplemented; - case 2: -// gen_helper_mfc0_tracecontrol2(arg); /* PDtrace support */ + case CP0_REG23__TRACECONTROL2: + /* PDtrace support */ + /* gen_helper_mfc0_tracecontrol2(arg); */ register_name =3D "TraceControl2"; goto cp0_unimplemented; - case 3: -// gen_helper_mfc0_usertracedata(arg); /* PDtrace support */ - register_name =3D "UserTraceData"; + case CP0_REG23__USERTRACEDATA1: + /* PDtrace support */ + /* gen_helper_mfc0_usertracedata1(arg);*/ + register_name =3D "UserTraceData1"; goto cp0_unimplemented; - case 4: -// gen_helper_mfc0_tracebpc(arg); /* PDtrace support */ - register_name =3D "TraceBPC"; + case CP0_REG23__TRACEIBPC: + /* PDtrace support */ + /* gen_helper_mfc0_traceibpc(arg); */ + register_name =3D "TraceIBPC"; + goto cp0_unimplemented; + case CP0_REG23__TRACEDBPC: + /* PDtrace support */ + /* gen_helper_mfc0_tracedbpc(arg); */ + register_name =3D "TraceDBPC"; goto cp0_unimplemented; default: goto cp0_unimplemented; @@ -8156,38 +8165,49 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, i= nt reg, int sel) break; case CP0_REGISTER_23: switch (sel) { - case 0: + case CP0_REG23__DEBUG: gen_helper_mtc0_debug(cpu_env, arg); /* EJTAG support */ /* DISAS_STOP isn't good enough here, hflags may have changed.= */ gen_save_pc(ctx->base.pc_next + 4); ctx->base.is_jmp =3D DISAS_EXIT; register_name =3D "Debug"; break; - case 1: -// gen_helper_mtc0_tracecontrol(cpu_env, arg); /* PDtrace suppo= rt */ + case CP0_REG23__TRACECONTROL: + /* PDtrace support */ + /* gen_helper_mtc0_tracecontrol(cpu_env, arg); */ register_name =3D "TraceControl"; /* Stop translation as we may have switched the execution mode= */ ctx->base.is_jmp =3D DISAS_STOP; goto cp0_unimplemented; - case 2: -// gen_helper_mtc0_tracecontrol2(cpu_env, arg); /* PDtrace supp= ort */ + case CP0_REG23__TRACECONTROL2: + /* PDtrace support */ + /* gen_helper_mtc0_tracecontrol2(cpu_env, arg); */ register_name =3D "TraceControl2"; /* Stop translation as we may have switched the execution mode= */ ctx->base.is_jmp =3D DISAS_STOP; goto cp0_unimplemented; - case 3: + case CP0_REG23__USERTRACEDATA1: /* Stop translation as we may have switched the execution mode= */ ctx->base.is_jmp =3D DISAS_STOP; -// gen_helper_mtc0_usertracedata(cpu_env, arg); /* PDtrace supp= ort */ + /* PDtrace support */ + /* gen_helper_mtc0_usertracedata1(cpu_env, arg);*/ register_name =3D "UserTraceData"; /* Stop translation as we may have switched the execution mode= */ ctx->base.is_jmp =3D DISAS_STOP; goto cp0_unimplemented; - case 4: -// gen_helper_mtc0_tracebpc(cpu_env, arg); /* PDtrace support */ + case CP0_REG23__TRACEIBPC: + /* PDtrace support */ + /* gen_helper_mtc0_traceibpc(cpu_env, arg); */ /* Stop translation as we may have switched the execution mode= */ ctx->base.is_jmp =3D DISAS_STOP; - register_name =3D "TraceBPC"; + register_name =3D "TraceIBPC"; + goto cp0_unimplemented; + case CP0_REG23__TRACEDBPC: + /* PDtrace support */ + /* gen_helper_mtc0_tracedbpc(cpu_env, arg); */ + /* Stop translation as we may have switched the execution mode= */ + ctx->base.is_jmp =3D DISAS_STOP; + register_name =3D "TraceDBPC"; goto cp0_unimplemented; default: goto cp0_unimplemented; @@ -8899,25 +8919,34 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, = int reg, int sel) break; case CP0_REGISTER_23: switch (sel) { - case 0: + case CP0_REG23__DEBUG: gen_helper_mfc0_debug(arg, cpu_env); /* EJTAG support */ register_name =3D "Debug"; break; - case 1: -// gen_helper_dmfc0_tracecontrol(arg, cpu_env); /* PDtrace supp= ort */ + case CP0_REG23__TRACECONTROL: + /* PDtrace support */ + /* gen_helper_dmfc0_tracecontrol(arg, cpu_env); */ register_name =3D "TraceControl"; goto cp0_unimplemented; - case 2: -// gen_helper_dmfc0_tracecontrol2(arg, cpu_env); /* PDtrace sup= port */ + case CP0_REG23__TRACECONTROL2: + /* PDtrace support */ + /* gen_helper_dmfc0_tracecontrol2(arg, cpu_env); */ register_name =3D "TraceControl2"; goto cp0_unimplemented; - case 3: -// gen_helper_dmfc0_usertracedata(arg, cpu_env); /* PDtrace sup= port */ - register_name =3D "UserTraceData"; + case CP0_REG23__USERTRACEDATA1: + /* PDtrace support */ + /* gen_helper_dmfc0_usertracedata1(arg, cpu_env);*/ + register_name =3D "UserTraceData1"; goto cp0_unimplemented; - case 4: -// gen_helper_dmfc0_tracebpc(arg, cpu_env); /* PDtrace support = */ - register_name =3D "TraceBPC"; + case CP0_REG23__TRACEIBPC: + /* PDtrace support */ + /* gen_helper_dmfc0_traceibpc(arg, cpu_env); */ + register_name =3D "TraceIBPC"; + goto cp0_unimplemented; + case CP0_REG23__TRACEDBPC: + /* PDtrace support */ + /* gen_helper_dmfc0_tracedbpc(arg, cpu_env); */ + register_name =3D "TraceDBPC"; goto cp0_unimplemented; default: goto cp0_unimplemented; @@ -9620,36 +9649,47 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, = int reg, int sel) break; case CP0_REGISTER_23: switch (sel) { - case 0: + case CP0_REG23__DEBUG: gen_helper_mtc0_debug(cpu_env, arg); /* EJTAG support */ /* DISAS_STOP isn't good enough here, hflags may have changed.= */ gen_save_pc(ctx->base.pc_next + 4); ctx->base.is_jmp =3D DISAS_EXIT; register_name =3D "Debug"; break; - case 1: -// gen_helper_mtc0_tracecontrol(cpu_env, arg); /* PDtrace suppo= rt */ + case CP0_REG23__TRACECONTROL: + /* PDtrace support */ + /* gen_helper_mtc0_tracecontrol(cpu_env, arg); */ /* Stop translation as we may have switched the execution mode= */ ctx->base.is_jmp =3D DISAS_STOP; register_name =3D "TraceControl"; goto cp0_unimplemented; - case 2: -// gen_helper_mtc0_tracecontrol2(cpu_env, arg); /* PDtrace supp= ort */ + case CP0_REG23__TRACECONTROL2: + /* PDtrace support */ + /* gen_helper_mtc0_tracecontrol2(cpu_env, arg); */ /* Stop translation as we may have switched the execution mode= */ ctx->base.is_jmp =3D DISAS_STOP; register_name =3D "TraceControl2"; goto cp0_unimplemented; - case 3: -// gen_helper_mtc0_usertracedata(cpu_env, arg); /* PDtrace supp= ort */ + case CP0_REG23__USERTRACEDATA1: + /* PDtrace support */ + /* gen_helper_mtc0_usertracedata1(cpu_env, arg);*/ /* Stop translation as we may have switched the execution mode= */ ctx->base.is_jmp =3D DISAS_STOP; - register_name =3D "UserTraceData"; + register_name =3D "UserTraceData1"; goto cp0_unimplemented; - case 4: -// gen_helper_mtc0_tracebpc(cpu_env, arg); /* PDtrace support */ + case CP0_REG23__TRACEIBPC: + /* PDtrace support */ + /* gen_helper_mtc0_traceibpc(cpu_env, arg); */ + /* Stop translation as we may have switched the execution mode= */ + ctx->base.is_jmp =3D DISAS_STOP; + register_name =3D "TraceIBPC"; + goto cp0_unimplemented; + case CP0_REG23__TRACEDBPC: + /* PDtrace support */ + /* gen_helper_mtc0_tracedbpc(cpu_env, arg); */ /* Stop translation as we may have switched the execution mode= */ ctx->base.is_jmp =3D DISAS_STOP; - register_name =3D "TraceBPC"; + register_name =3D "TraceDBPC"; goto cp0_unimplemented; default: goto cp0_unimplemented; --=20 2.7.4 From nobody Tue May 7 19:36:38 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Thu, 22 Aug 2019 13:35:58 +0200 (CEST) X-Virus-Scanned: amavisd-new at rt-rk.com From: Aleksandar Markovic To: qemu-devel@nongnu.org Date: Thu, 22 Aug 2019 13:35:43 +0200 Message-Id: <1566473750-17743-20-git-send-email-aleksandar.markovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1566473750-17743-1-git-send-email-aleksandar.markovic@rt-rk.com> References: <1566473750-17743-1-git-send-email-aleksandar.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 89.216.37.149 Subject: [Qemu-devel] [PATCH 19/26] target/mips: Clean up handling of CP0 register 24 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: aurelien@aurel32.net, amarkovic@wavecomp.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Aleksandar Markovic Clean up handling of CP0 register 24. Signed-off-by: Aleksandar Markovic --- target/mips/translate.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/target/mips/translate.c b/target/mips/translate.c index 4272948..41392ab 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -7453,7 +7453,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int= reg, int sel) break; case CP0_REGISTER_24: switch (sel) { - case 0: + case CP0_REG24__DEPC: /* EJTAG support */ tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_DEPC)); tcg_gen_ext32s_tl(arg, arg); @@ -8215,7 +8215,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int= reg, int sel) break; case CP0_REGISTER_24: switch (sel) { - case 0: + case CP0_REG24__DEPC: /* EJTAG support */ tcg_gen_st_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_DEPC)); register_name =3D "DEPC"; @@ -8954,7 +8954,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, in= t reg, int sel) break; case CP0_REGISTER_24: switch (sel) { - case 0: + case CP0_REG24__DEPC: /* EJTAG support */ tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_DEPC)); register_name =3D "DEPC"; @@ -9697,7 +9697,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, in= t reg, int sel) break; case CP0_REGISTER_24: switch (sel) { - case 0: + case CP0_REG24__DEPC: /* EJTAG support */ tcg_gen_st_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_DEPC)); register_name =3D "DEPC"; --=20 2.7.4 From nobody Tue May 7 19:36:38 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1566475531; cv=none; d=zoho.com; s=zohoarc; b=SuncZ/paDCvP5neB/GLWB2XfRIvXzvQnLj+nA7YSKoH9Kl3AeMYyfnlZ/GZvXEwEeOuw3k3g0MCp7rnxnjlfXg2PPfq2Y+6uay7hs5ybMO4nwACDVY+NQF+zG1Elhz2FSvXTqio4k4raYEvet+OOqsWXv9QmC2PM9BQ+6VpUXhQ= ARC-Message-Signature: i=1; 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Thu, 22 Aug 2019 07:37:40 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1i0lPJ-00087Y-RH for qemu-devel@nongnu.org; Thu, 22 Aug 2019 07:37:37 -0400 Received: from mx2.rt-rk.com ([89.216.37.149]:48307 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1i0lPI-0007lQ-PF for qemu-devel@nongnu.org; Thu, 22 Aug 2019 07:37:33 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id 40B6D1A2107; Thu, 22 Aug 2019 13:35:59 +0200 (CEST) Received: from rtrkw774-lin.domain.local (rtrkw774-lin.domain.local [10.10.13.43]) by mail.rt-rk.com (Postfix) with ESMTPSA id EC5311A205C; Thu, 22 Aug 2019 13:35:58 +0200 (CEST) X-Virus-Scanned: amavisd-new at rt-rk.com From: Aleksandar Markovic To: qemu-devel@nongnu.org Date: Thu, 22 Aug 2019 13:35:44 +0200 Message-Id: <1566473750-17743-21-git-send-email-aleksandar.markovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1566473750-17743-1-git-send-email-aleksandar.markovic@rt-rk.com> References: <1566473750-17743-1-git-send-email-aleksandar.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 89.216.37.149 Subject: [Qemu-devel] [PATCH 20/26] target/mips: Clean up handling of CP0 register 25 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: aurelien@aurel32.net, amarkovic@wavecomp.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Aleksandar Markovic Clean up handling of CP0 register 25. Signed-off-by: Aleksandar Markovic --- target/mips/translate.c | 64 ++++++++++++++++++++++++---------------------= ---- 1 file changed, 32 insertions(+), 32 deletions(-) diff --git a/target/mips/translate.c b/target/mips/translate.c index 41392ab..55d1d95 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -7465,35 +7465,35 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, i= nt reg, int sel) break; case CP0_REGISTER_25: switch (sel) { - case 0: + case CP0_REG25__PERFCTL0: gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Performance0)); register_name =3D "Performance0"; break; - case 1: + case CP0_REG25__PERFCNT0: /* gen_helper_mfc0_performance1(arg); */ register_name =3D "Performance1"; goto cp0_unimplemented; - case 2: + case CP0_REG25__PERFCTL1: /* gen_helper_mfc0_performance2(arg); */ register_name =3D "Performance2"; goto cp0_unimplemented; - case 3: + case CP0_REG25__PERFCNT1: /* gen_helper_mfc0_performance3(arg); */ register_name =3D "Performance3"; goto cp0_unimplemented; - case 4: + case CP0_REG25__PERFCTL2: /* gen_helper_mfc0_performance4(arg); */ register_name =3D "Performance4"; goto cp0_unimplemented; - case 5: + case CP0_REG25__PERFCNT2: /* gen_helper_mfc0_performance5(arg); */ register_name =3D "Performance5"; goto cp0_unimplemented; - case 6: + case CP0_REG25__PERFCTL3: /* gen_helper_mfc0_performance6(arg); */ register_name =3D "Performance6"; goto cp0_unimplemented; - case 7: + case CP0_REG25__PERFCNT3: /* gen_helper_mfc0_performance7(arg); */ register_name =3D "Performance7"; goto cp0_unimplemented; @@ -8226,35 +8226,35 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, i= nt reg, int sel) break; case CP0_REGISTER_25: switch (sel) { - case 0: + case CP0_REG25__PERFCTL0: gen_helper_mtc0_performance0(cpu_env, arg); register_name =3D "Performance0"; break; - case 1: + case CP0_REG25__PERFCNT0: /* gen_helper_mtc0_performance1(arg); */ register_name =3D "Performance1"; goto cp0_unimplemented; - case 2: + case CP0_REG25__PERFCTL1: /* gen_helper_mtc0_performance2(arg); */ register_name =3D "Performance2"; goto cp0_unimplemented; - case 3: + case CP0_REG25__PERFCNT1: /* gen_helper_mtc0_performance3(arg); */ register_name =3D "Performance3"; goto cp0_unimplemented; - case 4: + case CP0_REG25__PERFCTL2: /* gen_helper_mtc0_performance4(arg); */ register_name =3D "Performance4"; goto cp0_unimplemented; - case 5: + case CP0_REG25__PERFCNT2: /* gen_helper_mtc0_performance5(arg); */ register_name =3D "Performance5"; goto cp0_unimplemented; - case 6: + case CP0_REG25__PERFCTL3: /* gen_helper_mtc0_performance6(arg); */ register_name =3D "Performance6"; goto cp0_unimplemented; - case 7: + case CP0_REG25__PERFCNT3: /* gen_helper_mtc0_performance7(arg); */ register_name =3D "Performance7"; goto cp0_unimplemented; @@ -8965,35 +8965,35 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, = int reg, int sel) break; case CP0_REGISTER_25: switch (sel) { - case 0: + case CP0_REG25__PERFCTL0: gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Performance0)); register_name =3D "Performance0"; break; - case 1: + case CP0_REG25__PERFCNT0: /* gen_helper_dmfc0_performance1(arg); */ register_name =3D "Performance1"; goto cp0_unimplemented; - case 2: + case CP0_REG25__PERFCTL1: /* gen_helper_dmfc0_performance2(arg); */ register_name =3D "Performance2"; goto cp0_unimplemented; - case 3: + case CP0_REG25__PERFCNT1: /* gen_helper_dmfc0_performance3(arg); */ register_name =3D "Performance3"; goto cp0_unimplemented; - case 4: + case CP0_REG25__PERFCTL2: /* gen_helper_dmfc0_performance4(arg); */ register_name =3D "Performance4"; goto cp0_unimplemented; - case 5: + case CP0_REG25__PERFCNT2: /* gen_helper_dmfc0_performance5(arg); */ register_name =3D "Performance5"; goto cp0_unimplemented; - case 6: + case CP0_REG25__PERFCTL3: /* gen_helper_dmfc0_performance6(arg); */ register_name =3D "Performance6"; goto cp0_unimplemented; - case 7: + case CP0_REG25__PERFCNT3: /* gen_helper_dmfc0_performance7(arg); */ register_name =3D "Performance7"; goto cp0_unimplemented; @@ -9708,35 +9708,35 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, = int reg, int sel) break; case CP0_REGISTER_25: switch (sel) { - case 0: + case CP0_REG25__PERFCTL0: gen_helper_mtc0_performance0(cpu_env, arg); register_name =3D "Performance0"; break; - case 1: + case CP0_REG25__PERFCNT0: /* gen_helper_mtc0_performance1(cpu_env, arg); */ register_name =3D "Performance1"; goto cp0_unimplemented; - case 2: + case CP0_REG25__PERFCTL1: /* gen_helper_mtc0_performance2(cpu_env, arg); */ register_name =3D "Performance2"; goto cp0_unimplemented; - case 3: + case CP0_REG25__PERFCNT1: /* gen_helper_mtc0_performance3(cpu_env, arg); */ register_name =3D "Performance3"; goto cp0_unimplemented; - case 4: + case CP0_REG25__PERFCTL2: /* gen_helper_mtc0_performance4(cpu_env, arg); */ register_name =3D "Performance4"; goto cp0_unimplemented; - case 5: + case CP0_REG25__PERFCNT2: /* gen_helper_mtc0_performance5(cpu_env, arg); */ register_name =3D "Performance5"; goto cp0_unimplemented; - case 6: + case CP0_REG25__PERFCTL3: /* gen_helper_mtc0_performance6(cpu_env, arg); */ register_name =3D "Performance6"; goto cp0_unimplemented; - case 7: + case CP0_REG25__PERFCNT3: /* gen_helper_mtc0_performance7(cpu_env, arg); */ register_name =3D "Performance7"; goto cp0_unimplemented; --=20 2.7.4 From nobody Tue May 7 19:36:38 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1566474976; cv=none; d=zoho.com; s=zohoarc; b=KGYB7QqqYN83TgY/V2nFfS3rthWsJkzfNQ7Iq7wsTNh8NSfpFskcht157P0AAftWt0iTOuqWx4HHaSj6yxV8O8MJJiCAvn4p31MdtIZFXZyHsFuv1v+n8AJu7f9U4lkVZPYspa0Qfnz1hpMhlzz7CMKOpuWba4sNQmL5xH5ddb0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1566474976; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; 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Thu, 22 Aug 2019 07:37:37 -0400 Received: from mx2.rt-rk.com ([89.216.37.149]:49969 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1i0lPJ-0007rA-3R for qemu-devel@nongnu.org; Thu, 22 Aug 2019 07:37:33 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id 4254B1A20C2; Thu, 22 Aug 2019 13:35:59 +0200 (CEST) Received: from rtrkw774-lin.domain.local (rtrkw774-lin.domain.local [10.10.13.43]) by mail.rt-rk.com (Postfix) with ESMTPSA id 090071A20D6; Thu, 22 Aug 2019 13:35:59 +0200 (CEST) X-Virus-Scanned: amavisd-new at rt-rk.com From: Aleksandar Markovic To: qemu-devel@nongnu.org Date: Thu, 22 Aug 2019 13:35:45 +0200 Message-Id: <1566473750-17743-22-git-send-email-aleksandar.markovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1566473750-17743-1-git-send-email-aleksandar.markovic@rt-rk.com> References: <1566473750-17743-1-git-send-email-aleksandar.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 89.216.37.149 Subject: [Qemu-devel] [PATCH 21/26] target/mips: Clean up handling of CP0 register 26 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: aurelien@aurel32.net, amarkovic@wavecomp.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Aleksandar Markovic Clean up handling of CP0 register 26. Signed-off-by: Aleksandar Markovic --- target/mips/cpu.h | 2 +- target/mips/translate.c | 8 ++++---- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/target/mips/cpu.h b/target/mips/cpu.h index c14afcd..80c896b 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -419,7 +419,7 @@ typedef struct mips_def_t mips_def_t; #define CP0_REG25__PERFCTL3 6 #define CP0_REG25__PERFCNT3 7 /* CP0 Register 26 */ -#define CP0_REG00__ERRCTL 0 +#define CP0_REG26__ERRCTL 0 /* CP0 Register 27 */ #define CP0_REG27__CACHERR 0 /* CP0 Register 28 */ diff --git a/target/mips/translate.c b/target/mips/translate.c index 55d1d95..f7e33f6 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -7503,7 +7503,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int= reg, int sel) break; case CP0_REGISTER_26: switch (sel) { - case 0: + case CP0_REG26__ERRCTL: gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_ErrCtl)); register_name =3D "ErrCtl"; break; @@ -8264,7 +8264,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int= reg, int sel) break; case CP0_REGISTER_26: switch (sel) { - case 0: + case CP0_REG26__ERRCTL: gen_helper_mtc0_errctl(cpu_env, arg); ctx->base.is_jmp =3D DISAS_STOP; register_name =3D "ErrCtl"; @@ -9003,7 +9003,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, in= t reg, int sel) break; case CP0_REGISTER_26: switch (sel) { - case 0: + case CP0_REG26__ERRCTL: gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_ErrCtl)); register_name =3D "ErrCtl"; break; @@ -9746,7 +9746,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, in= t reg, int sel) break; case CP0_REGISTER_26: switch (sel) { - case 0: + case CP0_REG26__ERRCTL: gen_helper_mtc0_errctl(cpu_env, arg); ctx->base.is_jmp =3D DISAS_STOP; register_name =3D "ErrCtl"; --=20 2.7.4 From nobody Tue May 7 19:36:38 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; 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Thu, 22 Aug 2019 13:35:59 +0200 (CEST) X-Virus-Scanned: amavisd-new at rt-rk.com From: Aleksandar Markovic To: qemu-devel@nongnu.org Date: Thu, 22 Aug 2019 13:35:46 +0200 Message-Id: <1566473750-17743-23-git-send-email-aleksandar.markovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1566473750-17743-1-git-send-email-aleksandar.markovic@rt-rk.com> References: <1566473750-17743-1-git-send-email-aleksandar.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 89.216.37.149 Subject: [Qemu-devel] [PATCH 22/26] target/mips: Clean up handling of CP0 register 27 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: aurelien@aurel32.net, amarkovic@wavecomp.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Aleksandar Markovic Clean up handling of CP0 register 27. Signed-off-by: Aleksandar Markovic --- target/mips/translate.c | 20 ++++---------------- 1 file changed, 4 insertions(+), 16 deletions(-) diff --git a/target/mips/translate.c b/target/mips/translate.c index f7e33f6..936c51c 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -7513,10 +7513,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, in= t reg, int sel) break; case CP0_REGISTER_27: switch (sel) { - case 0: - case 1: - case 2: - case 3: + case CP0_REG27__CACHERR: tcg_gen_movi_tl(arg, 0); /* unimplemented */ register_name =3D "CacheErr"; break; @@ -8275,10 +8272,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, in= t reg, int sel) break; case CP0_REGISTER_27: switch (sel) { - case 0: - case 1: - case 2: - case 3: + case CP0_REG27__CACHERR: /* ignored */ register_name =3D "CacheErr"; break; @@ -9014,10 +9008,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, i= nt reg, int sel) case CP0_REGISTER_27: switch (sel) { /* ignored */ - case 0: - case 1: - case 2: - case 3: + case CP0_REG27__CACHERR: tcg_gen_movi_tl(arg, 0); /* unimplemented */ register_name =3D "CacheErr"; break; @@ -9757,10 +9748,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, i= nt reg, int sel) break; case CP0_REGISTER_27: switch (sel) { - case 0: - case 1: - case 2: - case 3: + case CP0_REG27__CACHERR: /* ignored */ register_name =3D "CacheErr"; break; --=20 2.7.4 From nobody Tue May 7 19:36:38 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1566475661; cv=none; d=zoho.com; s=zohoarc; b=UVzuhRqHDbtxfYWfLnZbElnSY3fnY0SqoUoDl6iYbYd+ud2sJQpxwuUIMwwtL/dJx6SMyS2o0blmW/+tYdGN/njBwytUTE5+CSoWgBvksG+bYY/qDaJkFyoh1MmD3FNTIsYtWSXqoZR2tAOZugQX3gIb//qgKypmPwzVPMRmneI= ARC-Message-Signature: i=1; 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Thu, 22 Aug 2019 07:37:40 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1i0lPJ-00087d-QK for qemu-devel@nongnu.org; Thu, 22 Aug 2019 07:37:38 -0400 Received: from mx2.rt-rk.com ([89.216.37.149]:49986 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1i0lPI-0007sS-K3 for qemu-devel@nongnu.org; Thu, 22 Aug 2019 07:37:33 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id 5882D1A2077; Thu, 22 Aug 2019 13:35:59 +0200 (CEST) Received: from rtrkw774-lin.domain.local (rtrkw774-lin.domain.local [10.10.13.43]) by mail.rt-rk.com (Postfix) with ESMTPSA id 1C9A31A20CC; Thu, 22 Aug 2019 13:35:59 +0200 (CEST) X-Virus-Scanned: amavisd-new at rt-rk.com From: Aleksandar Markovic To: qemu-devel@nongnu.org Date: Thu, 22 Aug 2019 13:35:47 +0200 Message-Id: <1566473750-17743-24-git-send-email-aleksandar.markovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1566473750-17743-1-git-send-email-aleksandar.markovic@rt-rk.com> References: <1566473750-17743-1-git-send-email-aleksandar.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 89.216.37.149 Subject: [Qemu-devel] [PATCH 23/26] target/mips: Clean up handling of CP0 register 28 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: aurelien@aurel32.net, amarkovic@wavecomp.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Aleksandar Markovic Clean up handling of CP0 register 28. Signed-off-by: Aleksandar Markovic --- target/mips/cpu.h | 24 +++++++++++-------- target/mips/translate.c | 64 ++++++++++++++++++++++++---------------------= ---- 2 files changed, 46 insertions(+), 42 deletions(-) diff --git a/target/mips/cpu.h b/target/mips/cpu.h index 80c896b..55ada8c 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -235,12 +235,12 @@ typedef struct mips_def_t mips_def_t; * * 0 DataLo DataHi ErrorEPC DESAVE * 1 TagLo TagHi - * 2 DataLo DataHi KScratch - * 3 TagLo TagHi KScratch - * 4 DataLo DataHi KScratch - * 5 TagLo TagHi KScratch - * 6 DataLo DataHi KScratch - * 7 TagLo TagHi KScratch + * 2 DataLo1 DataHi KScratch + * 3 TagLo1 TagHi KScratch + * 4 DataLo2 DataHi KScratch + * 5 TagLo2 TagHi KScratch + * 6 DataLo3 DataHi KScratch + * 7 TagLo3 TagHi KScratch * */ #define CP0_REGISTER_00 0 @@ -423,10 +423,14 @@ typedef struct mips_def_t mips_def_t; /* CP0 Register 27 */ #define CP0_REG27__CACHERR 0 /* CP0 Register 28 */ -#define CP0_REG28__ITAGLO 0 -#define CP0_REG28__IDATALO 1 -#define CP0_REG28__DTAGLO 2 -#define CP0_REG28__DDATALO 3 +#define CP0_REG28__TAGLO 0 +#define CP0_REG28__DATALO 1 +#define CP0_REG28__TAGLO1 2 +#define CP0_REG28__DATALO1 3 +#define CP0_REG28__TAGLO2 4 +#define CP0_REG28__DATALO2 5 +#define CP0_REG28__TAGLO3 6 +#define CP0_REG28__DATALO3 7 /* CP0 Register 29 */ #define CP0_REG29__IDATAHI 1 #define CP0_REG29__DDATAHI 3 diff --git a/target/mips/translate.c b/target/mips/translate.c index 936c51c..6f5eed7 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -7523,10 +7523,10 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, i= nt reg, int sel) break; case CP0_REGISTER_28: switch (sel) { - case 0: - case 2: - case 4: - case 6: + case CP0_REG28__TAGLO: + case CP0_REG28__TAGLO1: + case CP0_REG28__TAGLO2: + case CP0_REG28__TAGLO3: { TCGv_i64 tmp =3D tcg_temp_new_i64(); tcg_gen_ld_i64(tmp, cpu_env, offsetof(CPUMIPSState, CP0_Ta= gLo)); @@ -7535,10 +7535,10 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, i= nt reg, int sel) } register_name =3D "TagLo"; break; - case 1: - case 3: - case 5: - case 7: + case CP0_REG28__DATALO: + case CP0_REG28__DATALO1: + case CP0_REG28__DATALO2: + case CP0_REG28__DATALO3: gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_DataLo)); register_name =3D "DataLo"; break; @@ -8282,17 +8282,17 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, i= nt reg, int sel) break; case CP0_REGISTER_28: switch (sel) { - case 0: - case 2: - case 4: - case 6: + case CP0_REG28__TAGLO: + case CP0_REG28__TAGLO1: + case CP0_REG28__TAGLO2: + case CP0_REG28__TAGLO3: gen_helper_mtc0_taglo(cpu_env, arg); register_name =3D "TagLo"; break; - case 1: - case 3: - case 5: - case 7: + case CP0_REG28__DATALO: + case CP0_REG28__DATALO1: + case CP0_REG28__DATALO2: + case CP0_REG28__DATALO3: gen_helper_mtc0_datalo(cpu_env, arg); register_name =3D "DataLo"; break; @@ -9018,17 +9018,17 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, = int reg, int sel) break; case CP0_REGISTER_28: switch (sel) { - case 0: - case 2: - case 4: - case 6: + case CP0_REG28__TAGLO: + case CP0_REG28__TAGLO1: + case CP0_REG28__TAGLO2: + case CP0_REG28__TAGLO3: gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_TagLo)); register_name =3D "TagLo"; break; - case 1: - case 3: - case 5: - case 7: + case CP0_REG28__DATALO: + case CP0_REG28__DATALO1: + case CP0_REG28__DATALO2: + case CP0_REG28__DATALO3: gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_DataLo)); register_name =3D "DataLo"; break; @@ -9758,17 +9758,17 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, = int reg, int sel) break; case CP0_REGISTER_28: switch (sel) { - case 0: - case 2: - case 4: - case 6: + case CP0_REG28__TAGLO: + case CP0_REG28__TAGLO1: + case CP0_REG28__TAGLO2: + case CP0_REG28__TAGLO3: gen_helper_mtc0_taglo(cpu_env, arg); register_name =3D "TagLo"; break; - case 1: - case 3: - case 5: - case 7: + case CP0_REG28__DATALO: + case CP0_REG28__DATALO1: + case CP0_REG28__DATALO2: + case CP0_REG28__DATALO3: gen_helper_mtc0_datalo(cpu_env, arg); register_name =3D "DataLo"; break; --=20 2.7.4 From nobody Tue May 7 19:36:38 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1566475456; cv=none; d=zoho.com; s=zohoarc; b=A1AyAOAKLP9GV+xDX3OOvgJVRHEFyYbxMqTqlPDzuLPqeKoHuzEV72mrwlEZd7tA6eUUNbzyFOja7wSosd3dCjwKcCND7UVPqHeF5ykwP799gSuWzqbzuV9+Tse2R61B0q2c+LQ63P5zO+7ymqY9vO99UfgnSsu3Owc9L2XVN8M= ARC-Message-Signature: i=1; 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Thu, 22 Aug 2019 07:37:40 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1i0lPJ-00087h-PE for qemu-devel@nongnu.org; Thu, 22 Aug 2019 07:37:37 -0400 Received: from mx2.rt-rk.com ([89.216.37.149]:49983 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1i0lPI-0007sP-Ow for qemu-devel@nongnu.org; Thu, 22 Aug 2019 07:37:33 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id 5EF761A20BE; Thu, 22 Aug 2019 13:35:59 +0200 (CEST) Received: from rtrkw774-lin.domain.local (rtrkw774-lin.domain.local [10.10.13.43]) by mail.rt-rk.com (Postfix) with ESMTPSA id 26C8F1A2044; Thu, 22 Aug 2019 13:35:59 +0200 (CEST) X-Virus-Scanned: amavisd-new at rt-rk.com From: Aleksandar Markovic To: qemu-devel@nongnu.org Date: Thu, 22 Aug 2019 13:35:48 +0200 Message-Id: <1566473750-17743-25-git-send-email-aleksandar.markovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1566473750-17743-1-git-send-email-aleksandar.markovic@rt-rk.com> References: <1566473750-17743-1-git-send-email-aleksandar.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 89.216.37.149 Subject: [Qemu-devel] [PATCH 24/26] target/mips: Clean up handling of CP0 register 29 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: aurelien@aurel32.net, amarkovic@wavecomp.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Aleksandar Markovic Clean up handling of CP0 register 29. Signed-off-by: Aleksandar Markovic --- target/mips/cpu.h | 22 ++++++++++------- target/mips/translate.c | 64 ++++++++++++++++++++++++---------------------= ---- 2 files changed, 46 insertions(+), 40 deletions(-) diff --git a/target/mips/cpu.h b/target/mips/cpu.h index 55ada8c..90d1373 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -235,12 +235,12 @@ typedef struct mips_def_t mips_def_t; * * 0 DataLo DataHi ErrorEPC DESAVE * 1 TagLo TagHi - * 2 DataLo1 DataHi KScratch - * 3 TagLo1 TagHi KScratch - * 4 DataLo2 DataHi KScratch - * 5 TagLo2 TagHi KScratch - * 6 DataLo3 DataHi KScratch - * 7 TagLo3 TagHi KScratch + * 2 DataLo1 DataHi1 KScratch + * 3 TagLo1 TagHi1 KScratch + * 4 DataLo2 DataHi2 KScratch + * 5 TagLo2 TagHi2 KScratch + * 6 DataLo3 DataHi3 KScratch + * 7 TagLo3 TagHi3 KScratch * */ #define CP0_REGISTER_00 0 @@ -432,8 +432,14 @@ typedef struct mips_def_t mips_def_t; #define CP0_REG28__TAGLO3 6 #define CP0_REG28__DATALO3 7 /* CP0 Register 29 */ -#define CP0_REG29__IDATAHI 1 -#define CP0_REG29__DDATAHI 3 +#define CP0_REG29__TAGHI 0 +#define CP0_REG29__DATAHI 1 +#define CP0_REG29__TAGHI1 2 +#define CP0_REG29__DATAHI1 3 +#define CP0_REG29__TAGHI2 4 +#define CP0_REG29__DATAHI2 5 +#define CP0_REG29__TAGHI3 6 +#define CP0_REG29__DATAHI3 7 /* CP0 Register 30 */ #define CP0_REG30__ERROREPC 0 /* CP0 Register 31 */ diff --git a/target/mips/translate.c b/target/mips/translate.c index 6f5eed7..95cb473 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -7548,17 +7548,17 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, i= nt reg, int sel) break; case CP0_REGISTER_29: switch (sel) { - case 0: - case 2: - case 4: - case 6: + case CP0_REG29__TAGHI: + case CP0_REG29__TAGHI1: + case CP0_REG29__TAGHI2: + case CP0_REG29__TAGHI3: gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_TagHi)); register_name =3D "TagHi"; break; - case 1: - case 3: - case 5: - case 7: + case CP0_REG29__DATAHI: + case CP0_REG29__DATAHI1: + case CP0_REG29__DATAHI2: + case CP0_REG29__DATAHI3: gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_DataHi)); register_name =3D "DataHi"; break; @@ -8302,17 +8302,17 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, i= nt reg, int sel) break; case CP0_REGISTER_29: switch (sel) { - case 0: - case 2: - case 4: - case 6: + case CP0_REG29__TAGHI: + case CP0_REG29__TAGHI1: + case CP0_REG29__TAGHI2: + case CP0_REG29__TAGHI3: gen_helper_mtc0_taghi(cpu_env, arg); register_name =3D "TagHi"; break; - case 1: - case 3: - case 5: - case 7: + case CP0_REG29__DATAHI: + case CP0_REG29__DATAHI1: + case CP0_REG29__DATAHI2: + case CP0_REG29__DATAHI3: gen_helper_mtc0_datahi(cpu_env, arg); register_name =3D "DataHi"; break; @@ -9038,17 +9038,17 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, = int reg, int sel) break; case CP0_REGISTER_29: switch (sel) { - case 0: - case 2: - case 4: - case 6: + case CP0_REG29__TAGHI: + case CP0_REG29__TAGHI1: + case CP0_REG29__TAGHI2: + case CP0_REG29__TAGHI3: gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_TagHi)); register_name =3D "TagHi"; break; - case 1: - case 3: - case 5: - case 7: + case CP0_REG29__DATAHI: + case CP0_REG29__DATAHI1: + case CP0_REG29__DATAHI2: + case CP0_REG29__DATAHI3: gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_DataHi)); register_name =3D "DataHi"; break; @@ -9778,17 +9778,17 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, = int reg, int sel) break; case CP0_REGISTER_29: switch (sel) { - case 0: - case 2: - case 4: - case 6: + case CP0_REG29__TAGHI: + case CP0_REG29__TAGHI1: + case CP0_REG29__TAGHI2: + case CP0_REG29__TAGHI3: gen_helper_mtc0_taghi(cpu_env, arg); register_name =3D "TagHi"; break; - case 1: - case 3: - case 5: - case 7: + case CP0_REG29__DATAHI: + case CP0_REG29__DATAHI1: + case CP0_REG29__DATAHI2: + case CP0_REG29__DATAHI3: gen_helper_mtc0_datahi(cpu_env, arg); register_name =3D "DataHi"; break; --=20 2.7.4 From nobody Tue May 7 19:36:38 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1566475496; cv=none; d=zoho.com; s=zohoarc; b=JWFLVQO9M3tAK2rK08tur3xmZ9sc+gIitttG/Z/NFAZhGSYQLK0KMh3LcERUGZJ4Jp0nylzMMb0i1mn9Oqqqb+qkBEPE03ILwoJOeaKKi7c9kJiUqhn3w1jjnMaBaZCPBuH+KtZ/CBp4u2O8IFDpilfh4J1NLYgmK88CkgPBJRM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; 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Thu, 22 Aug 2019 07:37:38 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1i0lPJ-000881-U8 for qemu-devel@nongnu.org; Thu, 22 Aug 2019 07:37:36 -0400 Received: from mx2.rt-rk.com ([89.216.37.149]:49984 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1i0lPJ-0007sQ-0s for qemu-devel@nongnu.org; Thu, 22 Aug 2019 07:37:33 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id 5FD741A20C1; Thu, 22 Aug 2019 13:35:59 +0200 (CEST) Received: from rtrkw774-lin.domain.local (rtrkw774-lin.domain.local [10.10.13.43]) by mail.rt-rk.com (Postfix) with ESMTPSA id 315AC1A20A9; Thu, 22 Aug 2019 13:35:59 +0200 (CEST) X-Virus-Scanned: amavisd-new at rt-rk.com From: Aleksandar Markovic To: qemu-devel@nongnu.org Date: Thu, 22 Aug 2019 13:35:49 +0200 Message-Id: <1566473750-17743-26-git-send-email-aleksandar.markovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1566473750-17743-1-git-send-email-aleksandar.markovic@rt-rk.com> References: <1566473750-17743-1-git-send-email-aleksandar.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 89.216.37.149 Subject: [Qemu-devel] [PATCH 25/26] target/mips: Clean up handling of CP0 register 30 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: aurelien@aurel32.net, amarkovic@wavecomp.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Aleksandar Markovic Clean up handling of CP0 register 30. Signed-off-by: Aleksandar Markovic --- target/mips/translate.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/target/mips/translate.c b/target/mips/translate.c index 95cb473..808d046 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -7568,7 +7568,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int= reg, int sel) break; case CP0_REGISTER_30: switch (sel) { - case 0: + case CP0_REG30__ERROREPC: tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_ErrorEP= C)); tcg_gen_ext32s_tl(arg, arg); register_name =3D "ErrorEPC"; @@ -8323,7 +8323,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int= reg, int sel) break; case CP0_REGISTER_30: switch (sel) { - case 0: + case CP0_REG30__ERROREPC: tcg_gen_st_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_ErrorEP= C)); register_name =3D "ErrorEPC"; break; @@ -9058,7 +9058,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, in= t reg, int sel) break; case CP0_REGISTER_30: switch (sel) { - case 0: + case CP0_REG30__ERROREPC: tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_ErrorEP= C)); register_name =3D "ErrorEPC"; break; @@ -9799,7 +9799,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, in= t reg, int sel) break; case CP0_REGISTER_30: switch (sel) { - case 0: + case CP0_REG30__ERROREPC: tcg_gen_st_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_ErrorEP= C)); register_name =3D "ErrorEPC"; break; --=20 2.7.4 From nobody Tue May 7 19:36:38 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1566475175; cv=none; d=zoho.com; s=zohoarc; b=hNRDgwqtiNh1bKDZUVOg4wuLtnGGl5Aeo6VjG6dTD9NM0DRx+mhDIXYWAv7YOM7Ep2yRJKeqwF1e9aVazoRhjBDyzXbi4mS6YeYVQyEo5mAFjiZg+Q5E6ltFZczIAdQkQhUbaUVZ2Hz4SvTRzgM6wmsAh+4OpOJAwc3wlcXjAso= ARC-Message-Signature: i=1; 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Thu, 22 Aug 2019 07:37:40 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1i0lPK-00088G-15 for qemu-devel@nongnu.org; Thu, 22 Aug 2019 07:37:37 -0400 Received: from mx2.rt-rk.com ([89.216.37.149]:49985 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1i0lPJ-0007sR-93 for qemu-devel@nongnu.org; Thu, 22 Aug 2019 07:37:33 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id 663581A20D6; Thu, 22 Aug 2019 13:35:59 +0200 (CEST) Received: from rtrkw774-lin.domain.local (rtrkw774-lin.domain.local [10.10.13.43]) by mail.rt-rk.com (Postfix) with ESMTPSA id 39A0C1A20C8; Thu, 22 Aug 2019 13:35:59 +0200 (CEST) X-Virus-Scanned: amavisd-new at rt-rk.com From: Aleksandar Markovic To: qemu-devel@nongnu.org Date: Thu, 22 Aug 2019 13:35:50 +0200 Message-Id: <1566473750-17743-27-git-send-email-aleksandar.markovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1566473750-17743-1-git-send-email-aleksandar.markovic@rt-rk.com> References: <1566473750-17743-1-git-send-email-aleksandar.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 89.216.37.149 Subject: [Qemu-devel] [PATCH 26/26] target/mips: Clean up handling of CP0 register 31 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: aurelien@aurel32.net, amarkovic@wavecomp.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Aleksandar Markovic Clean up handling of CP0 register 31. Signed-off-by: Aleksandar Markovic --- target/mips/cpu.h | 2 +- target/mips/translate.c | 56 ++++++++++++++++++++++++---------------------= ---- 2 files changed, 29 insertions(+), 29 deletions(-) diff --git a/target/mips/cpu.h b/target/mips/cpu.h index 90d1373..070f5ea 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -610,7 +610,6 @@ struct CPUMIPSState { * CP0 Register 4 */ target_ulong CP0_Context; - target_ulong CP0_KScratch[MIPS_KSCRATCH_NUM]; int32_t CP0_MemoryMapID; /* * CP0 Register 5 @@ -1021,6 +1020,7 @@ struct CPUMIPSState { * CP0 Register 31 */ int32_t CP0_DESAVE; + target_ulong CP0_KScratch[MIPS_KSCRATCH_NUM]; =20 /* We waste some space so we can handle shadow registers like TCs. */ TCState tcs[MIPS_SHADOW_SET_MAX]; diff --git a/target/mips/translate.c b/target/mips/translate.c index 808d046..ba4e28e 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -7579,17 +7579,17 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, i= nt reg, int sel) break; case CP0_REGISTER_31: switch (sel) { - case 0: + case CP0_REG31__DESAVE: /* EJTAG support */ gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_DESAVE)); register_name =3D "DESAVE"; break; - case 2: - case 3: - case 4: - case 5: - case 6: - case 7: + case CP0_REG31__KSCRATCH1: + case CP0_REG31__KSCRATCH2: + case CP0_REG31__KSCRATCH3: + case CP0_REG31__KSCRATCH4: + case CP0_REG31__KSCRATCH5: + case CP0_REG31__KSCRATCH6: CP0_CHECK(ctx->kscrexist & (1 << sel)); tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_KScratch[sel-2])); @@ -8333,17 +8333,17 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, i= nt reg, int sel) break; case CP0_REGISTER_31: switch (sel) { - case 0: + case CP0_REG31__DESAVE: /* EJTAG support */ gen_mtc0_store32(arg, offsetof(CPUMIPSState, CP0_DESAVE)); register_name =3D "DESAVE"; break; - case 2: - case 3: - case 4: - case 5: - case 6: - case 7: + case CP0_REG31__KSCRATCH1: + case CP0_REG31__KSCRATCH2: + case CP0_REG31__KSCRATCH3: + case CP0_REG31__KSCRATCH4: + case CP0_REG31__KSCRATCH5: + case CP0_REG31__KSCRATCH6: CP0_CHECK(ctx->kscrexist & (1 << sel)); tcg_gen_st_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_KScratch[sel-2])); @@ -9068,17 +9068,17 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, = int reg, int sel) break; case CP0_REGISTER_31: switch (sel) { - case 0: + case CP0_REG31__DESAVE: /* EJTAG support */ gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_DESAVE)); register_name =3D "DESAVE"; break; - case 2: - case 3: - case 4: - case 5: - case 6: - case 7: + case CP0_REG31__KSCRATCH1: + case CP0_REG31__KSCRATCH2: + case CP0_REG31__KSCRATCH3: + case CP0_REG31__KSCRATCH4: + case CP0_REG31__KSCRATCH5: + case CP0_REG31__KSCRATCH6: CP0_CHECK(ctx->kscrexist & (1 << sel)); tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_KScratch[sel-2])); @@ -9809,17 +9809,17 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, = int reg, int sel) break; case CP0_REGISTER_31: switch (sel) { - case 0: + case CP0_REG31__DESAVE: /* EJTAG support */ gen_mtc0_store32(arg, offsetof(CPUMIPSState, CP0_DESAVE)); register_name =3D "DESAVE"; break; - case 2: - case 3: - case 4: - case 5: - case 6: - case 7: + case CP0_REG31__KSCRATCH1: + case CP0_REG31__KSCRATCH2: + case CP0_REG31__KSCRATCH3: + case CP0_REG31__KSCRATCH4: + case CP0_REG31__KSCRATCH5: + case CP0_REG31__KSCRATCH6: CP0_CHECK(ctx->kscrexist & (1 << sel)); tcg_gen_st_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_KScratch[sel - 2])); --=20 2.7.4