From nobody Tue Nov 11 22:52:44 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1566283386; cv=none; d=zoho.com; s=zohoarc; b=fRqLijsLiwaqwuHqNUgQeY76bV/3ZXSjjsoK+mD53Vy5wPWjwcLji0Y/kHc4naa2zmFCX0uYQNNehb0cHzy/frdEsF2gdMsiF519I9ffGYqCZgmwDea1DDqx5lRleqJeIUYv9yUQw7vtCGZMqmN3osUWuX7LVf1naWnBV6Mf+3E= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1566283386; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=2rAEgE+gMakSwPICH6V1VOLUAEtBOqrJKskF/cw3rls=; b=Z5+fgZlG2uddj+MqDpRDdYV6yCYOoqy8iKO3g5eQoN5DwK2tPXwaIkrwID+2DmyM9pw+zMFnzb9Lsc6lc8qdQI/SlfbUQsG38UfIxP6J6j8EMZLDVnFwmR6P4HT8JgC8nbI3T9ku7D4gkaAAyiOZXhKFVWkcF4g3Fr5Ak6ahEUA= ARC-Authentication-Results: i=1; mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1566283386546568.8258516549886; Mon, 19 Aug 2019 23:43:06 -0700 (PDT) Received: from localhost ([::1]:33402 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1hzxrA-0002MD-Hc for importer@patchew.org; Tue, 20 Aug 2019 02:43:00 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:40017) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1hzxmh-0004rS-O6 for qemu-devel@nongnu.org; Tue, 20 Aug 2019 02:38:26 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hzxme-0006c5-Sg for qemu-devel@nongnu.org; Tue, 20 Aug 2019 02:38:23 -0400 Received: from mx2.rt-rk.com ([89.216.37.149]:39312 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1hzxme-0006W2-Dp for qemu-devel@nongnu.org; Tue, 20 Aug 2019 02:38:20 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id CEFBA1A0F20; Tue, 20 Aug 2019 08:38:15 +0200 (CEST) Received: from rtrkw774-lin.domain.local (rtrkw774-lin.domain.local [10.10.13.43]) by mail.rt-rk.com (Postfix) with ESMTPSA id 8A1691A200C; Tue, 20 Aug 2019 08:38:15 +0200 (CEST) X-Virus-Scanned: amavisd-new at rt-rk.com From: Aleksandar Markovic To: qemu-devel@nongnu.org Date: Tue, 20 Aug 2019 08:38:00 +0200 Message-Id: <1566283083-21838-9-git-send-email-aleksandar.markovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1566283083-21838-1-git-send-email-aleksandar.markovic@rt-rk.com> References: <1566283083-21838-1-git-send-email-aleksandar.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 89.216.37.149 Subject: [Qemu-devel] [PULL 08/11] target/mips: Style improvements in mips_malta.c X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, amarkovic@wavecomp.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Aleksandar Markovic Fixes mostly errors and warnings reported by 'checkpatch.pl -f'. Signed-off-by: Aleksandar Markovic Reviewed-by: Aleksandar Rikalo Message-Id: <1566216496-17375-16-git-send-email-aleksandar.markovic@rt-rk.c= om> --- hw/mips/mips_malta.c | 216 ++++++++++++++++++++++++++++++-----------------= ---- 1 file changed, 128 insertions(+), 88 deletions(-) diff --git a/hw/mips/mips_malta.c b/hw/mips/mips_malta.c index 9fec2b0..4d9c64b 100644 --- a/hw/mips/mips_malta.c +++ b/hw/mips/mips_malta.c @@ -60,18 +60,18 @@ #include "hw/semihosting/semihost.h" #include "hw/mips/cps.h" =20 -#define ENVP_ADDR 0x80002000l -#define ENVP_NB_ENTRIES 16 -#define ENVP_ENTRY_SIZE 256 +#define ENVP_ADDR 0x80002000l +#define ENVP_NB_ENTRIES 16 +#define ENVP_ENTRY_SIZE 256 =20 /* Hardware addresses */ -#define FLASH_ADDRESS 0x1e000000ULL -#define FPGA_ADDRESS 0x1f000000ULL -#define RESET_ADDRESS 0x1fc00000ULL +#define FLASH_ADDRESS 0x1e000000ULL +#define FPGA_ADDRESS 0x1f000000ULL +#define RESET_ADDRESS 0x1fc00000ULL =20 -#define FLASH_SIZE 0x400000 +#define FLASH_SIZE 0x400000 =20 -#define MAX_IDE_BUS 2 +#define MAX_IDE_BUS 2 =20 typedef struct { MemoryRegion iomem; @@ -117,10 +117,11 @@ static void malta_fpga_update_display(void *opaque) MaltaFPGAState *s =3D opaque; =20 for (i =3D 7 ; i >=3D 0 ; i--) { - if (s->leds & (1 << i)) + if (s->leds & (1 << i)) { leds_text[i] =3D '#'; - else + } else { leds_text[i] =3D ' '; + } } leds_text[8] =3D '\0'; =20 @@ -140,8 +141,6 @@ static void malta_fpga_update_display(void *opaque) * Typical device names include Microchip 24C02SC or SGS Thomson ST24C02. */ =20 -//~ #define DEBUG - #if defined(DEBUG) # define logout(fmt, ...) fprintf(stderr, "MALTA\t%-24s" fmt, __func__, #= # __VA_ARGS__) #else @@ -156,7 +155,7 @@ struct _eeprom24c0x_t { uint8_t scl; uint8_t sda; uint8_t data; - //~ uint16_t size; + /* uint16_t size; */ uint8_t contents[256]; }; =20 @@ -164,22 +163,38 @@ typedef struct _eeprom24c0x_t eeprom24c0x_t; =20 static eeprom24c0x_t spd_eeprom =3D { .contents =3D { - /* 00000000: */ 0x80,0x08,0xFF,0x0D,0x0A,0xFF,0x40,0x00, - /* 00000008: */ 0x01,0x75,0x54,0x00,0x82,0x08,0x00,0x01, - /* 00000010: */ 0x8F,0x04,0x02,0x01,0x01,0x00,0x00,0x00, - /* 00000018: */ 0x00,0x00,0x00,0x14,0x0F,0x14,0x2D,0xFF, - /* 00000020: */ 0x15,0x08,0x15,0x08,0x00,0x00,0x00,0x00, - /* 00000028: */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - /* 00000030: */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - /* 00000038: */ 0x00,0x00,0x00,0x00,0x00,0x00,0x12,0xD0, - /* 00000040: */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - /* 00000048: */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - /* 00000050: */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - /* 00000058: */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - /* 00000060: */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - /* 00000068: */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - /* 00000070: */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - /* 00000078: */ 0x00,0x00,0x00,0x00,0x00,0x00,0x64,0xF4, + /* 00000000: */ + 0x80, 0x08, 0xFF, 0x0D, 0x0A, 0xFF, 0x40, 0x00, + /* 00000008: */ + 0x01, 0x75, 0x54, 0x00, 0x82, 0x08, 0x00, 0x01, + /* 00000010: */ + 0x8F, 0x04, 0x02, 0x01, 0x01, 0x00, 0x00, 0x00, + /* 00000018: */ + 0x00, 0x00, 0x00, 0x14, 0x0F, 0x14, 0x2D, 0xFF, + /* 00000020: */ + 0x15, 0x08, 0x15, 0x08, 0x00, 0x00, 0x00, 0x00, + /* 00000028: */ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + /* 00000030: */ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + /* 00000038: */ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x12, 0xD0, + /* 00000040: */ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + /* 00000048: */ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + /* 00000050: */ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + /* 00000058: */ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + /* 00000060: */ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + /* 00000068: */ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + /* 00000070: */ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + /* 00000078: */ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x64, 0xF4, }, }; =20 @@ -349,7 +364,8 @@ static uint64_t malta_fpga_read(void *opaque, hwaddr ad= dr, =20 /* SWITCH Register */ case 0x00200: - val =3D 0x00000000; /* All switches closed */ + /* ori a3, a3, low(ram_low_size) */ + val =3D 0x00000000; break; =20 /* STATUS Register */ @@ -388,10 +404,11 @@ static uint64_t malta_fpga_read(void *opaque, hwaddr = addr, /* GPINP Register */ case 0x00a08: /* IN =3D OUT until a real I2C control is implemented */ - if (s->i2csel) + if (s->i2csel) { val =3D s->i2cout; - else + } else { val =3D 0x00; + } break; =20 /* I2CINP Register */ @@ -416,8 +433,8 @@ static uint64_t malta_fpga_read(void *opaque, hwaddr ad= dr, =20 default: #if 0 - printf ("malta_fpga_read: Bad register offset 0x" TARGET_FMT_lx "\= n", - addr); + printf("malta_fpga_read: Bad register offset 0x" TARGET_FMT_lx "\n= ", + addr); #endif break; } @@ -469,8 +486,9 @@ static void malta_fpga_write(void *opaque, hwaddr addr, =20 /* SOFTRES Register */ case 0x00500: - if (val =3D=3D 0x42) + if (val =3D=3D 0x42) { qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); + } break; =20 /* BRKRES Register */ @@ -503,8 +521,8 @@ static void malta_fpga_write(void *opaque, hwaddr addr, =20 default: #if 0 - printf ("malta_fpga_write: Bad register offset 0x" TARGET_FMT_lx "= \n", - addr); + printf("malta_fpga_write: Bad register offset 0x" TARGET_FMT_lx "\= n", + addr); #endif break; } @@ -563,7 +581,7 @@ static MaltaFPGAState *malta_fpga_init(MemoryRegion *ad= dress_space, memory_region_init_alias(&s->iomem_lo, NULL, "malta-fpga", &s->iomem, 0, 0x900); memory_region_init_alias(&s->iomem_hi, NULL, "malta-fpga", - &s->iomem, 0xa00, 0x10000-0xa00); + &s->iomem, 0xa00, 0x10000 - 0xa00); =20 memory_region_add_subregion(address_space, base, &s->iomem_lo); memory_region_add_subregion(address_space, base + 0xa00, &s->iomem_hi); @@ -587,7 +605,7 @@ static void network_init(PCIBus *pci_bus) { int i; =20 - for(i =3D 0; i < nb_nics; i++) { + for (i =3D 0; i < nb_nics; i++) { NICInfo *nd =3D &nd_table[i]; const char *default_devaddr =3D NULL; =20 @@ -801,27 +819,28 @@ static void write_bootloader_nanomips(uint8_t *base, = int64_t run_addr, /* jalrc t8 */ } =20 -/* ROM and pseudo bootloader - - The following code implements a very very simple bootloader. It first - loads the registers a0 to a3 to the values expected by the OS, and - then jump at the kernel address. - - The bootloader should pass the locations of the kernel arguments and - environment variables tables. Those tables contain the 32-bit address - of NULL terminated strings. The environment variables table should be - terminated by a NULL address. - - For a simpler implementation, the number of kernel arguments is fixed - to two (the name of the kernel and the command line), and the two - tables are actually the same one. - - The registers a0 to a3 should contain the following values: - a0 - number of kernel arguments - a1 - 32-bit address of the kernel arguments table - a2 - 32-bit address of the environment variables table - a3 - RAM size in bytes -*/ +/* + * ROM and pseudo bootloader + * + * The following code implements a very very simple bootloader. It first + * loads the registers a0 to a3 to the values expected by the OS, and + * then jump at the kernel address. + * + * The bootloader should pass the locations of the kernel arguments and + * environment variables tables. Those tables contain the 32-bit address + * of NULL terminated strings. The environment variables table should be + * terminated by a NULL address. + * + * For a simpler implementation, the number of kernel arguments is fixed + * to two (the name of the kernel and the command line), and the two + * tables are actually the same one. + * + * The registers a0 to a3 should contain the following values: + * a0 - number of kernel arguments + * a1 - 32-bit address of the kernel arguments table + * a2 - 32-bit address of the environment variables table + * a3 - RAM size in bytes + */ static void write_bootloader(uint8_t *base, int64_t run_addr, int64_t kernel_entry) { @@ -859,14 +878,23 @@ static void write_bootloader(uint8_t *base, int64_t r= un_addr, } else { stl_p(p++, 0x24040002); /* addiu a0, zero,= 2 */ } - stl_p(p++, 0x3c1d0000 | (((ENVP_ADDR - 64) >> 16) & 0xffff)); /* lui s= p, high(ENVP_ADDR) */ - stl_p(p++, 0x37bd0000 | ((ENVP_ADDR - 64) & 0xffff)); /* ori sp= , sp, low(ENVP_ADDR) */ - stl_p(p++, 0x3c050000 | ((ENVP_ADDR >> 16) & 0xffff)); /* lui a1= , high(ENVP_ADDR) */ - stl_p(p++, 0x34a50000 | (ENVP_ADDR & 0xffff)); /* ori a1= , a1, low(ENVP_ADDR) */ - stl_p(p++, 0x3c060000 | (((ENVP_ADDR + 8) >> 16) & 0xffff)); /* lui a2= , high(ENVP_ADDR + 8) */ - stl_p(p++, 0x34c60000 | ((ENVP_ADDR + 8) & 0xffff)); /* ori a2= , a2, low(ENVP_ADDR + 8) */ - stl_p(p++, 0x3c070000 | (loaderparams.ram_low_size >> 16)); /* lui= a3, high(ram_low_size) */ - stl_p(p++, 0x34e70000 | (loaderparams.ram_low_size & 0xffff)); /* ori= a3, a3, low(ram_low_size) */ + + /* lui sp, high(ENVP_ADDR) */ + stl_p(p++, 0x3c1d0000 | (((ENVP_ADDR - 64) >> 16) & 0xffff)); + /* ori sp, sp, low(ENVP_ADDR) */ + stl_p(p++, 0x37bd0000 | ((ENVP_ADDR - 64) & 0xffff)); + /* lui a1, high(ENVP_ADDR) */ + stl_p(p++, 0x3c050000 | ((ENVP_ADDR >> 16) & 0xffff)); + /* ori a1, a1, low(ENVP_ADDR) */ + stl_p(p++, 0x34a50000 | (ENVP_ADDR & 0xffff)); + /* lui a2, high(ENVP_ADDR + 8) */ + stl_p(p++, 0x3c060000 | (((ENVP_ADDR + 8) >> 16) & 0xffff)); + /* ori a2, a2, low(ENVP_ADDR + 8) */ + stl_p(p++, 0x34c60000 | ((ENVP_ADDR + 8) & 0xffff)); + /* lui a3, high(ram_low_size) */ + stl_p(p++, 0x3c070000 | (loaderparams.ram_low_size >> 16)); + /* ori a3, a3, low(ram_low_size) */ + stl_p(p++, 0x34e70000 | (loaderparams.ram_low_size & 0xffff)); =20 /* Load BAR registers as done by YAMON */ stl_p(p++, 0x3c09b400); /* lui t1= , 0xb400 */ @@ -970,14 +998,15 @@ static void write_bootloader(uint8_t *base, int64_t r= un_addr, =20 } =20 -static void GCC_FMT_ATTR(3, 4) prom_set(uint32_t* prom_buf, int index, +static void GCC_FMT_ATTR(3, 4) prom_set(uint32_t *prom_buf, int index, const char *string, ...) { va_list ap; int32_t table_addr; =20 - if (index >=3D ENVP_NB_ENTRIES) + if (index >=3D ENVP_NB_ENTRIES) { return; + } =20 if (string =3D=3D NULL) { prom_buf[index] =3D 0; @@ -993,7 +1022,7 @@ static void GCC_FMT_ATTR(3, 4) prom_set(uint32_t* prom= _buf, int index, } =20 /* Kernel */ -static int64_t load_kernel (void) +static int64_t load_kernel(void) { int64_t kernel_entry, kernel_high, initrd_size; long kernel_size; @@ -1041,11 +1070,13 @@ static int64_t load_kernel (void) initrd_size =3D 0; initrd_offset =3D 0; if (loaderparams.initrd_filename) { - initrd_size =3D get_image_size (loaderparams.initrd_filename); + initrd_size =3D get_image_size(loaderparams.initrd_filename); if (initrd_size > 0) { - /* The kernel allocates the bootmap memory in the low memory a= fter - the initrd. It takes at most 128kiB for 2GB RAM and 4kiB - pages. */ + /* + * The kernel allocates the bootmap memory in the low memory a= fter + * the initrd. It takes at most 128kiB for 2GB RAM and 4kiB + * pages. + */ initrd_offset =3D (loaderparams.ram_low_size - initrd_size - (128 * KiB) - ~INITRD_PAGE_MASK) & INITRD_PAGE_MASK; @@ -1071,9 +1102,10 @@ static int64_t load_kernel (void) =20 prom_set(prom_buf, prom_index++, "%s", loaderparams.kernel_filename); if (initrd_size > 0) { - prom_set(prom_buf, prom_index++, "rd_start=3D0x%" PRIx64 " rd_size= =3D%" PRId64 " %s", - xlate_to_kseg0(NULL, initrd_offset), initrd_size, - loaderparams.kernel_cmdline); + prom_set(prom_buf, prom_index++, + "rd_start=3D0x%" PRIx64 " rd_size=3D%" PRId64 " %s", + xlate_to_kseg0(NULL, initrd_offset), + initrd_size, loaderparams.kernel_cmdline); } else { prom_set(prom_buf, prom_index++, "%s", loaderparams.kernel_cmdline= ); } @@ -1113,9 +1145,11 @@ static void main_cpu_reset(void *opaque) =20 cpu_reset(CPU(cpu)); =20 - /* The bootloader does not need to be rewritten as it is located in a - read only location. The kernel location and the arguments table - location does not change. */ + /* + * The bootloader does not need to be rewritten as it is located in a + * read only location. The kernel location and the arguments table + * location does not change. + */ if (loaderparams.kernel_filename) { env->CP0_Status &=3D ~(1 << CP0St_ERL); } @@ -1213,9 +1247,11 @@ void mips_malta_init(MachineState *machine) DeviceState *dev =3D qdev_create(NULL, TYPE_MIPS_MALTA); MaltaState *s =3D MIPS_MALTA(dev); =20 - /* The whole address space decoded by the GT-64120A doesn't generate - exception when accessing invalid memory. Create an empty slot to - emulate this feature. */ + /* + * The whole address space decoded by the GT-64120A doesn't generate + * exception when accessing invalid memory. Create an empty slot to + * emulate this feature.\ + */ empty_slot_init(0, 0x20000000); =20 qdev_init_nofail(dev); @@ -1331,8 +1367,10 @@ void mips_malta_init(MachineState *machine) exit(1); } } - /* In little endian mode the 32bit words in the bios are swapped, - a neat trick which allows bi-endian firmware. */ + /* + * In little endian mode the 32bit words in the bios are swapped, + * a neat trick which allows bi-endian firmware. + */ #ifndef TARGET_WORDS_BIGENDIAN { uint32_t *end, *addr; @@ -1386,8 +1424,10 @@ void mips_malta_init(MachineState *machine) =20 piix4_devfn =3D piix4_init(pci_bus, &isa_bus, 80); =20 - /* Interrupt controller */ - /* The 8259 is attached to the MIPS CPU INT0 pin, ie interrupt 2 */ + /* + * Interrupt controller + * The 8259 is attached to the MIPS CPU INT0 pin, ie interrupt 2 + */ s->i8259 =3D i8259_init(isa_bus, i8259_irq); =20 isa_bus_irqs(isa_bus, s->i8259); --=20 2.7.4