From nobody Tue Feb 10 09:40:45 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1566217128; cv=none; d=zoho.com; s=zohoarc; b=mKtlfwCwbPS3S5uv4LiyXWjOX4aJGo1ohPbAGgS+OpbgYetV8cPASmeLZqZdPKJFyL+N6EoWyd5tFKZ6syLYllolr9oUOsh6idLs6lfTM+xjBjp0R7DplKK5CQm6uoX7N9Hls3yoiN5AdSKmpwXLjugGUL0M3BxlDfxoZfILgi0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1566217128; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=dhjrbTFvZJQbI4Fy0GdnuKKQrdBZtteTXW41Yf4bUq4=; b=h/l9MiW75t657ViIPzJSwIXTqSpkmsjCTB65d1kUT2xbQi5MAMumnKHrrFYN7ymTTnWLVLsDBxPXA0rmXT3jQe+yrPAu0FKpG1oZLt15qi8zHDfJx/g1n4ahWwAIsYEP/W8KO9UC2qKAV38BV1fjDFG1FHjSd24Ygpthton1SPs= ARC-Authentication-Results: i=1; mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1566217128309745.0269227621002; Mon, 19 Aug 2019 05:18:48 -0700 (PDT) Received: from localhost ([::1]:49098 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1hzgcY-0003XF-Sf for importer@patchew.org; Mon, 19 Aug 2019 08:18:46 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:36332) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1hzgTp-0002Ay-Fq for qemu-devel@nongnu.org; Mon, 19 Aug 2019 08:09:46 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hzgTm-0002lX-Oa for qemu-devel@nongnu.org; Mon, 19 Aug 2019 08:09:45 -0400 Received: from mx2.rt-rk.com ([89.216.37.149]:58066 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1hzgTm-0002bq-8i for qemu-devel@nongnu.org; Mon, 19 Aug 2019 08:09:42 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id CD1961A21E3; Mon, 19 Aug 2019 14:08:25 +0200 (CEST) Received: from rtrkw774-lin.domain.local (rtrkw774-lin.domain.local [10.10.13.43]) by mail.rt-rk.com (Postfix) with ESMTPSA id 0298C1A21CB; Mon, 19 Aug 2019 14:08:25 +0200 (CEST) X-Virus-Scanned: amavisd-new at rt-rk.com From: Aleksandar Markovic To: qemu-devel@nongnu.org Date: Mon, 19 Aug 2019 14:08:08 +0200 Message-Id: <1566216496-17375-30-git-send-email-aleksandar.markovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1566216496-17375-1-git-send-email-aleksandar.markovic@rt-rk.com> References: <1566216496-17375-1-git-send-email-aleksandar.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 89.216.37.149 Subject: [Qemu-devel] [PATCH v8 29/37] target/mips: Clean up handling of CP0 register 17 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: arikalo@wavecomp.com, philmd@redhat.com, amarkovic@wavecomp.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Aleksandar Markovic Clean up handling of CP0 register 17. Signed-off-by: Aleksandar Markovic --- target/mips/translate.c | 32 ++++++++++++++++---------------- 1 file changed, 16 insertions(+), 16 deletions(-) diff --git a/target/mips/translate.c b/target/mips/translate.c index 729b84d..ed6d567 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -6671,12 +6671,12 @@ static void gen_mfhc0(DisasContext *ctx, TCGv arg, = int reg, int sel) break; case CP0_REGISTER_17: switch (sel) { - case 0: + case CP0_REG17__LLADDR: gen_mfhc0_load64(arg, offsetof(CPUMIPSState, CP0_LLAddr), ctx->CP0_LLAddr_shift); register_name =3D "LLAddr"; break; - case 1: + case CP0_REG17__MAAR: CP0_CHECK(ctx->mrp); gen_helper_mfhc0_maar(arg, cpu_env); register_name =3D "MAAR"; @@ -6772,7 +6772,7 @@ static void gen_mthc0(DisasContext *ctx, TCGv arg, in= t reg, int sel) break; case CP0_REGISTER_17: switch (sel) { - case 0: + case CP0_REG17__LLADDR: /* * LLAddr is read-only (the only exception is bit 0 if LLB is * supported); the CP0_LLAddr_rw_bitmask does not seem to be @@ -6781,7 +6781,7 @@ static void gen_mthc0(DisasContext *ctx, TCGv arg, in= t reg, int sel) */ register_name =3D "LLAddr"; break; - case 1: + case CP0_REG17__MAAR: CP0_CHECK(ctx->mrp); gen_helper_mthc0_maar(cpu_env, arg); register_name =3D "MAAR"; @@ -7332,16 +7332,16 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, i= nt reg, int sel) break; case CP0_REGISTER_17: switch (sel) { - case 0: + case CP0_REG17__LLADDR: gen_helper_mfc0_lladdr(arg, cpu_env); register_name =3D "LLAddr"; break; - case 1: + case CP0_REG17__MAAR: CP0_CHECK(ctx->mrp); gen_helper_mfc0_maar(arg, cpu_env); register_name =3D "MAAR"; break; - case 2: + case CP0_REG17__MAARI: CP0_CHECK(ctx->mrp); gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_MAARI)); register_name =3D "MAARI"; @@ -8071,16 +8071,16 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, i= nt reg, int sel) break; case CP0_REGISTER_17: switch (sel) { - case 0: + case CP0_REG17__LLADDR: gen_helper_mtc0_lladdr(cpu_env, arg); register_name =3D "LLAddr"; break; - case 1: + case CP0_REG17__MAAR: CP0_CHECK(ctx->mrp); gen_helper_mtc0_maar(cpu_env, arg); register_name =3D "MAAR"; break; - case 2: + case CP0_REG17__MAARI: CP0_CHECK(ctx->mrp); gen_helper_mtc0_maari(cpu_env, arg); register_name =3D "MAARI"; @@ -8816,16 +8816,16 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, = int reg, int sel) break; case CP0_REGISTER_17: switch (sel) { - case 0: + case CP0_REG17__LLADDR: gen_helper_dmfc0_lladdr(arg, cpu_env); register_name =3D "LLAddr"; break; - case 1: + case CP0_REG17__MAAR: CP0_CHECK(ctx->mrp); gen_helper_dmfc0_maar(arg, cpu_env); register_name =3D "MAAR"; break; - case 2: + case CP0_REG17__MAARI: CP0_CHECK(ctx->mrp); gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_MAARI)); register_name =3D "MAARI"; @@ -9537,16 +9537,16 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, = int reg, int sel) break; case CP0_REGISTER_17: switch (sel) { - case 0: + case CP0_REG17__LLADDR: gen_helper_mtc0_lladdr(cpu_env, arg); register_name =3D "LLAddr"; break; - case 1: + case CP0_REG17__MAAR: CP0_CHECK(ctx->mrp); gen_helper_mtc0_maar(cpu_env, arg); register_name =3D "MAAR"; break; - case 2: + case CP0_REG17__MAARI: CP0_CHECK(ctx->mrp); gen_helper_mtc0_maari(cpu_env, arg); register_name =3D "MAARI"; --=20 2.7.4