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X-Received-From: 2607:f8b0:4864:20::641 Subject: [Qemu-devel] [PATCH v4 21/28] riscv: sifive_u: Update UART base addresses and IRQs X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This updates the UART base address and IRQs to match the hardware. Signed-off-by: Bin Meng Reviewed-by: Jonathan Behrens Acked-by: Alistair Francis Reviewed-by: Chih-Min Chao --- Changes in v4: None Changes in v3: - update IRQ numbers of both UARTs to match hardware as well Changes in v2: None hw/riscv/sifive_u.c | 4 ++-- include/hw/riscv/sifive_u.h | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index 8818fd6..a85db77 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -64,8 +64,8 @@ static const struct MemmapEntry { [SIFIVE_U_CLINT] =3D { 0x2000000, 0x10000 }, [SIFIVE_U_PLIC] =3D { 0xc000000, 0x4000000 }, [SIFIVE_U_PRCI] =3D { 0x10000000, 0x1000 }, - [SIFIVE_U_UART0] =3D { 0x10013000, 0x1000 }, - [SIFIVE_U_UART1] =3D { 0x10023000, 0x1000 }, + [SIFIVE_U_UART0] =3D { 0x10010000, 0x1000 }, + [SIFIVE_U_UART1] =3D { 0x10011000, 0x1000 }, [SIFIVE_U_DRAM] =3D { 0x80000000, 0x0 }, [SIFIVE_U_GEM] =3D { 0x100900FC, 0x2000 }, }; diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h index 0ec04df..9acb69e 100644 --- a/include/hw/riscv/sifive_u.h +++ b/include/hw/riscv/sifive_u.h @@ -62,8 +62,8 @@ enum { }; =20 enum { - SIFIVE_U_UART0_IRQ =3D 3, - SIFIVE_U_UART1_IRQ =3D 4, + SIFIVE_U_UART0_IRQ =3D 4, + SIFIVE_U_UART1_IRQ =3D 5, SIFIVE_U_GEM_IRQ =3D 0x35 }; =20 --=20 2.7.4