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X-Received-From: 2607:f8b0:4864:20::644 Subject: [Qemu-devel] [PATCH v4 19/28] riscv: sifive_u: Add PRCI block to the SoC X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Add PRCI mmio base address and size mappings to sifive_u machine, and generate the corresponding device tree node. Signed-off-by: Bin Meng --- Changes in v4: None Changes in v3: None Changes in v2: None hw/riscv/sifive_u.c | 21 ++++++++++++++++++++- include/hw/riscv/sifive_u.h | 1 + 2 files changed, 21 insertions(+), 1 deletion(-) diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index 08db741..bd5551c 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -9,6 +9,7 @@ * 0) UART * 1) CLINT (Core Level Interruptor) * 2) PLIC (Platform Level Interrupt Controller) + * 3) PRCI (Power, Reset, Clock, Interrupt) * * This board currently generates devicetree dynamically that indicates at= least * two harts and up to five harts. @@ -43,6 +44,7 @@ #include "hw/riscv/sifive_clint.h" #include "hw/riscv/sifive_uart.h" #include "hw/riscv/sifive_u.h" +#include "hw/riscv/sifive_u_prci.h" #include "hw/riscv/boot.h" #include "chardev/char.h" #include "sysemu/arch_init.h" @@ -61,6 +63,7 @@ static const struct MemmapEntry { [SIFIVE_U_MROM] =3D { 0x1000, 0x11000 }, [SIFIVE_U_CLINT] =3D { 0x2000000, 0x10000 }, [SIFIVE_U_PLIC] =3D { 0xc000000, 0x4000000 }, + [SIFIVE_U_PRCI] =3D { 0x10000000, 0x1000 }, [SIFIVE_U_UART0] =3D { 0x10013000, 0x1000 }, [SIFIVE_U_UART1] =3D { 0x10023000, 0x1000 }, [SIFIVE_U_DRAM] =3D { 0x80000000, 0x0 }, @@ -78,7 +81,7 @@ static void create_fdt(SiFiveUState *s, const struct Memm= apEntry *memmap, uint32_t *cells; char *nodename; char ethclk_names[] =3D "pclk\0hclk\0tx_clk"; - uint32_t plic_phandle, ethclk_phandle, phandle =3D 1; + uint32_t plic_phandle, prci_phandle, ethclk_phandle, phandle =3D 1; uint32_t uartclk_phandle; uint32_t hfclk_phandle, rtcclk_phandle; =20 @@ -189,6 +192,21 @@ static void create_fdt(SiFiveUState *s, const struct M= emmapEntry *memmap, g_free(cells); g_free(nodename); =20 + prci_phandle =3D phandle++; + nodename =3D g_strdup_printf("/soc/clock-controller@%lx", + (long)memmap[SIFIVE_U_PRCI].base); + qemu_fdt_add_subnode(fdt, nodename); + qemu_fdt_setprop_cell(fdt, nodename, "phandle", prci_phandle); + qemu_fdt_setprop_cell(fdt, nodename, "#clock-cells", 0x1); + qemu_fdt_setprop_cells(fdt, nodename, "clocks", + hfclk_phandle, rtcclk_phandle); + qemu_fdt_setprop_cells(fdt, nodename, "reg", + 0x0, memmap[SIFIVE_U_PRCI].base, + 0x0, memmap[SIFIVE_U_PRCI].size); + qemu_fdt_setprop_string(fdt, nodename, "compatible", + "sifive,fu540-c000-prci"); + g_free(nodename); + plic_phandle =3D phandle++; cells =3D g_new0(uint32_t, ms->smp.cpus * 4 - 2); for (cpu =3D 0; cpu < ms->smp.cpus; cpu++) { @@ -483,6 +501,7 @@ static void riscv_sifive_u_soc_realize(DeviceState *dev= , Error **errp) sifive_clint_create(memmap[SIFIVE_U_CLINT].base, memmap[SIFIVE_U_CLINT].size, ms->smp.cpus, SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE); + sifive_u_prci_create(memmap[SIFIVE_U_PRCI].base); =20 for (i =3D 0; i < SIFIVE_U_PLIC_NUM_SOURCES; i++) { plic_gpios[i] =3D qdev_get_gpio_in(DEVICE(s->plic), i); diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h index debbf28..0ec04df 100644 --- a/include/hw/riscv/sifive_u.h +++ b/include/hw/riscv/sifive_u.h @@ -54,6 +54,7 @@ enum { SIFIVE_U_MROM, SIFIVE_U_CLINT, SIFIVE_U_PLIC, + SIFIVE_U_PRCI, SIFIVE_U_UART0, SIFIVE_U_UART1, SIFIVE_U_DRAM, --=20 2.7.4