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X-Received-From: 2607:f8b0:4864:20::444 Subject: [Qemu-devel] [PATCH v4 13/28] riscv: hart: Add a "hartid-base" property to RISC-V hart array X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" At present each hart's hartid in a RISC-V hart array is assigned the same value of its index in the hart array. But for a system that has multiple hart arrays, this is not the case any more. Add a new "hartid-base" property so that hartid number can be assigned based on the property value. Signed-off-by: Bin Meng --- Changes in v4: - new patch to add a "hartid-base" property to RISC-V hart array Changes in v3: None Changes in v2: None hw/riscv/riscv_hart.c | 8 +++++--- include/hw/riscv/riscv_hart.h | 1 + 2 files changed, 6 insertions(+), 3 deletions(-) diff --git a/hw/riscv/riscv_hart.c b/hw/riscv/riscv_hart.c index 9deef869..52ab86a 100644 --- a/hw/riscv/riscv_hart.c +++ b/hw/riscv/riscv_hart.c @@ -27,6 +27,7 @@ =20 static Property riscv_harts_props[] =3D { DEFINE_PROP_UINT32("num-harts", RISCVHartArrayState, num_harts, 1), + DEFINE_PROP_UINT32("hartid-base", RISCVHartArrayState, hartid_base, 0), DEFINE_PROP_STRING("cpu-type", RISCVHartArrayState, cpu_type), DEFINE_PROP_END_OF_LIST(), }; @@ -37,7 +38,7 @@ static void riscv_harts_cpu_reset(void *opaque) cpu_reset(CPU(cpu)); } =20 -static void riscv_hart_realize(RISCVHartArrayState *s, int idx, +static void riscv_hart_realize(RISCVHartArrayState *s, int idx, uint32_t h= artid, char *cpu_type, Error **errp) { Error *err =3D NULL; @@ -45,7 +46,7 @@ static void riscv_hart_realize(RISCVHartArrayState *s, in= t idx, object_initialize_child(OBJECT(s), "harts[*]", &s->harts[idx], sizeof(RISCVCPU), cpu_type, &error_abort, NULL); - s->harts[idx].env.mhartid =3D idx; + s->harts[idx].env.mhartid =3D hartid; qemu_register_reset(riscv_harts_cpu_reset, &s->harts[idx]); object_property_set_bool(OBJECT(&s->harts[idx]), true, "realized", &err); @@ -58,12 +59,13 @@ static void riscv_hart_realize(RISCVHartArrayState *s, = int idx, static void riscv_harts_realize(DeviceState *dev, Error **errp) { RISCVHartArrayState *s =3D RISCV_HART_ARRAY(dev); + uint32_t hartid =3D s->hartid_base; int n; =20 s->harts =3D g_new0(RISCVCPU, s->num_harts); =20 for (n =3D 0; n < s->num_harts; n++) { - riscv_hart_realize(s, n, s->cpu_type, errp); + riscv_hart_realize(s, n, hartid + n, s->cpu_type, errp); } } =20 diff --git a/include/hw/riscv/riscv_hart.h b/include/hw/riscv/riscv_hart.h index 0671d88..1984e30 100644 --- a/include/hw/riscv/riscv_hart.h +++ b/include/hw/riscv/riscv_hart.h @@ -32,6 +32,7 @@ typedef struct RISCVHartArrayState { =20 /*< public >*/ uint32_t num_harts; + uint32_t hartid_base; char *cpu_type; RISCVCPU *harts; } RISCVHartArrayState; --=20 2.7.4