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boundary="===============1818700280045352391==" Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" --===============1818700280045352391== Content-Language: en-AU Content-Type: multipart/alternative; boundary="_000_156594108323439909btcom_" --_000_156594108323439909btcom_ Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Preparation for collapsing the two byte swaps adjust_endianness and handle_bswap into the former. Call memory_region_dispatch_{read|write} with endianness encoded into the "MemOp op" operand. This patch does not change any behaviour as memory_region_dispatch_{read|write} is yet to handle the endianness. Once it does handle endianness, callers with byte swaps can collapse them into adjust_endianness. Signed-off-by: Tony Nguyen --- accel/tcg/cputlb.c | 6 ++++-- exec.c | 5 +++-- hw/intc/armv7m_nvic.c | 15 ++++++++------- hw/s390x/s390-pci-inst.c | 6 ++++-- hw/vfio/pci-quirks.c | 5 +++-- hw/virtio/virtio-pci.c | 6 ++++-- memory_ldst.inc.c | 18 ++++++++++++------ 7 files changed, 38 insertions(+), 23 deletions(-) diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 6c83878..0aff6a3 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -906,7 +906,8 @@ static uint64_t io_readx(CPUArchState *env, CPUIOTLBEnt= ry *iotlbentry, qemu_mutex_lock_iothread(); locked =3D true; } - r =3D memory_region_dispatch_read(mr, mr_offset, &val, size_memop(size= ), + r =3D memory_region_dispatch_read(mr, mr_offset, &val, + size_memop(size) | MO_TE, iotlbentry->attrs); if (r !=3D MEMTX_OK) { hwaddr physaddr =3D mr_offset + @@ -947,7 +948,8 @@ static void io_writex(CPUArchState *env, CPUIOTLBEntry = *iotlbentry, qemu_mutex_lock_iothread(); locked =3D true; } - r =3D memory_region_dispatch_write(mr, mr_offset, val, size_memop(size= ), + r =3D memory_region_dispatch_write(mr, mr_offset, val, + size_memop(size) | MO_TE, iotlbentry->attrs); if (r !=3D MEMTX_OK) { hwaddr physaddr =3D mr_offset + diff --git a/exec.c b/exec.c index 303f9a7..562fb5b 100644 --- a/exec.c +++ b/exec.c @@ -3335,7 +3335,8 @@ static MemTxResult flatview_write_continue(FlatView *= fv, hwaddr addr, potential bugs */ val =3D ldn_p(buf, l); result |=3D memory_region_dispatch_write(mr, addr1, val, - size_memop(l), attrs); + size_memop(l) | MO_TE, + attrs); } else { /* RAM case */ ptr =3D qemu_ram_ptr_length(mr->ram_block, addr1, &l, false); @@ -3397,7 +3398,7 @@ MemTxResult flatview_read_continue(FlatView *fv, hwad= dr addr, release_lock |=3D prepare_mmio_access(mr); l =3D memory_access_size(mr, l, addr1); result |=3D memory_region_dispatch_read(mr, addr1, &val, - size_memop(l), attrs); + size_memop(l) | MO_TE, a= ttrs); stn_p(buf, l, val); } else { /* RAM case */ diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c index 975d7cc..e150f9a 100644 --- a/hw/intc/armv7m_nvic.c +++ b/hw/intc/armv7m_nvic.c @@ -2346,8 +2346,8 @@ static MemTxResult nvic_sysreg_ns_write(void *opaque,= hwaddr addr, if (attrs.secure) { /* S accesses to the alias act like NS accesses to the real region= */ attrs.secure =3D 0; - return memory_region_dispatch_write(mr, addr, value, size_memop(si= ze), - attrs); + return memory_region_dispatch_write(mr, addr, value, + size_memop(size) | MO_TE, attr= s); } else { /* NS attrs are RAZ/WI for privileged, and BusFault for user */ if (attrs.user) { @@ -2366,8 +2366,8 @@ static MemTxResult nvic_sysreg_ns_read(void *opaque, = hwaddr addr, if (attrs.secure) { /* S accesses to the alias act like NS accesses to the real region= */ attrs.secure =3D 0; - return memory_region_dispatch_read(mr, addr, data, size_memop(size= ), - attrs); + return memory_region_dispatch_read(mr, addr, data, + size_memop(size) | MO_TE, attrs= ); } else { /* NS attrs are RAZ/WI for privileged, and BusFault for user */ if (attrs.user) { @@ -2393,8 +2393,8 @@ static MemTxResult nvic_systick_write(void *opaque, h= waddr addr, /* Direct the access to the correct systick */ mr =3D sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->systick[attrs.secure]= ), 0); - return memory_region_dispatch_write(mr, addr, value, size_memop(size), - attrs); + return memory_region_dispatch_write(mr, addr, value, + size_memop(size) | MO_TE, attrs); } static MemTxResult nvic_systick_read(void *opaque, hwaddr addr, @@ -2406,7 +2406,8 @@ static MemTxResult nvic_systick_read(void *opaque, hw= addr addr, /* Direct the access to the correct systick */ mr =3D sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->systick[attrs.secure]= ), 0); - return memory_region_dispatch_read(mr, addr, data, size_memop(size), a= ttrs); + return memory_region_dispatch_read(mr, addr, data, size_memop(size) | = MO_TE, + attrs); } static const MemoryRegionOps nvic_systick_ops =3D { diff --git a/hw/s390x/s390-pci-inst.c b/hw/s390x/s390-pci-inst.c index 0e92a37..272cb28 100644 --- a/hw/s390x/s390-pci-inst.c +++ b/hw/s390x/s390-pci-inst.c @@ -373,7 +373,8 @@ static MemTxResult zpci_read_bar(S390PCIBusDevice *pbde= v, uint8_t pcias, mr =3D pbdev->pdev->io_regions[pcias].memory; mr =3D s390_get_subregion(mr, offset, len); offset -=3D mr->addr; - return memory_region_dispatch_read(mr, offset, data, size_memop(len), + return memory_region_dispatch_read(mr, offset, data, + size_memop(len) | MO_LE, MEMTXATTRS_UNSPECIFIED); } @@ -472,7 +473,8 @@ static MemTxResult zpci_write_bar(S390PCIBusDevice *pbd= ev, uint8_t pcias, mr =3D pbdev->pdev->io_regions[pcias].memory; mr =3D s390_get_subregion(mr, offset, len); offset -=3D mr->addr; - return memory_region_dispatch_write(mr, offset, data, size_memop(len), + return memory_region_dispatch_write(mr, offset, data, + size_memop(len) | MO_LE, MEMTXATTRS_UNSPECIFIED); } diff --git a/hw/vfio/pci-quirks.c b/hw/vfio/pci-quirks.c index d5c0268..53db1c3 100644 --- a/hw/vfio/pci-quirks.c +++ b/hw/vfio/pci-quirks.c @@ -1072,7 +1072,8 @@ static void vfio_rtl8168_quirk_address_write(void *op= aque, hwaddr addr, /* Write to the proper guest MSI-X table instead */ memory_region_dispatch_write(&vdev->pdev.msix_table_mmio, - offset, val, size_memop(size)= , + offset, val, + size_memop(size) | MO_LE, MEMTXATTRS_UNSPECIFIED); } return; /* Do not write guest MSI-X data to hardware */ @@ -1103,7 +1104,7 @@ static uint64_t vfio_rtl8168_quirk_data_read(void *op= aque, if (rtl->enabled && (vdev->pdev.cap_present & QEMU_PCI_CAP_MSIX)) { hwaddr offset =3D rtl->addr & 0xfff; memory_region_dispatch_read(&vdev->pdev.msix_table_mmio, offset, - &data, size_memop(size), + &data, size_memop(size) | MO_LE, MEMTXATTRS_UNSPECIFIED); trace_vfio_quirk_rtl8168_msix_read(vdev->vbasedev.name, offset, da= ta); } diff --git a/hw/virtio/virtio-pci.c b/hw/virtio/virtio-pci.c index b929e44..ad06c12 100644 --- a/hw/virtio/virtio-pci.c +++ b/hw/virtio/virtio-pci.c @@ -551,7 +551,8 @@ void virtio_address_space_write(VirtIOPCIProxy *proxy, = hwaddr addr, /* As length is under guest control, handle illegal values. */ return; } - memory_region_dispatch_write(mr, addr, val, size_memop(len), + /* FIXME: memory_region_dispatch_write ignores MO_BSWAP. */ + memory_region_dispatch_write(mr, addr, val, size_memop(len) | MO_LE, MEMTXATTRS_UNSPECIFIED); } @@ -575,7 +576,8 @@ virtio_address_space_read(VirtIOPCIProxy *proxy, hwaddr= addr, /* Make sure caller aligned buf properly */ assert(!(((uintptr_t)buf) & (len - 1))); - memory_region_dispatch_read(mr, addr, &val, size_memop(len), + /* FIXME: memory_region_dispatch_read ignores MO_BSWAP. */ + memory_region_dispatch_read(mr, addr, &val, size_memop(len) | MO_LE, MEMTXATTRS_UNSPECIFIED); switch (len) { case 1: diff --git a/memory_ldst.inc.c b/memory_ldst.inc.c index d08fc79..482e4b3 100644 --- a/memory_ldst.inc.c +++ b/memory_ldst.inc.c @@ -37,7 +37,8 @@ static inline uint32_t glue(address_space_ldl_internal, S= UFFIX)(ARG1_DECL, release_lock |=3D prepare_mmio_access(mr); /* I/O case */ - r =3D memory_region_dispatch_read(mr, addr1, &val, MO_32, attrs); + /* FIXME: memory_region_dispatch_read ignores MO_BSWAP. */ + r =3D memory_region_dispatch_read(mr, addr1, &val, MO_32 | endian,= attrs); #if defined(TARGET_WORDS_BIGENDIAN) if (endian =3D=3D MO_LE) { val =3D bswap32(val); @@ -112,7 +113,8 @@ static inline uint64_t glue(address_space_ldq_internal,= SUFFIX)(ARG1_DECL, release_lock |=3D prepare_mmio_access(mr); /* I/O case */ - r =3D memory_region_dispatch_read(mr, addr1, &val, MO_64, attrs); + /* FIXME: memory_region_dispatch_read ignores MO_BSWAP. */ + r =3D memory_region_dispatch_read(mr, addr1, &val, MO_64 | endian,= attrs); #if defined(TARGET_WORDS_BIGENDIAN) if (endian =3D=3D MO_LE) { val =3D bswap64(val); @@ -221,7 +223,8 @@ static inline uint32_t glue(address_space_lduw_internal= , SUFFIX)(ARG1_DECL, release_lock |=3D prepare_mmio_access(mr); /* I/O case */ - r =3D memory_region_dispatch_read(mr, addr1, &val, MO_16, attrs); + /* FIXME: memory_region_dispatch_read ignores MO_BSWAP. */ + r =3D memory_region_dispatch_read(mr, addr1, &val, MO_16 | endian,= attrs); #if defined(TARGET_WORDS_BIGENDIAN) if (endian =3D=3D MO_LE) { val =3D bswap16(val); @@ -342,7 +345,8 @@ static inline void glue(address_space_stl_internal, SUF= FIX)(ARG1_DECL, val =3D bswap32(val); } #endif - r =3D memory_region_dispatch_write(mr, addr1, val, MO_32, attrs); + /* FIXME: memory_region_dispatch_write ignores MO_BSWAP. */ + r =3D memory_region_dispatch_write(mr, addr1, val, MO_32 | endian,= attrs); } else { /* RAM case */ ptr =3D qemu_map_ram_ptr(mr->ram_block, addr1); @@ -447,7 +451,8 @@ static inline void glue(address_space_stw_internal, SUF= FIX)(ARG1_DECL, val =3D bswap16(val); } #endif - r =3D memory_region_dispatch_write(mr, addr1, val, MO_16, attrs); + /* FIXME: memory_region_dispatch_write ignores MO_BSWAP. */ + r =3D memory_region_dispatch_write(mr, addr1, val, MO_16 | endian,= attrs); } else { /* RAM case */ ptr =3D qemu_map_ram_ptr(mr->ram_block, addr1); @@ -520,7 +525,8 @@ static void glue(address_space_stq_internal, SUFFIX)(AR= G1_DECL, val =3D bswap64(val); } #endif - r =3D memory_region_dispatch_write(mr, addr1, val, MO_64, attrs); + /* FIXME: memory_region_dispatch_write ignores MO_BSWAP. */ + r =3D memory_region_dispatch_write(mr, addr1, val, MO_64 | endian,= attrs); } else { /* RAM case */ ptr =3D qemu_map_ram_ptr(mr->ram_block, addr1); -- 1.8.3.1 ? --_000_156594108323439909btcom_ Content-Type: text/html; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable

Preparation for collapsing the two by= te swaps adjust_endianness and
handle_bswap into the former.

Call memory_region_dispatch_{read|write} with endianness encoded into<= /div>
the "MemOp op" operand.

This patch does not change any behaviour as
memory_region_dispatch_{read|write} is yet to handle the endianness.

Once it does handle endianness, callers with byte swaps can collapse
them into adjust_endianness.

Signed-off-by: Tony Nguyen <tony.nguyen@bt.com>
---
 accel/tcg/cputlb.c       |  6 +++= ;+--
 exec.c                 &= nbsp; |  5 +++--
 hw/intc/armv7m_nvic.c    | 15 +++++= ;+++-------
 hw/s390x/s390-pci-inst.c |  6 ++++--
 hw/vfio/pci-quirks.c     |  5 +++--
 hw/virtio/virtio-pci.c   |  6 ++++--
 memory_ldst.inc.c        | 18 +++= ;+++++++++------
 7 files changed, 38 insertions(+), 23 deletions(-)

diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
index 6c83878..0aff6a3 100644
--- a/accel/tcg/cputlb.c
+++ b/accel/tcg/cputlb.c
@@ -906,7 +906,8 @@ static uint64_t io_readx(CPUArchState *env, CP= UIOTLBEntry *iotlbentry,
         qemu_mutex_lock_iothread();
         locked =3D true;
     }
-    r =3D memory_region_dispatch_read(mr, mr_offset, &v= al, size_memop(size),
+    r =3D memory_region_dispatch_read(mr, mr_offset, &a= mp;val,
+                   &= nbsp;                size_memop(siz= e) | MO_TE,
                    =                  iotlbentry-&g= t;attrs);
     if (r !=3D MEMTX_OK) {
         hwaddr physaddr =3D mr_offset +<= /div>
@@ -947,7 +948,8 @@ static void io_writex(CPUArchState *env, CPUIO= TLBEntry *iotlbentry,
         qemu_mutex_lock_iothread();
         locked =3D true;
     }
-    r =3D memory_region_dispatch_write(mr, mr_offset, val, = size_memop(size),
+    r =3D memory_region_dispatch_write(mr, mr_offset, v= al,
+                   &= nbsp;                 size_memop(si= ze) | MO_TE,
                    =                   iotlbentry-&= gt;attrs);
     if (r !=3D MEMTX_OK) {
         hwaddr physaddr =3D mr_offset +<= /div>
diff --git a/exec.c b/exec.c
index 303f9a7..562fb5b 100644
--- a/exec.c
+++ b/exec.c
@@ -3335,7 +3335,8 @@ static MemTxResult flatview_write_continue(F= latView *fv, hwaddr addr,
                potential bugs= */
             val =3D ldn_p(buf, l);=
             result |=3D memory_reg= ion_dispatch_write(mr, addr1, val,
-                    = ;                     &nb= sp;         size_memop(l), attrs);
+                   &= nbsp;                    =           size_memop(l) | MO_TE,
+                   &= nbsp;                    =           attrs);
         } else {
             /* RAM case */
             ptr =3D qemu_ram_ptr_l= ength(mr->ram_block, addr1, &l, false);
@@ -3397,7 +3398,7 @@ MemTxResult flatview_read_continue(FlatView = *fv, hwaddr addr,
             release_lock |=3D prep= are_mmio_access(mr);
             l =3D memory_access_si= ze(mr, l, addr1);
             result |=3D memory_reg= ion_dispatch_read(mr, addr1, &val,
-                    = ;                     &nb= sp;        size_memop(l), attrs);
+                   &= nbsp;                    =          size_memop(l) | MO_TE, attrs);
             stn_p(buf, l, val);
         } else {
             /* RAM case */
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
index 975d7cc..e150f9a 100644
--- a/hw/intc/armv7m_nvic.c
+++ b/hw/intc/armv7m_nvic.c
@@ -2346,8 +2346,8 @@ static MemTxResult nvic_sysreg_ns_write(void= *opaque, hwaddr addr,
     if (attrs.secure) {
         /* S accesses to the alias act like = NS accesses to the real region */
         attrs.secure =3D 0;
-        return memory_region_dispatch_write(mr, a= ddr, value, size_memop(size),
-                    = ;                     &nb= sp;  attrs);
+        return memory_region_dispatch_write(m= r, addr, value,
+                   &= nbsp;                    =    size_memop(size) | MO_TE, attrs);
     } else {
         /* NS attrs are RAZ/WI for privilege= d, and BusFault for user */
         if (attrs.user) {
@@ -2366,8 +2366,8 @@ static MemTxResult nvic_sysreg_ns_read(void = *opaque, hwaddr addr,
     if (attrs.secure) {
         /* S accesses to the alias act like = NS accesses to the real region */
         attrs.secure =3D 0;
-        return memory_region_dispatch_read(mr, ad= dr, data, size_memop(size),
-                    = ;                     &nb= sp; attrs);
+        return memory_region_dispatch_read(mr= , addr, data,
+                   &= nbsp;                    =   size_memop(size) | MO_TE, attrs);
     } else {
         /* NS attrs are RAZ/WI for privilege= d, and BusFault for user */
         if (attrs.user) {
@@ -2393,8 +2393,8 @@ static MemTxResult nvic_systick_write(void *= opaque, hwaddr addr,
 
     /* Direct the access to the correct systick */
     mr =3D sysbus_mmio_get_region(SYS_BUS_DEVICE(&= s->systick[attrs.secure]), 0);
-    return memory_region_dispatch_write(mr, addr, value, si= ze_memop(size),
-                    = ;                    attr= s);
+    return memory_region_dispatch_write(mr, addr, value= ,
+                   &= nbsp;                    = size_memop(size) | MO_TE, attrs);
 }
 
 static MemTxResult nvic_systick_read(void *opaque, hwaddr addr,<= /div>
@@ -2406,7 +2406,8 @@ static MemTxResult nvic_systick_read(void *o= paque, hwaddr addr,
 
     /* Direct the access to the correct systick */
     mr =3D sysbus_mmio_get_region(SYS_BUS_DEVICE(&= s->systick[attrs.secure]), 0);
-    return memory_region_dispatch_read(mr, addr, data, size= _memop(size), attrs);
+    return memory_region_dispatch_read(mr, addr, data, = size_memop(size) | MO_TE,
+                   &= nbsp;                   attrs)= ;
 }
 
 static const MemoryRegionOps nvic_systick_ops =3D {
diff --git a/hw/s390x/s390-pci-inst.c b/hw/s390x/s390-pci-inst.c
index 0e92a37..272cb28 100644
--- a/hw/s390x/s390-pci-inst.c
+++ b/hw/s390x/s390-pci-inst.c
@@ -373,7 +373,8 @@ static MemTxResult zpci_read_bar(S390PCIBusDev= ice *pbdev, uint8_t pcias,
     mr =3D pbdev->pdev->io_regions[pcias].memory= ;
     mr =3D s390_get_subregion(mr, offset, len);
     offset -=3D mr->addr;
-    return memory_region_dispatch_read(mr, offset, data, si= ze_memop(len),
+    return memory_region_dispatch_read(mr, offset, data= ,
+                   &= nbsp;                   size_m= emop(len) | MO_LE,
                    =                     MEMTX= ATTRS_UNSPECIFIED);
 }
 
@@ -472,7 +473,8 @@ static MemTxResult zpci_write_bar(S390PCIBusDe= vice *pbdev, uint8_t pcias,
     mr =3D pbdev->pdev->io_regions[pcias].memory= ;
     mr =3D s390_get_subregion(mr, offset, len);
     offset -=3D mr->addr;
-    return memory_region_dispatch_write(mr, offset, data, s= ize_memop(len),
+    return memory_region_dispatch_write(mr, offset, dat= a,
+                   &= nbsp;                    = size_memop(len) | MO_LE,
                    =                      = ;MEMTXATTRS_UNSPECIFIED);
 }
 
diff --git a/hw/vfio/pci-quirks.c b/hw/vfio/pci-quirks.c
index d5c0268..53db1c3 100644
--- a/hw/vfio/pci-quirks.c
+++ b/hw/vfio/pci-quirks.c
@@ -1072,7 +1072,8 @@ static void vfio_rtl8168_quirk_address_write= (void *opaque, hwaddr addr,
 
                 /* Write= to the proper guest MSI-X table instead */
                 memory_r= egion_dispatch_write(&vdev->pdev.msix_table_mmio,
-                    = ;                     &nb= sp;   offset, val, size_memop(size),
+                   &= nbsp;                    =     offset, val,
+                   &= nbsp;                    =     size_memop(size) | MO_LE,
                    =                      = ;     MEMTXATTRS_UNSPECIFIED);
             }
             return; /* Do not writ= e guest MSI-X data to hardware */
@@ -1103,7 +1104,7 @@ static uint64_t vfio_rtl8168_quirk_data_read= (void *opaque,
     if (rtl->enabled && (vdev->pdev.cap_= present & QEMU_PCI_CAP_MSIX)) {
         hwaddr offset =3D rtl->addr &= 0xfff;
         memory_region_dispatch_read(&vde= v->pdev.msix_table_mmio, offset,
-                    = ;                &data, size_me= mop(size),
+                   &= nbsp;                &data, siz= e_memop(size) | MO_LE,
                    =                  MEMTXATTRS_UN= SPECIFIED);
         trace_vfio_quirk_rtl8168_msix_read(v= dev->vbasedev.name, offset, data);
     }
diff --git a/hw/virtio/virtio-pci.c b/hw/virtio/virtio-pci.c
index b929e44..ad06c12 100644
--- a/hw/virtio/virtio-pci.c
+++ b/hw/virtio/virtio-pci.c
@@ -551,7 +551,8 @@ void virtio_address_space_write(VirtIOPCIProxy= *proxy, hwaddr addr,
         /* As length is under guest control,= handle illegal values. */
         return;
     }
-    memory_region_dispatch_write(mr, addr, val, size_memop(= len),
+    /* FIXME: memory_region_dispatch_write ignores MO_B= SWAP.  */
+    memory_region_dispatch_write(mr, addr, val, size_me= mop(len) | MO_LE,
                    =               MEMTXATTRS_UNSPECIFIED);
 }
 
@@ -575,7 +576,8 @@ virtio_address_space_read(VirtIOPCIProxy *prox= y, hwaddr addr,
     /* Make sure caller aligned buf properly */
     assert(!(((uintptr_t)buf) & (len - 1)));
 
-    memory_region_dispatch_read(mr, addr, &val, size_me= mop(len),
+    /* FIXME: memory_region_dispatch_read ignores MO_BS= WAP.  */
+    memory_region_dispatch_read(mr, addr, &val, siz= e_memop(len) | MO_LE,
                    =              MEMTXATTRS_UNSPECIFIED);
     switch (len) {
     case 1:
diff --git a/memory_ldst.inc.c b/memory_ldst.inc.c
index d08fc79..482e4b3 100644
--- a/memory_ldst.inc.c
+++ b/memory_ldst.inc.c
@@ -37,7 +37,8 @@ static inline uint32_t glue(address_space_ldl_in= ternal, SUFFIX)(ARG1_DECL,
         release_lock |=3D prepare_mmio_acces= s(mr);
 
         /* I/O case */
-        r =3D memory_region_dispatch_read(mr, add= r1, &val, MO_32, attrs);
+        /* FIXME: memory_region_dispatch_read= ignores MO_BSWAP.  */
+        r =3D memory_region_dispatch_read(mr,= addr1, &val, MO_32 | endian, attrs);
 #if defined(TARGET_WORDS_BIGENDIAN)
         if (endian =3D=3D MO_LE) {
             val =3D bswap32(val);<= /div>
@@ -112,7 +113,8 @@ static inline uint64_t glue(address_space_ldq_= internal, SUFFIX)(ARG1_DECL,
         release_lock |=3D prepare_mmio_acces= s(mr);
 
         /* I/O case */
-        r =3D memory_region_dispatch_read(mr, add= r1, &val, MO_64, attrs);
+        /* FIXME: memory_region_dispatch_read= ignores MO_BSWAP.  */
+        r =3D memory_region_dispatch_read(mr,= addr1, &val, MO_64 | endian, attrs);
 #if defined(TARGET_WORDS_BIGENDIAN)
         if (endian =3D=3D MO_LE) {
             val =3D bswap64(val);<= /div>
@@ -221,7 +223,8 @@ static inline uint32_t glue(address_space_lduw= _internal, SUFFIX)(ARG1_DECL,
         release_lock |=3D prepare_mmio_acces= s(mr);
 
         /* I/O case */
-        r =3D memory_region_dispatch_read(mr, add= r1, &val, MO_16, attrs);
+        /* FIXME: memory_region_dispatch_read= ignores MO_BSWAP.  */
+        r =3D memory_region_dispatch_read(mr,= addr1, &val, MO_16 | endian, attrs);
 #if defined(TARGET_WORDS_BIGENDIAN)
         if (endian =3D=3D MO_LE) {
             val =3D bswap16(val);<= /div>
@@ -342,7 +345,8 @@ static inline void glue(address_space_stl_inte= rnal, SUFFIX)(ARG1_DECL,
             val =3D bswap32(val);<= /div>
         }
 #endif
-        r =3D memory_region_dispatch_write(mr, ad= dr1, val, MO_32, attrs);
+        /* FIXME: memory_region_dispatch_writ= e ignores MO_BSWAP.  */
+        r =3D memory_region_dispatch_write(mr= , addr1, val, MO_32 | endian, attrs);
     } else {
         /* RAM case */
         ptr =3D qemu_map_ram_ptr(mr->ram_= block, addr1);
@@ -447,7 +451,8 @@ static inline void glue(address_space_stw_inte= rnal, SUFFIX)(ARG1_DECL,
             val =3D bswap16(val);<= /div>
         }
 #endif
-        r =3D memory_region_dispatch_write(mr, ad= dr1, val, MO_16, attrs);
+        /* FIXME: memory_region_dispatch_writ= e ignores MO_BSWAP.  */
+        r =3D memory_region_dispatch_write(mr= , addr1, val, MO_16 | endian, attrs);
     } else {
         /* RAM case */
         ptr =3D qemu_map_ram_ptr(mr->ram_= block, addr1);
@@ -520,7 +525,8 @@ static void glue(address_space_stq_internal, S= UFFIX)(ARG1_DECL,
             val =3D bswap64(val);<= /div>
         }
 #endif
-        r =3D memory_region_dispatch_write(mr, ad= dr1, val, MO_64, attrs);
+        /* FIXME: memory_region_dispatch_writ= e ignores MO_BSWAP.  */
+        r =3D memory_region_dispatch_write(mr= , addr1, val, MO_64 | endian, attrs);
     } else {
         /* RAM case */
         ptr =3D qemu_map_ram_ptr(mr->ram_= block, addr1);
-- 
1.8.3.1

​

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