From nobody Thu Mar 28 22:22:47 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1565763191; cv=none; d=zoho.com; s=zohoarc; b=IZGQOENDHnPO7ohwRl/I56uzqp7BIBxNJ2S6nKKM5e2jPqTTa7fFXjZxasR1dNbxFMpBmAx/FW/rA0SpKkHwmQhfo6Y244yFRrB1Fskyt+FP/Yk9pmlJQTgBooXWMeY0ooXHeNag6Is3CxRn8IaL8VZuAXrNM2/XcTZQ8LWH0qk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1565763191; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=v1c+VLZf9CdXtKjT2f1D1iO6RheTR3pL5Y4eURltFLA=; b=LpkhSw2AtvNBExvmkLshA/zbILTCeEg8KE8vWPRavnI8yzfIBzVXc15N4I1cd2NzskK+/h6UfeOpweU8m/y0xz/1QioMQhni84vbK5gsPALQPuz9llh14TVzlrmiLclqdp1FxcoIQ0XpshBzS5VRgAahk5w+X2fUA6WENcua9Ls= ARC-Authentication-Results: i=1; mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1565763190809421.3308385816109; Tue, 13 Aug 2019 23:13:10 -0700 (PDT) Received: from localhost ([::1]:57402 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1hxmWv-0003zo-GM for importer@patchew.org; Wed, 14 Aug 2019 02:13:05 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:52407) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1hxmV3-0002QX-7Y for qemu-devel@nongnu.org; Wed, 14 Aug 2019 02:11:10 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hxmV2-0006LT-16 for qemu-devel@nongnu.org; Wed, 14 Aug 2019 02:11:09 -0400 Received: from mx0a-001b2d01.pphosted.com ([148.163.156.1]:53364) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1hxmV1-0006JP-Mg for qemu-devel@nongnu.org; Wed, 14 Aug 2019 02:11:07 -0400 Received: from pps.filterd (m0098396.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id x7E66r6D050432 for ; Wed, 14 Aug 2019 02:11:06 -0400 Received: from e34.co.us.ibm.com (e34.co.us.ibm.com [32.97.110.152]) by mx0a-001b2d01.pphosted.com with ESMTP id 2uc9s0ed0x-1 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=NOT) for ; Wed, 14 Aug 2019 02:11:05 -0400 Received: from localhost by e34.co.us.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; (version=TLSv1/SSLv3 cipher=AES256-GCM-SHA384 bits=256/256) Wed, 14 Aug 2019 07:11:03 +0100 Received: from b03ledav003.gho.boulder.ibm.com (b03ledav003.gho.boulder.ibm.com [9.17.130.234]) by b03cxnp08028.gho.boulder.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id x7E6B2Kq47120668 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Wed, 14 Aug 2019 06:11:02 GMT Received: from b03ledav003.gho.boulder.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 7EA206A04D; Wed, 14 Aug 2019 06:11:02 +0000 (GMT) Received: from b03ledav003.gho.boulder.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 358AF6A047; Wed, 14 Aug 2019 06:11:00 +0000 (GMT) Received: from [127.0.1.1] (unknown [9.124.31.79]) by b03ledav003.gho.boulder.ibm.com (Postfix) with ESMTP; Wed, 14 Aug 2019 06:10:59 +0000 (GMT) From: Aravinda Prasad To: aik@au1.ibm.com, qemu-ppc@nongnu.org, qemu-devel@nongnu.org, david@gibson.dropbear.id.au Date: Wed, 14 Aug 2019 11:40:58 +0530 In-Reply-To: <156576293464.29984.1631520917528142744.stgit@aravinda> References: <156576293464.29984.1631520917528142744.stgit@aravinda> User-Agent: StGit/0.17.1-dirty MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 x-cbid: 19081406-0016-0000-0000-000009DC0450 X-IBM-SpamModules-Scores: X-IBM-SpamModules-Versions: BY=3.00011590; HX=3.00000242; KW=3.00000007; PH=3.00000004; SC=3.00000287; SDB=6.01246559; UDB=6.00657833; IPR=6.01028066; MB=3.00028170; MTD=3.00000008; XFM=3.00000015; UTC=2019-08-14 06:11:04 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 19081406-0017-0000-0000-0000446B2F4D Message-Id: <156576305894.29984.16040662309121781174.stgit@aravinda> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2019-08-14_02:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=0 phishscore=0 bulkscore=0 spamscore=0 clxscore=1015 lowpriorityscore=0 mlxscore=0 impostorscore=0 mlxlogscore=899 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1906280000 definitions=main-1908140060 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [generic] X-Received-From: 148.163.156.1 Subject: [Qemu-devel] [patch-for-4.2 PATCH v11 1/6] Wrapper function to wait on condition for the main loop mutex X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: paulus@ozlabs.org, aravinda@linux.vnet.ibm.com, groug@kaod.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Introduce a wrapper function to wait on condition for the main loop mutex. This function atomically releases the main loop mutex and causes the calling thread to block on the condition. This wrapper is required because qemu_global_mutex is a static variable. Signed-off-by: Aravinda Prasad Reviewed-by: David Gibson Reviewed-by: Greg Kurz --- cpus.c | 5 +++++ include/qemu/main-loop.h | 8 ++++++++ 2 files changed, 13 insertions(+) diff --git a/cpus.c b/cpus.c index 927a00a..7dca2b7 100644 --- a/cpus.c +++ b/cpus.c @@ -1867,6 +1867,11 @@ void qemu_mutex_unlock_iothread(void) qemu_mutex_unlock(&qemu_global_mutex); } =20 +void qemu_cond_wait_iothread(QemuCond *cond) +{ + qemu_cond_wait(cond, &qemu_global_mutex); +} + static bool all_vcpus_paused(void) { CPUState *cpu; diff --git a/include/qemu/main-loop.h b/include/qemu/main-loop.h index f6ba78e..a6d20b0 100644 --- a/include/qemu/main-loop.h +++ b/include/qemu/main-loop.h @@ -295,6 +295,14 @@ void qemu_mutex_lock_iothread_impl(const char *file, i= nt line); */ void qemu_mutex_unlock_iothread(void); =20 +/* + * qemu_cond_wait_iothread: Wait on condition for the main loop mutex + * + * This function atomically releases the main loop mutex and causes + * the calling thread to block on the condition. + */ +void qemu_cond_wait_iothread(QemuCond *cond); + /* internal interfaces */ =20 void qemu_fd_register(int fd); From nobody Thu Mar 28 22:22:47 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1565763315; cv=none; d=zoho.com; s=zohoarc; b=TQBjY8Ap7KqA94SU4AiVd/Mg14CrONsFCeQnjo0JzgYfQzYRsezfMZCvTdZv7RlGW7sUOlrSqTo+kOooyNnF3Wat24Y95HD6ABx8RJj6csJ4Oip+Giaj4f5chI2T8BiEvu3fyj+P7UP9x7pnZ459JJ28rc5uDmAVfqC83KHBhCY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1565763315; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=pdnNP3R5VbUJwsIJ+rcTMEKQDeJeNAbcrFg2xwvWpGQ=; b=Xh9LFW8JCTWgkHgG/7uP6ToiuRF7Sp62mJ3nZ8ZoCKF79zv9NjaGDJzjZ4wUf2BUtu5eLSL5mJsSHdeLkslqmLdJLnyBIJX20Vusjb8mQoDwdYYgHlTnufHZ5FY18JQnN1NUh60DSjVD84mCsizIxY8BgfT8747s2tn9nsMWOog= ARC-Authentication-Results: i=1; mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1565763315858147.08420273268018; Tue, 13 Aug 2019 23:15:15 -0700 (PDT) Received: from localhost ([::1]:57428 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1hxmZ0-0007Rm-Bq for importer@patchew.org; Wed, 14 Aug 2019 02:15:14 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:52442) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1hxmVJ-0002ZB-In for qemu-devel@nongnu.org; Wed, 14 Aug 2019 02:11:29 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hxmVF-0006jT-OH for qemu-devel@nongnu.org; Wed, 14 Aug 2019 02:11:23 -0400 Received: from mx0a-001b2d01.pphosted.com ([148.163.156.1]:20152) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1hxmVE-0006Zn-G4 for qemu-devel@nongnu.org; Wed, 14 Aug 2019 02:11:20 -0400 Received: from pps.filterd (m0098393.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id x7E673pD023102 for ; Wed, 14 Aug 2019 02:11:15 -0400 Received: from e32.co.us.ibm.com (e32.co.us.ibm.com [32.97.110.150]) by mx0a-001b2d01.pphosted.com with ESMTP id 2uc9nexcwa-1 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=NOT) for ; Wed, 14 Aug 2019 02:11:15 -0400 Received: from localhost by e32.co.us.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; (version=TLSv1/SSLv3 cipher=AES256-GCM-SHA384 bits=256/256) Wed, 14 Aug 2019 07:11:12 +0100 Received: from b03ledav004.gho.boulder.ibm.com (b03ledav004.gho.boulder.ibm.com [9.17.130.235]) by b03cxnp08025.gho.boulder.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id x7E6BBxF52625856 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Wed, 14 Aug 2019 06:11:11 GMT Received: from b03ledav004.gho.boulder.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 327F27805C; Wed, 14 Aug 2019 06:11:11 +0000 (GMT) Received: from b03ledav004.gho.boulder.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 0A4A978060; Wed, 14 Aug 2019 06:11:09 +0000 (GMT) Received: from [127.0.1.1] (unknown [9.124.31.79]) by b03ledav004.gho.boulder.ibm.com (Postfix) with ESMTP; Wed, 14 Aug 2019 06:11:08 +0000 (GMT) From: Aravinda Prasad To: aik@au1.ibm.com, qemu-ppc@nongnu.org, qemu-devel@nongnu.org, david@gibson.dropbear.id.au Date: Wed, 14 Aug 2019 11:41:07 +0530 In-Reply-To: <156576293464.29984.1631520917528142744.stgit@aravinda> References: <156576293464.29984.1631520917528142744.stgit@aravinda> User-Agent: StGit/0.17.1-dirty MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 x-cbid: 19081406-0004-0000-0000-00001535AEB8 X-IBM-SpamModules-Scores: X-IBM-SpamModules-Versions: BY=3.00011590; HX=3.00000242; KW=3.00000007; PH=3.00000004; SC=3.00000287; SDB=6.01246559; UDB=6.00657833; IPR=6.01028066; MB=3.00028170; MTD=3.00000008; XFM=3.00000015; UTC=2019-08-14 06:11:14 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 19081406-0005-0000-0000-00008CDE9E00 Message-Id: <156576306787.29984.3922767345151790072.stgit@aravinda> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2019-08-14_02:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=0 phishscore=0 bulkscore=0 spamscore=0 clxscore=1015 lowpriorityscore=0 mlxscore=0 impostorscore=0 mlxlogscore=999 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1906280000 definitions=main-1908140060 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [generic] X-Received-From: 148.163.156.1 Subject: [Qemu-devel] [patch-for-4.2 PATCH v11 2/6] ppc: spapr: Introduce FWNMI capability X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: paulus@ozlabs.org, aravinda@linux.vnet.ibm.com, groug@kaod.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Introduce the KVM capability KVM_CAP_PPC_FWNMI so that the KVM causes guest exit with NMI as exit reason when it encounters a machine check exception on the address belonging to a guest. Without this capability enabled, KVM redirects machine check exceptions to guest's 0x200 vector. This patch also introduces fwnmi-mce capability to deal with the case when a guest with the KVM_CAP_PPC_FWNMI capability enabled is attempted to migrate to a host that does not support this capability. Signed-off-by: Aravinda Prasad --- hw/ppc/spapr.c | 1 + hw/ppc/spapr_caps.c | 29 +++++++++++++++++++++++++++++ include/hw/ppc/spapr.h | 4 +++- target/ppc/kvm.c | 22 ++++++++++++++++++++++ target/ppc/kvm_ppc.h | 11 +++++++++++ 5 files changed, 66 insertions(+), 1 deletion(-) diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c index 855e9fb..07714cb 100644 --- a/hw/ppc/spapr.c +++ b/hw/ppc/spapr.c @@ -4463,6 +4463,7 @@ static void spapr_machine_class_init(ObjectClass *oc,= void *data) smc->default_caps.caps[SPAPR_CAP_NESTED_KVM_HV] =3D SPAPR_CAP_OFF; smc->default_caps.caps[SPAPR_CAP_LARGE_DECREMENTER] =3D SPAPR_CAP_ON; smc->default_caps.caps[SPAPR_CAP_CCF_ASSIST] =3D SPAPR_CAP_OFF; + smc->default_caps.caps[SPAPR_CAP_FWNMI_MCE] =3D SPAPR_CAP_OFF; spapr_caps_add_properties(smc, &error_abort); smc->irq =3D &spapr_irq_dual; smc->dr_phb_enabled =3D true; diff --git a/hw/ppc/spapr_caps.c b/hw/ppc/spapr_caps.c index 0263c78..5448123 100644 --- a/hw/ppc/spapr_caps.c +++ b/hw/ppc/spapr_caps.c @@ -481,6 +481,25 @@ static void cap_ccf_assist_apply(SpaprMachineState *sp= apr, uint8_t val, } } =20 +static void cap_fwnmi_mce_apply(SpaprMachineState *spapr, uint8_t val, + Error **errp) +{ + if (!val) { + return; /* Disabled by default */ + } + + if (tcg_enabled()) { + /* + * TCG support may not be correct in some conditions (e.g., in case + * of software injected faults like duplicate SLBs). + */ + warn_report("Firmware Assisted Non-Maskable Interrupts not support= ed in TCG"); + } else if (kvm_enabled() && !kvmppc_has_cap_ppc_fwnmi()) { + error_setg(errp, +"Firmware Assisted Non-Maskable Interrupts not supported by KVM, try cap-f= wnmi-mce=3Doff"); + } +} + SpaprCapabilityInfo capability_table[SPAPR_CAP_NUM] =3D { [SPAPR_CAP_HTM] =3D { .name =3D "htm", @@ -580,6 +599,15 @@ SpaprCapabilityInfo capability_table[SPAPR_CAP_NUM] = =3D { .type =3D "bool", .apply =3D cap_ccf_assist_apply, }, + [SPAPR_CAP_FWNMI_MCE] =3D { + .name =3D "fwnmi-mce", + .description =3D "Handle fwnmi machine check exceptions", + .index =3D SPAPR_CAP_FWNMI_MCE, + .get =3D spapr_cap_get_bool, + .set =3D spapr_cap_set_bool, + .type =3D "bool", + .apply =3D cap_fwnmi_mce_apply, + }, }; =20 static SpaprCapabilities default_caps_with_cpu(SpaprMachineState *spapr, @@ -719,6 +747,7 @@ SPAPR_CAP_MIG_STATE(hpt_maxpagesize, SPAPR_CAP_HPT_MAXP= AGESIZE); SPAPR_CAP_MIG_STATE(nested_kvm_hv, SPAPR_CAP_NESTED_KVM_HV); SPAPR_CAP_MIG_STATE(large_decr, SPAPR_CAP_LARGE_DECREMENTER); SPAPR_CAP_MIG_STATE(ccf_assist, SPAPR_CAP_CCF_ASSIST); +SPAPR_CAP_MIG_STATE(fwnmi, SPAPR_CAP_FWNMI_MCE); =20 void spapr_caps_init(SpaprMachineState *spapr) { diff --git a/include/hw/ppc/spapr.h b/include/hw/ppc/spapr.h index fa7c380..01c106f 100644 --- a/include/hw/ppc/spapr.h +++ b/include/hw/ppc/spapr.h @@ -79,8 +79,10 @@ typedef enum { #define SPAPR_CAP_LARGE_DECREMENTER 0x08 /* Count Cache Flush Assist HW Instruction */ #define SPAPR_CAP_CCF_ASSIST 0x09 +/* FWNMI machine check handling */ +#define SPAPR_CAP_FWNMI_MCE 0x0A /* Num Caps */ -#define SPAPR_CAP_NUM (SPAPR_CAP_CCF_ASSIST + 1) +#define SPAPR_CAP_NUM (SPAPR_CAP_FWNMI_MCE + 1) =20 /* * Capability Values diff --git a/target/ppc/kvm.c b/target/ppc/kvm.c index 5ab5e6c..c922bcb 100644 --- a/target/ppc/kvm.c +++ b/target/ppc/kvm.c @@ -83,6 +83,7 @@ static int cap_ppc_safe_indirect_branch; static int cap_ppc_count_cache_flush_assist; static int cap_ppc_nested_kvm_hv; static int cap_large_decr; +static int cap_ppc_fwnmi; =20 static uint32_t debug_inst_opcode; =20 @@ -2053,6 +2054,22 @@ void kvmppc_set_mpic_proxy(PowerPCCPU *cpu, int mpic= _proxy) } } =20 +int kvmppc_set_fwnmi(void) +{ + PowerPCCPU *cpu =3D POWERPC_CPU(first_cpu); + CPUState *cs =3D CPU(cpu); + int ret; + + ret =3D kvm_vcpu_enable_cap(cs, KVM_CAP_PPC_FWNMI, 0); + if (ret) { + error_report("This KVM version does not support FWNMI"); + return ret; + } + + cap_ppc_fwnmi =3D 1; + return ret; +} + int kvmppc_smt_threads(void) { return cap_ppc_smt ? cap_ppc_smt : 1; @@ -2353,6 +2370,11 @@ bool kvmppc_has_cap_mmu_hash_v3(void) return cap_mmu_hash_v3; } =20 +bool kvmppc_has_cap_ppc_fwnmi(void) +{ + return cap_ppc_fwnmi; +} + static bool kvmppc_power8_host(void) { bool ret =3D false; diff --git a/target/ppc/kvm_ppc.h b/target/ppc/kvm_ppc.h index 98bd7d5..2990898 100644 --- a/target/ppc/kvm_ppc.h +++ b/target/ppc/kvm_ppc.h @@ -27,6 +27,8 @@ void kvmppc_enable_h_page_init(void); void kvmppc_set_papr(PowerPCCPU *cpu); int kvmppc_set_compat(PowerPCCPU *cpu, uint32_t compat_pvr); void kvmppc_set_mpic_proxy(PowerPCCPU *cpu, int mpic_proxy); +int kvmppc_set_fwnmi(void); +bool kvmppc_has_cap_ppc_fwnmi(void); int kvmppc_smt_threads(void); void kvmppc_hint_smt_possible(Error **errp); int kvmppc_set_smt_threads(int smt); @@ -159,6 +161,15 @@ static inline void kvmppc_set_mpic_proxy(PowerPCCPU *c= pu, int mpic_proxy) { } =20 +static inline int kvmppc_set_fwnmi(void) +{ +} + +static inline bool kvmppc_has_cap_ppc_fwnmi(void) +{ + return false; +} + static inline int kvmppc_smt_threads(void) { return 1; From nobody Thu Mar 28 22:22:47 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; 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Wed, 14 Aug 2019 06:11:17 +0000 (GMT) From: Aravinda Prasad To: aik@au1.ibm.com, qemu-ppc@nongnu.org, qemu-devel@nongnu.org, david@gibson.dropbear.id.au Date: Wed, 14 Aug 2019 11:41:16 +0530 Message-ID: <156576307653.29984.11318539963120745329.stgit@aravinda> In-Reply-To: <156576293464.29984.1631520917528142744.stgit@aravinda> References: <156576293464.29984.1631520917528142744.stgit@aravinda> User-Agent: StGit/0.17.1-dirty MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2019-08-14_02:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=0 phishscore=0 bulkscore=0 spamscore=0 clxscore=1015 lowpriorityscore=0 mlxscore=0 impostorscore=0 mlxlogscore=999 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1906280000 definitions=main-1908140060 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [generic] X-Received-From: 148.163.158.5 Subject: [Qemu-devel] [patch-for-4.2 PATCH v11 3/6] target/ppc: Handle NMI guest exit X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: paulus@ozlabs.org, aravinda@linux.vnet.ibm.com, groug@kaod.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Memory error such as bit flips that cannot be corrected by hardware are passed on to the kernel for handling. If the memory address in error belongs to guest then the guest kernel is responsible for taking suitable action. Patch [1] enhances KVM to exit guest with exit reason set to KVM_EXIT_NMI in such cases. This patch handles KVM_EXIT_NMI exit. [1] https://www.spinics.net/lists/kvm-ppc/msg12637.html (e20bbd3d and related commits) Signed-off-by: Aravinda Prasad Reviewed-by: David Gibson --- hw/ppc/spapr.c | 8 ++++++++ hw/ppc/spapr_events.c | 23 +++++++++++++++++++++++ include/hw/ppc/spapr.h | 10 ++++++++++ target/ppc/kvm.c | 14 ++++++++++++++ target/ppc/kvm_ppc.h | 2 ++ target/ppc/trace-events | 1 + 6 files changed, 58 insertions(+) diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c index 07714cb..99def34 100644 --- a/hw/ppc/spapr.c +++ b/hw/ppc/spapr.c @@ -1813,6 +1813,12 @@ static void spapr_machine_reset(MachineState *machin= e) first_ppc_cpu->env.gpr[5] =3D 0; =20 spapr->cas_reboot =3D false; + + spapr->mc_status =3D -1; + spapr->guest_machine_check_addr =3D -1; + + /* Signal all vCPUs waiting on this condition */ + qemu_cond_broadcast(&spapr->mc_delivery_cond); } =20 static void spapr_create_nvram(SpaprMachineState *spapr) @@ -3089,6 +3095,8 @@ static void spapr_machine_init(MachineState *machine) =20 kvmppc_spapr_enable_inkernel_multitce(); } + + qemu_cond_init(&spapr->mc_delivery_cond); } =20 static int spapr_kvm_type(MachineState *machine, const char *vm_type) diff --git a/hw/ppc/spapr_events.c b/hw/ppc/spapr_events.c index ae0f093..a0c66d7 100644 --- a/hw/ppc/spapr_events.c +++ b/hw/ppc/spapr_events.c @@ -620,6 +620,29 @@ void spapr_hotplug_req_remove_by_count_indexed(SpaprDr= cType drc_type, RTAS_LOG_V6_HP_ACTION_REMOVE, drc_type, &drc_i= d); } =20 +void spapr_mce_req_event(PowerPCCPU *cpu) +{ + SpaprMachineState *spapr =3D SPAPR_MACHINE(qdev_get_machine()); + + while (spapr->mc_status !=3D -1) { + /* + * Check whether the same CPU got machine check error + * while still handling the mc error (i.e., before + * that CPU called "ibm,nmi-interlock") + */ + if (spapr->mc_status =3D=3D cpu->vcpu_id) { + qemu_system_guest_panicked(NULL); + return; + } + qemu_cond_wait_iothread(&spapr->mc_delivery_cond); + /* Meanwhile if the system is reset, then just return */ + if (spapr->guest_machine_check_addr =3D=3D -1) { + return; + } + } + spapr->mc_status =3D cpu->vcpu_id; +} + static void check_exception(PowerPCCPU *cpu, SpaprMachineState *spapr, uint32_t token, uint32_t nargs, target_ulong args, diff --git a/include/hw/ppc/spapr.h b/include/hw/ppc/spapr.h index 01c106f..619677a 100644 --- a/include/hw/ppc/spapr.h +++ b/include/hw/ppc/spapr.h @@ -191,6 +191,15 @@ struct SpaprMachineState { * occurs during the unplug process. */ QTAILQ_HEAD(, SpaprDimmState) pending_dimm_unplugs; =20 + /* State related to "ibm,nmi-register" and "ibm,nmi-interlock" calls */ + target_ulong guest_machine_check_addr; + /* + * mc_status is set to -1 if mc is not in progress, else is set to the= CPU + * handling the mc. + */ + int mc_status; + QemuCond mc_delivery_cond; + /*< public >*/ char *kvm_type; char *host_model; @@ -804,6 +813,7 @@ void spapr_clear_pending_events(SpaprMachineState *spap= r); int spapr_max_server_number(SpaprMachineState *spapr); void spapr_store_hpte(PowerPCCPU *cpu, hwaddr ptex, uint64_t pte0, uint64_t pte1); +void spapr_mce_req_event(PowerPCCPU *cpu); =20 /* DRC callbacks. */ void spapr_core_release(DeviceState *dev); diff --git a/target/ppc/kvm.c b/target/ppc/kvm.c index c922bcb..375dc09 100644 --- a/target/ppc/kvm.c +++ b/target/ppc/kvm.c @@ -1702,6 +1702,11 @@ int kvm_arch_handle_exit(CPUState *cs, struct kvm_ru= n *run) ret =3D 0; break; =20 + case KVM_EXIT_NMI: + trace_kvm_handle_nmi_exception(); + ret =3D kvm_handle_nmi(cpu, run); + break; + default: fprintf(stderr, "KVM: unknown exit reason %d\n", run->exit_reason); ret =3D -1; @@ -2805,6 +2810,15 @@ int kvm_arch_msi_data_to_gsi(uint32_t data) return data & 0xffff; } =20 +int kvm_handle_nmi(PowerPCCPU *cpu, struct kvm_run *run) +{ + cpu_synchronize_state(CPU(cpu)); + + spapr_mce_req_event(cpu); + + return 0; +} + int kvmppc_enable_hwrng(void) { if (!kvm_enabled() || !kvm_check_extension(kvm_state, KVM_CAP_PPC_HWRN= G)) { diff --git a/target/ppc/kvm_ppc.h b/target/ppc/kvm_ppc.h index 2990898..173c000 100644 --- a/target/ppc/kvm_ppc.h +++ b/target/ppc/kvm_ppc.h @@ -84,6 +84,8 @@ void kvm_check_mmu(PowerPCCPU *cpu, Error **errp); void kvmppc_set_reg_ppc_online(PowerPCCPU *cpu, unsigned int online); void kvmppc_set_reg_tb_offset(PowerPCCPU *cpu, int64_t tb_offset); =20 +int kvm_handle_nmi(PowerPCCPU *cpu, struct kvm_run *run); + #else =20 static inline uint32_t kvmppc_get_tbfreq(void) diff --git a/target/ppc/trace-events b/target/ppc/trace-events index 3dc6740..6d15aa9 100644 --- a/target/ppc/trace-events +++ b/target/ppc/trace-events @@ -28,3 +28,4 @@ kvm_handle_papr_hcall(void) "handle PAPR hypercall" kvm_handle_epr(void) "handle epr" kvm_handle_watchdog_expiry(void) "handle watchdog expiry" kvm_handle_debug_exception(void) "handle debug exception" +kvm_handle_nmi_exception(void) "handle NMI exception" From nobody Thu Mar 28 22:22:47 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; 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Wed, 14 Aug 2019 06:11:25 +0000 (GMT) Received: from [127.0.1.1] (unknown [9.124.31.79]) by b03ledav005.gho.boulder.ibm.com (Postfix) with ESMTP; Wed, 14 Aug 2019 06:11:25 +0000 (GMT) From: Aravinda Prasad To: aik@au1.ibm.com, qemu-ppc@nongnu.org, qemu-devel@nongnu.org, david@gibson.dropbear.id.au Date: Wed, 14 Aug 2019 11:41:24 +0530 Message-ID: <156576308472.29984.2031846105883673373.stgit@aravinda> In-Reply-To: <156576293464.29984.1631520917528142744.stgit@aravinda> References: <156576293464.29984.1631520917528142744.stgit@aravinda> User-Agent: StGit/0.17.1-dirty MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2019-08-14_02:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=2 phishscore=0 bulkscore=0 spamscore=0 clxscore=1015 lowpriorityscore=0 mlxscore=0 impostorscore=0 mlxlogscore=999 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1906280000 definitions=main-1908140060 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [generic] X-Received-From: 148.163.156.1 Subject: [Qemu-devel] [patch-for-4.2 PATCH v11 4/6] target/ppc: Build rtas error log upon an MCE X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: paulus@ozlabs.org, aravinda@linux.vnet.ibm.com, groug@kaod.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Upon a machine check exception (MCE) in a guest address space, KVM causes a guest exit to enable QEMU to build and pass the error to the guest in the PAPR defined rtas error log format. This patch builds the rtas error log, copies it to the rtas_addr and then invokes the guest registered machine check handler. The handler in the guest takes suitable action(s) depending on the type and criticality of the error. For example, if an error is unrecoverable memory corruption in an application inside the guest, then the guest kernel sends a SIGBUS to the application. For recoverable errors, the guest performs recovery actions and logs the error. Signed-off-by: Aravinda Prasad --- hw/ppc/spapr.c | 13 +++ hw/ppc/spapr_events.c | 233 ++++++++++++++++++++++++++++++++++++++++++++= ++++ hw/ppc/spapr_rtas.c | 26 +++++ include/hw/ppc/spapr.h | 6 + target/ppc/cpu.h | 1=20 target/ppc/kvm.c | 4 + 6 files changed, 280 insertions(+), 3 deletions(-) diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c index 99def34..27ea679 100644 --- a/hw/ppc/spapr.c +++ b/hw/ppc/spapr.c @@ -2920,6 +2920,19 @@ static void spapr_machine_init(MachineState *machine) error_report("Could not get size of LPAR rtas '%s'", filename); exit(1); } + + if (spapr_get_cap(spapr, SPAPR_CAP_FWNMI_MCE) =3D=3D SPAPR_CAP_ON) { + /* + * Ensure that the rtas image size is less than RTAS_ERROR_LOG_OFF= SET + * or else the rtas image will be overwritten with the rtas error = log + * when a machine check exception is encountered. + */ + g_assert(spapr->rtas_size < RTAS_ERROR_LOG_OFFSET); + + /* Resize rtas blob to accommodate error log */ + spapr->rtas_size =3D RTAS_ERROR_LOG_MAX; + } + spapr->rtas_blob =3D g_malloc(spapr->rtas_size); if (load_image_size(filename, spapr->rtas_blob, spapr->rtas_size) < 0)= { error_report("Could not load LPAR rtas '%s'", filename); diff --git a/hw/ppc/spapr_events.c b/hw/ppc/spapr_events.c index a0c66d7..b2baca9 100644 --- a/hw/ppc/spapr_events.c +++ b/hw/ppc/spapr_events.c @@ -212,6 +212,106 @@ struct hp_extended_log { struct rtas_event_log_v6_hp hp; } QEMU_PACKED; =20 +struct rtas_event_log_v6_mc { +#define RTAS_LOG_V6_SECTION_ID_MC 0x4D43 /* MC */ + struct rtas_event_log_v6_section_header hdr; + uint32_t fru_id; + uint32_t proc_id; + uint8_t error_type; +#define RTAS_LOG_V6_MC_TYPE_UE 0 +#define RTAS_LOG_V6_MC_TYPE_SLB 1 +#define RTAS_LOG_V6_MC_TYPE_ERAT 2 +#define RTAS_LOG_V6_MC_TYPE_TLB 4 +#define RTAS_LOG_V6_MC_TYPE_D_CACHE 5 +#define RTAS_LOG_V6_MC_TYPE_I_CACHE 7 + uint8_t sub_err_type; +#define RTAS_LOG_V6_MC_UE_INDETERMINATE 0 +#define RTAS_LOG_V6_MC_UE_IFETCH 1 +#define RTAS_LOG_V6_MC_UE_PAGE_TABLE_WALK_IFETCH 2 +#define RTAS_LOG_V6_MC_UE_LOAD_STORE 3 +#define RTAS_LOG_V6_MC_UE_PAGE_TABLE_WALK_LOAD_STORE 4 +#define RTAS_LOG_V6_MC_SLB_PARITY 0 +#define RTAS_LOG_V6_MC_SLB_MULTIHIT 1 +#define RTAS_LOG_V6_MC_SLB_INDETERMINATE 2 +#define RTAS_LOG_V6_MC_ERAT_PARITY 1 +#define RTAS_LOG_V6_MC_ERAT_MULTIHIT 2 +#define RTAS_LOG_V6_MC_ERAT_INDETERMINATE 3 +#define RTAS_LOG_V6_MC_TLB_PARITY 1 +#define RTAS_LOG_V6_MC_TLB_MULTIHIT 2 +#define RTAS_LOG_V6_MC_TLB_INDETERMINATE 3 + uint8_t reserved_1[6]; + uint64_t effective_address; + uint64_t logical_address; +} QEMU_PACKED; + +struct mc_extended_log { + struct rtas_event_log_v6 v6hdr; + struct rtas_event_log_v6_mc mc; +} QEMU_PACKED; + +struct MC_ierror_table { + unsigned long srr1_mask; + unsigned long srr1_value; + bool nip_valid; /* nip is a valid indicator of faulting address */ + uint8_t error_type; + uint8_t error_subtype; + unsigned int initiator; + unsigned int severity; +}; + +static const struct MC_ierror_table mc_ierror_table[] =3D { +{ 0x00000000081c0000, 0x0000000000040000, true, + RTAS_LOG_V6_MC_TYPE_UE, RTAS_LOG_V6_MC_UE_IFETCH, + RTAS_LOG_INITIATOR_CPU, RTAS_LOG_SEVERITY_ERROR_SYNC, }, +{ 0x00000000081c0000, 0x0000000000080000, true, + RTAS_LOG_V6_MC_TYPE_SLB, RTAS_LOG_V6_MC_SLB_PARITY, + RTAS_LOG_INITIATOR_CPU, RTAS_LOG_SEVERITY_ERROR_SYNC, }, +{ 0x00000000081c0000, 0x00000000000c0000, true, + RTAS_LOG_V6_MC_TYPE_SLB, RTAS_LOG_V6_MC_SLB_MULTIHIT, + RTAS_LOG_INITIATOR_CPU, RTAS_LOG_SEVERITY_ERROR_SYNC, }, +{ 0x00000000081c0000, 0x0000000000100000, true, + RTAS_LOG_V6_MC_TYPE_ERAT, RTAS_LOG_V6_MC_ERAT_MULTIHIT, + RTAS_LOG_INITIATOR_CPU, RTAS_LOG_SEVERITY_ERROR_SYNC, }, +{ 0x00000000081c0000, 0x0000000000140000, true, + RTAS_LOG_V6_MC_TYPE_TLB, RTAS_LOG_V6_MC_TLB_MULTIHIT, + RTAS_LOG_INITIATOR_CPU, RTAS_LOG_SEVERITY_ERROR_SYNC, }, +{ 0x00000000081c0000, 0x0000000000180000, true, + RTAS_LOG_V6_MC_TYPE_UE, RTAS_LOG_V6_MC_UE_PAGE_TABLE_WALK_IFETCH, + RTAS_LOG_INITIATOR_CPU, RTAS_LOG_SEVERITY_ERROR_SYNC, }, +{ 0, 0, 0, 0, 0, 0 } }; + +struct MC_derror_table { + unsigned long dsisr_value; + bool dar_valid; /* dar is a valid indicator of faulting address */ + uint8_t error_type; + uint8_t error_subtype; + unsigned int initiator; + unsigned int severity; +}; + +static const struct MC_derror_table mc_derror_table[] =3D { +{ 0x00008000, false, + RTAS_LOG_V6_MC_TYPE_UE, RTAS_LOG_V6_MC_UE_LOAD_STORE, + RTAS_LOG_INITIATOR_CPU, RTAS_LOG_SEVERITY_ERROR_SYNC, }, +{ 0x00004000, true, + RTAS_LOG_V6_MC_TYPE_UE, RTAS_LOG_V6_MC_UE_PAGE_TABLE_WALK_LOAD_STORE, + RTAS_LOG_INITIATOR_CPU, RTAS_LOG_SEVERITY_ERROR_SYNC, }, +{ 0x00000800, true, + RTAS_LOG_V6_MC_TYPE_ERAT, RTAS_LOG_V6_MC_ERAT_MULTIHIT, + RTAS_LOG_INITIATOR_CPU, RTAS_LOG_SEVERITY_ERROR_SYNC, }, +{ 0x00000400, true, + RTAS_LOG_V6_MC_TYPE_TLB, RTAS_LOG_V6_MC_TLB_MULTIHIT, + RTAS_LOG_INITIATOR_CPU, RTAS_LOG_SEVERITY_ERROR_SYNC, }, +{ 0x00000080, true, + RTAS_LOG_V6_MC_TYPE_SLB, RTAS_LOG_V6_MC_SLB_MULTIHIT, /* Before PARITY = */ + RTAS_LOG_INITIATOR_CPU, RTAS_LOG_SEVERITY_ERROR_SYNC, }, +{ 0x00000100, true, + RTAS_LOG_V6_MC_TYPE_SLB, RTAS_LOG_V6_MC_SLB_PARITY, + RTAS_LOG_INITIATOR_CPU, RTAS_LOG_SEVERITY_ERROR_SYNC, }, +{ 0, false, 0, 0, 0, 0 } }; + +#define SRR1_MC_LOADSTORE(srr1) ((srr1) & PPC_BIT(42)) + typedef enum EventClass { EVENT_CLASS_INTERNAL_ERRORS =3D 0, EVENT_CLASS_EPOW =3D 1, @@ -620,7 +720,136 @@ void spapr_hotplug_req_remove_by_count_indexed(SpaprD= rcType drc_type, RTAS_LOG_V6_HP_ACTION_REMOVE, drc_type, &drc_i= d); } =20 -void spapr_mce_req_event(PowerPCCPU *cpu) +static uint32_t spapr_mce_get_elog_type(PowerPCCPU *cpu, bool recovered, + struct mc_extended_log *ext_elog) +{ + int i; + CPUPPCState *env =3D &cpu->env; + uint32_t summary; + uint64_t dsisr =3D env->spr[SPR_DSISR]; + + summary =3D RTAS_LOG_VERSION_6 | RTAS_LOG_OPTIONAL_PART_PRESENT; + if (recovered) { + summary |=3D RTAS_LOG_DISPOSITION_FULLY_RECOVERED; + } else { + summary |=3D RTAS_LOG_DISPOSITION_NOT_RECOVERED; + } + + if (SRR1_MC_LOADSTORE(env->spr[SPR_SRR1])) { + for (i =3D 0; mc_derror_table[i].dsisr_value; i++) { + if (!(dsisr & mc_derror_table[i].dsisr_value)) { + continue; + } + + ext_elog->mc.error_type =3D mc_derror_table[i].error_type; + ext_elog->mc.sub_err_type =3D mc_derror_table[i].error_subtype; + if (mc_derror_table[i].dar_valid) { + ext_elog->mc.effective_address =3D cpu_to_be64(env->spr[SP= R_DAR]); + } + + summary |=3D mc_derror_table[i].initiator + | mc_derror_table[i].severity; + + return summary; + } + } else { + for (i =3D 0; mc_ierror_table[i].srr1_mask; i++) { + if ((env->spr[SPR_SRR1] & mc_ierror_table[i].srr1_mask) !=3D + mc_ierror_table[i].srr1_value) { + continue; + } + + ext_elog->mc.error_type =3D mc_ierror_table[i].error_type; + ext_elog->mc.sub_err_type =3D mc_ierror_table[i].error_subtype; + if (mc_ierror_table[i].nip_valid) { + ext_elog->mc.effective_address =3D cpu_to_be64(env->nip); + } + + summary |=3D mc_ierror_table[i].initiator + | mc_ierror_table[i].severity; + + return summary; + } + } + + summary |=3D RTAS_LOG_INITIATOR_CPU; + return summary; +} + +static void spapr_mce_dispatch_elog(PowerPCCPU *cpu, bool recovered) +{ + SpaprMachineState *spapr =3D SPAPR_MACHINE(qdev_get_machine()); + CPUState *cs =3D CPU(cpu); + uint64_t rtas_addr; + CPUPPCState *env =3D &cpu->env; + PowerPCCPUClass *pcc =3D POWERPC_CPU_GET_CLASS(cpu); + target_ulong msr =3D 0; + struct rtas_error_log log; + struct mc_extended_log *ext_elog; + uint32_t summary; + + /* + * Properly set bits in MSR before we invoke the handler. + * SRR0/1, DAR and DSISR are properly set by KVM + */ + if (!(*pcc->interrupts_big_endian)(cpu)) { + msr |=3D (1ULL << MSR_LE); + } + + if (env->msr & (1ULL << MSR_SF)) { + msr |=3D (1ULL << MSR_SF); + } + + msr |=3D (1ULL << MSR_ME); + + if (spapr->guest_machine_check_addr =3D=3D -1) { + /* + * This implies that we have hit a machine check between system + * reset and "ibm,nmi-register". Fall back to the old machine + * check behavior in such cases. + */ + cs->exception_index =3D POWERPC_EXCP_MCHECK; + ppc_cpu_do_interrupt(cs); + return; + } + + ext_elog =3D g_malloc0(sizeof(*ext_elog)); + summary =3D spapr_mce_get_elog_type(cpu, recovered, ext_elog); + + log.summary =3D cpu_to_be32(summary); + log.extended_length =3D cpu_to_be32(sizeof(*ext_elog)); + + spapr_init_v6hdr(&ext_elog->v6hdr); + ext_elog->mc.hdr.section_id =3D cpu_to_be16(RTAS_LOG_V6_SECTION_ID_MC); + ext_elog->mc.hdr.section_length =3D + cpu_to_be16(sizeof(struct rtas_event_log_v6_mc)); + ext_elog->mc.hdr.section_version =3D 1; + + /* get rtas addr from fdt */ + rtas_addr =3D spapr_get_rtas_addr(); + if (!rtas_addr) { + /* Unable to fetch rtas_addr. Hence reset the guest */ + ppc_cpu_do_system_reset(cs); + g_free(ext_elog); + return; + } + + stq_be_phys(&address_space_memory, rtas_addr + RTAS_ERROR_LOG_OFFSET, + env->gpr[3]); + cpu_physical_memory_write(rtas_addr + RTAS_ERROR_LOG_OFFSET + + sizeof(env->gpr[3]), &log, sizeof(log)); + cpu_physical_memory_write(rtas_addr + RTAS_ERROR_LOG_OFFSET + + sizeof(env->gpr[3]) + sizeof(log), ext_elog, + sizeof(*ext_elog)); + + env->gpr[3] =3D rtas_addr + RTAS_ERROR_LOG_OFFSET; + env->msr =3D msr; + env->nip =3D spapr->guest_machine_check_addr; + + g_free(ext_elog); +} + +void spapr_mce_req_event(PowerPCCPU *cpu, bool recovered) { SpaprMachineState *spapr =3D SPAPR_MACHINE(qdev_get_machine()); =20 @@ -641,6 +870,8 @@ void spapr_mce_req_event(PowerPCCPU *cpu) } } spapr->mc_status =3D cpu->vcpu_id; + + spapr_mce_dispatch_elog(cpu, recovered); } =20 static void check_exception(PowerPCCPU *cpu, SpaprMachineState *spapr, diff --git a/hw/ppc/spapr_rtas.c b/hw/ppc/spapr_rtas.c index 87175c1..bb650e0 100644 --- a/hw/ppc/spapr_rtas.c +++ b/hw/ppc/spapr_rtas.c @@ -502,6 +502,32 @@ void spapr_load_rtas(SpaprMachineState *spapr, void *f= dt, hwaddr addr) } } =20 +hwaddr spapr_get_rtas_addr(void) +{ + SpaprMachineState *spapr =3D SPAPR_MACHINE(qdev_get_machine()); + int rtas_node; + const fdt32_t *rtas_data; + void *fdt =3D spapr->fdt_blob; + + /* fetch rtas addr from fdt */ + rtas_node =3D fdt_path_offset(fdt, "/rtas"); + if (rtas_node < 0) { + return 0; + } + + rtas_data =3D fdt_getprop(fdt, rtas_node, "linux,rtas-base", NULL); + if (!rtas_data) { + return 0; + } + + /* + * We assume that the OS called RTAS instantiate-rtas, but some other + * OS might call RTAS instantiate-rtas-64 instead. This fine as of now + * as SLOF only supports 32-bit variant. + */ + return (hwaddr)fdt32_to_cpu(*rtas_data); +} + static void core_rtas_register_types(void) { spapr_rtas_register(RTAS_DISPLAY_CHARACTER, "display-character", diff --git a/include/hw/ppc/spapr.h b/include/hw/ppc/spapr.h index 619677a..47f05f2 100644 --- a/include/hw/ppc/spapr.h +++ b/include/hw/ppc/spapr.h @@ -725,6 +725,9 @@ void spapr_load_rtas(SpaprMachineState *spapr, void *fd= t, hwaddr addr); =20 #define RTAS_ERROR_LOG_MAX 2048 =20 +/* Offset from rtas-base where error log is placed */ +#define RTAS_ERROR_LOG_OFFSET 0x30 + #define RTAS_EVENT_SCAN_RATE 1 =20 /* This helper should be used to encode interrupt specifiers when the rela= ted @@ -813,7 +816,7 @@ void spapr_clear_pending_events(SpaprMachineState *spap= r); int spapr_max_server_number(SpaprMachineState *spapr); void spapr_store_hpte(PowerPCCPU *cpu, hwaddr ptex, uint64_t pte0, uint64_t pte1); -void spapr_mce_req_event(PowerPCCPU *cpu); +void spapr_mce_req_event(PowerPCCPU *cpu, bool recovered); =20 /* DRC callbacks. */ void spapr_core_release(DeviceState *dev); @@ -903,4 +906,5 @@ void spapr_check_pagesize(SpaprMachineState *spapr, hwa= ddr pagesize, #define SPAPR_OV5_XIVE_BOTH 0x80 /* Only to advertise on the platform = */ =20 void spapr_set_all_lpcrs(target_ulong value, target_ulong mask); +hwaddr spapr_get_rtas_addr(void); #endif /* HW_SPAPR_H */ diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 6479938..d9fa639 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -1259,6 +1259,7 @@ int ppc32_cpu_write_elf32_note(WriteCoreDumpFunction = f, CPUState *cs, int cpuid, void *opaque); #ifndef CONFIG_USER_ONLY void ppc_cpu_do_system_reset(CPUState *cs); +void ppc_cpu_do_machine_check(CPUState *cs); extern const struct VMStateDescription vmstate_ppc_cpu; #endif =20 diff --git a/target/ppc/kvm.c b/target/ppc/kvm.c index 375dc09..875d3da 100644 --- a/target/ppc/kvm.c +++ b/target/ppc/kvm.c @@ -2812,9 +2812,11 @@ int kvm_arch_msi_data_to_gsi(uint32_t data) =20 int kvm_handle_nmi(PowerPCCPU *cpu, struct kvm_run *run) { + bool recovered =3D run->flags & KVM_RUN_PPC_NMI_DISP_FULLY_RECOV; + cpu_synchronize_state(CPU(cpu)); =20 - spapr_mce_req_event(cpu); + spapr_mce_req_event(cpu, recovered); =20 return 0; } From nobody Thu Mar 28 22:22:47 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1565763220; cv=none; d=zoho.com; s=zohoarc; b=hnXjsJb+YcNxfQog1JndN4alR5TvhaOj4mIahdZAaQYSTFv5nq9xUDpIy+qi7gjgOZoVVTtYJgbJiiK8hgbkHH99D0XQKm6kpWKndkTUWddKVnGP0op1I6e0l6vGA9fWOs+gye+/tyN901PLN7hZWbuXSNDrxXfPeu5IdX8wQPM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1565763220; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; 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Wed, 14 Aug 2019 06:11:38 +0000 Received: from b03ledav006.gho.boulder.ibm.com (b03ledav006.gho.boulder.ibm.com [9.17.130.237]) by b03cxnp08025.gho.boulder.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id x7E6BbaL50004416 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Wed, 14 Aug 2019 06:11:37 GMT Received: from b03ledav006.gho.boulder.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 2F457C605A; Wed, 14 Aug 2019 06:11:37 +0000 (GMT) Received: from b03ledav006.gho.boulder.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id D09EBC6055; Wed, 14 Aug 2019 06:11:34 +0000 (GMT) Received: from [127.0.1.1] (unknown [9.124.31.79]) by b03ledav006.gho.boulder.ibm.com (Postfix) with ESMTP; Wed, 14 Aug 2019 06:11:34 +0000 (GMT) From: Aravinda Prasad To: aik@au1.ibm.com, qemu-ppc@nongnu.org, qemu-devel@nongnu.org, david@gibson.dropbear.id.au Date: Wed, 14 Aug 2019 11:41:33 +0530 Message-ID: <156576309362.29984.4496351195831814883.stgit@aravinda> In-Reply-To: <156576293464.29984.1631520917528142744.stgit@aravinda> References: <156576293464.29984.1631520917528142744.stgit@aravinda> User-Agent: StGit/0.17.1-dirty MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2019-08-14_02:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=0 phishscore=0 bulkscore=0 spamscore=0 clxscore=1015 lowpriorityscore=0 mlxscore=0 impostorscore=0 mlxlogscore=999 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1906280000 definitions=main-1908140060 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [generic] X-Received-From: 148.163.158.5 Subject: [Qemu-devel] [patch-for-4.2 PATCH v11 5/6] ppc: spapr: Handle "ibm, nmi-register" and "ibm, nmi-interlock" RTAS calls X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: paulus@ozlabs.org, aravinda@linux.vnet.ibm.com, groug@kaod.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" This patch adds support in QEMU to handle "ibm,nmi-register" and "ibm,nmi-interlock" RTAS calls and sets the default value of SPAPR_CAP_FWNMI_MCE to SPAPR_CAP_ON for machine type 4.2. The machine check notification address is saved when the OS issues "ibm,nmi-register" RTAS call. This patch also handles the case when multiple processors experience machine check at or about the same time by handling "ibm,nmi-interlock" call. In such cases, as per PAPR, subsequent processors serialize waiting for the first processor to issue the "ibm,nmi-interlock" call. The second processor that also received a machine check error waits till the first processor is done reading the error log. The first processor issues "ibm,nmi-interlock" call when the error log is consumed. Signed-off-by: Aravinda Prasad --- hw/ppc/spapr.c | 14 ++++++++++++- hw/ppc/spapr_rtas.c | 50 ++++++++++++++++++++++++++++++++++++++++++++= ++++ include/hw/ppc/spapr.h | 5 ++++- 3 files changed, 67 insertions(+), 2 deletions(-) diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c index 27ea679..04d7ac6 100644 --- a/hw/ppc/spapr.c +++ b/hw/ppc/spapr.c @@ -2931,6 +2931,15 @@ static void spapr_machine_init(MachineState *machine) =20 /* Resize rtas blob to accommodate error log */ spapr->rtas_size =3D RTAS_ERROR_LOG_MAX; + + /* Set fwnmi capability in KVM */ + if (kvmppc_set_fwnmi() < 0) { + error_report("Could not enable FWNMI capability"); + exit(1); + } + + /* Register ibm,nmi-register and ibm,nmi-interlock RTAS calls */ + spapr_fwnmi_register(); } =20 spapr->rtas_blob =3D g_malloc(spapr->rtas_size); @@ -4484,7 +4493,7 @@ static void spapr_machine_class_init(ObjectClass *oc,= void *data) smc->default_caps.caps[SPAPR_CAP_NESTED_KVM_HV] =3D SPAPR_CAP_OFF; smc->default_caps.caps[SPAPR_CAP_LARGE_DECREMENTER] =3D SPAPR_CAP_ON; smc->default_caps.caps[SPAPR_CAP_CCF_ASSIST] =3D SPAPR_CAP_OFF; - smc->default_caps.caps[SPAPR_CAP_FWNMI_MCE] =3D SPAPR_CAP_OFF; + smc->default_caps.caps[SPAPR_CAP_FWNMI_MCE] =3D SPAPR_CAP_ON; spapr_caps_add_properties(smc, &error_abort); smc->irq =3D &spapr_irq_dual; smc->dr_phb_enabled =3D true; @@ -4547,6 +4556,8 @@ DEFINE_SPAPR_MACHINE(4_2, "4.2", true); */ static void spapr_machine_4_1_class_options(MachineClass *mc) { + SpaprMachineClass *smc =3D SPAPR_MACHINE_CLASS(mc); + static GlobalProperty compat[] =3D { /* Only allow 4kiB and 64kiB IOMMU pagesizes */ { TYPE_SPAPR_PCI_HOST_BRIDGE, "pgsz", "0x11000" }, @@ -4555,6 +4566,7 @@ static void spapr_machine_4_1_class_options(MachineCl= ass *mc) spapr_machine_4_2_class_options(mc); compat_props_add(mc->compat_props, hw_compat_4_1, hw_compat_4_1_len); compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); + smc->default_caps.caps[SPAPR_CAP_FWNMI_MCE] =3D SPAPR_CAP_OFF; } =20 DEFINE_SPAPR_MACHINE(4_1, "4.1", false); diff --git a/hw/ppc/spapr_rtas.c b/hw/ppc/spapr_rtas.c index bb650e0..e4639a4 100644 --- a/hw/ppc/spapr_rtas.c +++ b/hw/ppc/spapr_rtas.c @@ -384,6 +384,48 @@ static void rtas_get_power_level(PowerPCCPU *cpu, Spap= rMachineState *spapr, rtas_st(rets, 1, 100); } =20 +static void rtas_ibm_nmi_register(PowerPCCPU *cpu, + SpaprMachineState *spapr, + uint32_t token, uint32_t nargs, + target_ulong args, + uint32_t nret, target_ulong rets) +{ + hwaddr rtas_addr =3D spapr_get_rtas_addr(); + + if (!rtas_addr) { + rtas_st(rets, 0, RTAS_OUT_NOT_SUPPORTED); + return; + } + + if (spapr_get_cap(spapr, SPAPR_CAP_FWNMI_MCE) =3D=3D SPAPR_CAP_OFF) { + rtas_st(rets, 0, RTAS_OUT_NOT_SUPPORTED); + return; + } + + spapr->guest_machine_check_addr =3D rtas_ld(args, 1); + rtas_st(rets, 0, RTAS_OUT_SUCCESS); +} + +static void rtas_ibm_nmi_interlock(PowerPCCPU *cpu, + SpaprMachineState *spapr, + uint32_t token, uint32_t nargs, + target_ulong args, + uint32_t nret, target_ulong rets) +{ + if (spapr->guest_machine_check_addr =3D=3D -1) { + /* NMI register not called */ + rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); + } else { + /* + * vCPU issuing "ibm,nmi-interlock" is done with NMI handling, + * hence unset mc_status. + */ + spapr->mc_status =3D -1; + qemu_cond_signal(&spapr->mc_delivery_cond); + rtas_st(rets, 0, RTAS_OUT_SUCCESS); + } +} + static struct rtas_call { const char *name; spapr_rtas_fn fn; @@ -528,6 +570,14 @@ hwaddr spapr_get_rtas_addr(void) return (hwaddr)fdt32_to_cpu(*rtas_data); } =20 +void spapr_fwnmi_register(void) +{ + spapr_rtas_register(RTAS_IBM_NMI_REGISTER, "ibm,nmi-register", + rtas_ibm_nmi_register); + spapr_rtas_register(RTAS_IBM_NMI_INTERLOCK, "ibm,nmi-interlock", + rtas_ibm_nmi_interlock); +} + static void core_rtas_register_types(void) { spapr_rtas_register(RTAS_DISPLAY_CHARACTER, "display-character", diff --git a/include/hw/ppc/spapr.h b/include/hw/ppc/spapr.h index 47f05f2..bc566f9 100644 --- a/include/hw/ppc/spapr.h +++ b/include/hw/ppc/spapr.h @@ -654,8 +654,10 @@ target_ulong spapr_hypercall(PowerPCCPU *cpu, target_u= long opcode, #define RTAS_IBM_REMOVE_PE_DMA_WINDOW (RTAS_TOKEN_BASE + 0x28) #define RTAS_IBM_RESET_PE_DMA_WINDOW (RTAS_TOKEN_BASE + 0x29) #define RTAS_IBM_SUSPEND_ME (RTAS_TOKEN_BASE + 0x2A) +#define RTAS_IBM_NMI_REGISTER (RTAS_TOKEN_BASE + 0x2B) +#define RTAS_IBM_NMI_INTERLOCK (RTAS_TOKEN_BASE + 0x2C) =20 -#define RTAS_TOKEN_MAX (RTAS_TOKEN_BASE + 0x2B) +#define RTAS_TOKEN_MAX (RTAS_TOKEN_BASE + 0x2D) =20 /* RTAS ibm,get-system-parameter token values */ #define RTAS_SYSPARM_SPLPAR_CHARACTERISTICS 20 @@ -907,4 +909,5 @@ void spapr_check_pagesize(SpaprMachineState *spapr, hwa= ddr pagesize, =20 void spapr_set_all_lpcrs(target_ulong value, target_ulong mask); hwaddr spapr_get_rtas_addr(void); +void spapr_fwnmi_register(void); #endif /* HW_SPAPR_H */ From nobody Thu Mar 28 22:22:47 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1565763333; cv=none; d=zoho.com; s=zohoarc; b=F6ZzjU9YnuscJlM9ENjBPw1f79tK3s6Fw6zN+KwMxkHQpDXi6gBQkwcO8XVzC7n8drhuSRlzOGImV6+GAHJA8S6uZWWHI88J8s0Asb5d1JDsLsGUORVM9z3ukjKnvYmN6Vey6/RzKZ4X/Q6pOnLcfsRRMoM7MXFTxGksgDcDivI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1565763333; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; 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Wed, 14 Aug 2019 06:11:45 +0000 Received: from b01ledav001.gho.pok.ibm.com (b01ledav001.gho.pok.ibm.com [9.57.199.106]) by b01cxnp22034.gho.pok.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id x7E6BjQ755247242 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Wed, 14 Aug 2019 06:11:45 GMT Received: from b01ledav001.gho.pok.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 7005D28059; Wed, 14 Aug 2019 06:11:45 +0000 (GMT) Received: from b01ledav001.gho.pok.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 86F532805C; Wed, 14 Aug 2019 06:11:43 +0000 (GMT) Received: from [127.0.1.1] (unknown [9.124.31.79]) by b01ledav001.gho.pok.ibm.com (Postfix) with ESMTP; Wed, 14 Aug 2019 06:11:43 +0000 (GMT) From: Aravinda Prasad To: aik@au1.ibm.com, qemu-ppc@nongnu.org, qemu-devel@nongnu.org, david@gibson.dropbear.id.au Date: Wed, 14 Aug 2019 11:41:42 +0530 Message-ID: <156576310253.29984.8674964786957195162.stgit@aravinda> In-Reply-To: <156576293464.29984.1631520917528142744.stgit@aravinda> References: <156576293464.29984.1631520917528142744.stgit@aravinda> User-Agent: StGit/0.17.1-dirty MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2019-08-14_02:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=0 phishscore=0 bulkscore=0 spamscore=0 clxscore=1015 lowpriorityscore=0 mlxscore=0 impostorscore=0 mlxlogscore=999 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1906280000 definitions=main-1908140060 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [generic] X-Received-From: 148.163.158.5 Subject: [Qemu-devel] [patch-for-4.2 PATCH v11 6/6] migration: Include migration support for machine check handling X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: paulus@ozlabs.org, aravinda@linux.vnet.ibm.com, groug@kaod.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" This patch includes migration support for machine check handling. Especially this patch blocks VM migration requests until the machine check error handling is complete as (i) these errors are specific to the source hardware and is irrelevant on the target hardware, (ii) these errors cause data corruption and should be handled before migration. Signed-off-by: Aravinda Prasad --- hw/ppc/spapr.c | 44 ++++++++++++++++++++++++++++++++++++++++++++ hw/ppc/spapr_events.c | 14 ++++++++++++++ hw/ppc/spapr_rtas.c | 2 ++ include/hw/ppc/spapr.h | 2 ++ 4 files changed, 62 insertions(+) diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c index 04d7ac6..da9570a 100644 --- a/hw/ppc/spapr.c +++ b/hw/ppc/spapr.c @@ -43,6 +43,7 @@ #include "migration/misc.h" #include "migration/global_state.h" #include "migration/register.h" +#include "migration/blocker.h" #include "mmu-hash64.h" #include "mmu-book3s-v3.h" #include "cpu-models.h" @@ -1819,6 +1820,8 @@ static void spapr_machine_reset(MachineState *machine) =20 /* Signal all vCPUs waiting on this condition */ qemu_cond_broadcast(&spapr->mc_delivery_cond); + + migrate_del_blocker(spapr->fwnmi_migration_blocker); } =20 static void spapr_create_nvram(SpaprMachineState *spapr) @@ -2109,6 +2112,42 @@ static const VMStateDescription vmstate_spapr_dtb = =3D { }, }; =20 +static bool spapr_fwnmi_needed(void *opaque) +{ + SpaprMachineState *spapr =3D (SpaprMachineState *)opaque; + + return spapr->guest_machine_check_addr !=3D -1; +} + +static int spapr_fwnmi_post_load(void *opaque, int version_id) +{ + SpaprMachineState *spapr =3D (SpaprMachineState *)opaque; + + if (spapr_get_cap(spapr, SPAPR_CAP_FWNMI_MCE) =3D=3D SPAPR_CAP_ON) { + + if (kvmppc_has_cap_ppc_fwnmi()) { + return 0; + } + + return kvmppc_set_fwnmi(); + } + + return 0; +} + +static const VMStateDescription vmstate_spapr_machine_check =3D { + .name =3D "spapr_machine_check", + .version_id =3D 1, + .minimum_version_id =3D 1, + .needed =3D spapr_fwnmi_needed, + .post_load =3D spapr_fwnmi_post_load, + .fields =3D (VMStateField[]) { + VMSTATE_UINT64(guest_machine_check_addr, SpaprMachineState), + VMSTATE_INT32(mc_status, SpaprMachineState), + VMSTATE_END_OF_LIST() + }, +}; + static const VMStateDescription vmstate_spapr =3D { .name =3D "spapr", .version_id =3D 3, @@ -2142,6 +2181,7 @@ static const VMStateDescription vmstate_spapr =3D { &vmstate_spapr_dtb, &vmstate_spapr_cap_large_decr, &vmstate_spapr_cap_ccf_assist, + &vmstate_spapr_machine_check, NULL } }; @@ -2938,6 +2978,10 @@ static void spapr_machine_init(MachineState *machine) exit(1); } =20 + /* Create the error string for live migration blocker */ + error_setg(&spapr->fwnmi_migration_blocker, + "Live migration not supported during machine check handling"); + /* Register ibm,nmi-register and ibm,nmi-interlock RTAS calls */ spapr_fwnmi_register(); } diff --git a/hw/ppc/spapr_events.c b/hw/ppc/spapr_events.c index b2baca9..62c3520 100644 --- a/hw/ppc/spapr_events.c +++ b/hw/ppc/spapr_events.c @@ -41,6 +41,7 @@ #include "qemu/bcd.h" #include "hw/ppc/spapr_ovec.h" #include +#include "migration/blocker.h" =20 #define RTAS_LOG_VERSION_MASK 0xff000000 #define RTAS_LOG_VERSION_6 0x06000000 @@ -852,6 +853,19 @@ static void spapr_mce_dispatch_elog(PowerPCCPU *cpu, b= ool recovered) void spapr_mce_req_event(PowerPCCPU *cpu, bool recovered) { SpaprMachineState *spapr =3D SPAPR_MACHINE(qdev_get_machine()); + int ret; + Error *local_err =3D NULL; + + ret =3D migrate_add_blocker(spapr->fwnmi_migration_blocker, &local_err= ); + if (ret < 0) { + /* + * We don't want to abort and let the migration to continue. In a + * rare case, the machine check handler will run on the target + * hardware. Though this is not preferable, it is better than abor= ting + * the migration or killing the VM. + */ + warn_report_err(local_err); + } =20 while (spapr->mc_status !=3D -1) { /* diff --git a/hw/ppc/spapr_rtas.c b/hw/ppc/spapr_rtas.c index e4639a4..05ba7e1 100644 --- a/hw/ppc/spapr_rtas.c +++ b/hw/ppc/spapr_rtas.c @@ -49,6 +49,7 @@ #include "hw/ppc/fdt.h" #include "target/ppc/mmu-hash64.h" #include "target/ppc/mmu-book3s-v3.h" +#include "migration/blocker.h" =20 static void rtas_display_character(PowerPCCPU *cpu, SpaprMachineState *spa= pr, uint32_t token, uint32_t nargs, @@ -422,6 +423,7 @@ static void rtas_ibm_nmi_interlock(PowerPCCPU *cpu, */ spapr->mc_status =3D -1; qemu_cond_signal(&spapr->mc_delivery_cond); + migrate_del_blocker(spapr->fwnmi_migration_blocker); rtas_st(rets, 0, RTAS_OUT_SUCCESS); } } diff --git a/include/hw/ppc/spapr.h b/include/hw/ppc/spapr.h index bc566f9..5114f86 100644 --- a/include/hw/ppc/spapr.h +++ b/include/hw/ppc/spapr.h @@ -216,6 +216,8 @@ struct SpaprMachineState { =20 unsigned gpu_numa_id; SpaprTpmProxy *tpm_proxy; + + Error *fwnmi_migration_blocker; }; =20 #define H_SUCCESS 0