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[147.11.224.80]) by smtp.gmail.com with ESMTPSA id t96sm13406767pjb.1.2019.08.12.07.13.54 (version=TLS1 cipher=AES128-SHA bits=128/128); Mon, 12 Aug 2019 07:13:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:subject:date:message-id; bh=jeVYxBKWMzqjksCMr2kqixZfwiMeOmYGjjMCVnetHOg=; b=Q5KiN35V4UCGQaCmu6rIn2KbwEXgpg5gXMfh9pbeMhynduUENSyoWeoL+1OiobzrKJ fjJQ4E1ilciCk2wRQiKfk2BqpSgGzqPF03SRk0oI3Z6YBHA1oa1o+iR+5I/ltN3UTHeu 8U6ejEexIIRietyVqJrA4N9eGdDxwlm3Z76KgeuvNldl/3cirYlpMfHQ3PlYyLNhJzuS 7FB1nva4mmSskIo1XX7efNpVfvG0TXdLrt9xe0kxr0zndHu0VBnIsfSp4q6NJvEAuvgx Ks3VA9eElM/vsugLqCrO3qKl7iKs4xXRq0zEJsohWZvXz3+MDVLIFJtmWHmQJM6t4u2s Am3Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id; bh=jeVYxBKWMzqjksCMr2kqixZfwiMeOmYGjjMCVnetHOg=; b=tjQMxEkd0jrKY+5wRQqlwYDx8AMNIlPcfjtx2oNkOLCudOxLks9ktrPZKyhuMtrVYA YYLUZBS6GDK8YpVKy73byFlgs2buw1WA0ZapOEkkk8XGso0MfjlNGuOxNC/mpP+A//Sg lW+hjD+v61EsqTm8Tjzsa13MoeuTE42VXdVrH/SA4Amps7tKc9USgNciEBto9yOg2eoU KRKBlhFqGvfm7cgHkjz+l2g9LIs69urqTq6HyVeY9mgnA4zkCDfVzyRR1PbtQefMUS0l YszTVXRo6lhv43HusXBGjtviG8agzPhIo5D77MZrBuyLzI8hn0kr5wd8+Ag360Wblhga Skjw== X-Gm-Message-State: APjAAAVGr1zjdenRtfAeG2UL8KSZrbH7BuUTaiBSZPBlTMsdiKRZ7KuK natFu5HyYBB8nPNbozRKGBM= X-Google-Smtp-Source: APXvYqx4ne8KkQBpKHdTXT6yrMBXZA+TjvvgDti2dnUZDg9o6MseqQVAv5PL6MokQE3cp5lDaTszBg== X-Received: by 2002:a63:1020:: with SMTP id f32mr31396124pgl.203.1565619235410; Mon, 12 Aug 2019 07:13:55 -0700 (PDT) From: Bin Meng To: Alistair Francis , Bastian Koppelmann , "Dr. David Alan Gilbert" , Palmer Dabbelt , Sagar Karandikar , qemu-devel@nongnu.org, qemu-riscv@nongnu.org Date: Mon, 12 Aug 2019 07:13:49 -0700 Message-Id: <1565619229-379-1-git-send-email-bmeng.cn@gmail.com> X-Mailer: git-send-email 1.7.1 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::441 Subject: [Qemu-devel] [PATCH v3] riscv: hmp: Add a command to show virtual memory mappings X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This adds 'info mem' command for RISC-V, to show virtual memory mappings of each hart that aids debugging. Rather than showing every valid PTE, the command compacts the output by merging all contiguous physical address mappings into one block and only shows the merged block mapping details. Signed-off-by: Bin Meng Acked-by: Dr. David Alan Gilbert --- Changes in v3: - print PTEs for all harts instead of just current hart Changes in v2: - promote ppn to hwaddr when doing page table address calculation hmp-commands-info.hx | 2 +- target/riscv/Makefile.objs | 4 + target/riscv/monitor.c | 234 +++++++++++++++++++++++++++++++++++++++++= ++++ 3 files changed, 239 insertions(+), 1 deletion(-) create mode 100644 target/riscv/monitor.c diff --git a/hmp-commands-info.hx b/hmp-commands-info.hx index c59444c..257ee7d 100644 --- a/hmp-commands-info.hx +++ b/hmp-commands-info.hx @@ -249,7 +249,7 @@ STEXI Show virtual to physical memory mappings. ETEXI =20 -#if defined(TARGET_I386) +#if defined(TARGET_I386) || defined(TARGET_RISCV) { .name =3D "mem", .args_type =3D "", diff --git a/target/riscv/Makefile.objs b/target/riscv/Makefile.objs index b1c79bc..a8ceccd 100644 --- a/target/riscv/Makefile.objs +++ b/target/riscv/Makefile.objs @@ -1,5 +1,9 @@ obj-y +=3D translate.o op_helper.o cpu_helper.o cpu.o csr.o fpu_helper.o g= dbstub.o pmp.o =20 +ifeq ($(CONFIG_SOFTMMU),y) +obj-y +=3D monitor.o +endif + DECODETREE =3D $(SRC_PATH)/scripts/decodetree.py =20 decode32-y =3D $(SRC_PATH)/target/riscv/insn32.decode diff --git a/target/riscv/monitor.c b/target/riscv/monitor.c new file mode 100644 index 0000000..9b480ad --- /dev/null +++ b/target/riscv/monitor.c @@ -0,0 +1,234 @@ +/* + * QEMU monitor for RISC-V + * + * Copyright (c) 2019 Bin Meng + * + * RISC-V specific monitor commands implementation + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License f= or + * more details. + * + * You should have received a copy of the GNU General Public License along= with + * this program. If not, see . + */ + +#include "qemu/osdep.h" +#include "cpu.h" +#include "cpu_bits.h" +#include "monitor/monitor.h" +#include "monitor/hmp-target.h" + +#ifdef TARGET_RISCV64 +#define PTE_HEADER_FIELDS "vaddr paddr "\ + "size attr\n" +#define PTE_HEADER_DELIMITER "---------------- ---------------- "\ + "---------------- -------\n" +#else +#define PTE_HEADER_FIELDS "vaddr paddr size attr\n" +#define PTE_HEADER_DELIMITER "-------- ---------------- -------- ------= -\n" +#endif + +/* Perform linear address sign extension */ +static target_ulong addr_canonical(int va_bits, target_ulong addr) +{ +#ifdef TARGET_RISCV64 + if (addr & (1UL << (va_bits - 1))) { + addr |=3D (hwaddr)-(1L << va_bits); + } +#endif + + return addr; +} + +static void print_pte_header(Monitor *mon) +{ + monitor_printf(mon, PTE_HEADER_FIELDS); + monitor_printf(mon, PTE_HEADER_DELIMITER); +} + +static void print_pte(Monitor *mon, int va_bits, target_ulong vaddr, + hwaddr paddr, target_ulong size, int attr) +{ + /* santity check on vaddr */ + if (vaddr >=3D (1UL << va_bits)) { + return; + } + + if (!size) { + return; + } + + monitor_printf(mon, TARGET_FMT_lx " " TARGET_FMT_plx " " TARGET_FMT_lx + " %c%c%c%c%c%c%c\n", + addr_canonical(va_bits, vaddr), + paddr, size, + attr & PTE_R ? 'r' : '-', + attr & PTE_W ? 'w' : '-', + attr & PTE_X ? 'x' : '-', + attr & PTE_U ? 'u' : '-', + attr & PTE_G ? 'g' : '-', + attr & PTE_A ? 'a' : '-', + attr & PTE_D ? 'd' : '-'); +} + +static void walk_pte(Monitor *mon, hwaddr base, target_ulong start, + int level, int ptidxbits, int ptesize, int va_bits, + target_ulong *vbase, hwaddr *pbase, hwaddr *last_padd= r, + target_ulong *last_size, int *last_attr) +{ + hwaddr pte_addr; + hwaddr paddr; + target_ulong pgsize; + target_ulong pte; + int ptshift; + int attr; + int idx; + + if (level < 0) { + return; + } + + ptshift =3D level * ptidxbits; + pgsize =3D 1UL << (PGSHIFT + ptshift); + + for (idx =3D 0; idx < (1UL << ptidxbits); idx++) { + pte_addr =3D base + idx * ptesize; + cpu_physical_memory_read(pte_addr, &pte, ptesize); + + paddr =3D (hwaddr)(pte >> PTE_PPN_SHIFT) << PGSHIFT; + attr =3D pte & 0xff; + + /* PTE has to be valid */ + if (attr & PTE_V) { + if (attr & (PTE_R | PTE_W | PTE_X)) { + /* + * A leaf PTE has been found + * + * If current PTE's permission bits differ from the last o= ne, + * or current PTE's ppn does not make a contiguous physical + * address block together with the last one, print out the= last + * contiguous mapped block details. + */ + if ((*last_attr !=3D attr) || + (*last_paddr + *last_size !=3D paddr)) { + print_pte(mon, va_bits, *vbase, *pbase, + *last_paddr + *last_size - *pbase, *last_att= r); + + *vbase =3D start; + *pbase =3D paddr; + *last_attr =3D attr; + } + + *last_paddr =3D paddr; + *last_size =3D pgsize; + } else { + /* pointer to the next level of the page table */ + walk_pte(mon, paddr, start, level - 1, ptidxbits, ptesize, + va_bits, vbase, pbase, last_paddr, + last_size, last_attr); + } + } + + start +=3D pgsize; + } + +} + +static void mem_info_svxx(Monitor *mon, CPUArchState *env) +{ + int levels, ptidxbits, ptesize, vm, va_bits; + hwaddr base; + target_ulong vbase; + hwaddr pbase; + hwaddr last_paddr; + target_ulong last_size; + int last_attr; + + base =3D (hwaddr)get_field(env->satp, SATP_PPN) << PGSHIFT; + + vm =3D get_field(env->satp, SATP_MODE); + switch (vm) { + case VM_1_10_SV32: + levels =3D 2; + ptidxbits =3D 10; + ptesize =3D 4; + break; + case VM_1_10_SV39: + levels =3D 3; + ptidxbits =3D 9; + ptesize =3D 8; + break; + case VM_1_10_SV48: + levels =3D 4; + ptidxbits =3D 9; + ptesize =3D 8; + break; + case VM_1_10_SV57: + levels =3D 5; + ptidxbits =3D 9; + ptesize =3D 8; + break; + default: + g_assert_not_reached(); + break; + } + + /* calculate virtual address bits */ + va_bits =3D PGSHIFT + levels * ptidxbits; + + /* print header */ + print_pte_header(mon); + + vbase =3D -1; + pbase =3D -1; + last_paddr =3D -1; + last_size =3D 0; + last_attr =3D 0; + + /* walk page tables, starting from address 0 */ + walk_pte(mon, base, 0, levels - 1, ptidxbits, ptesize, va_bits, + &vbase, &pbase, &last_paddr, &last_size, &last_attr); + + /* don't forget the last one */ + print_pte(mon, va_bits, vbase, pbase, + last_paddr + last_size - pbase, last_attr); +} + +void hmp_info_mem(Monitor *mon, const QDict *qdict) +{ + CPUArchState *env; + CPUState *cs; + + CPU_FOREACH(cs) { + monitor_printf(mon, "\nhart#%d:\n", cs->cpu_index); + + env =3D (CPUArchState *)(cs->env_ptr); + if (!env) { + monitor_printf(mon, "No CPU available\n"); + continue; + } + + if (!riscv_feature(env, RISCV_FEATURE_MMU)) { + monitor_printf(mon, "S-mode MMU unavailable\n"); + continue; + } + + if (env->priv_ver < PRIV_VERSION_1_10_0) { + monitor_printf(mon, "Privileged mode < 1.10 unsupported\n"); + continue; + } + + if (!(env->satp & SATP_MODE)) { + monitor_printf(mon, "No translation or protection\n"); + continue; + } + + mem_info_svxx(mon, env); + } +} --=20 2.7.4