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X-Received-From: 2607:f8b0:4864:20::541 Subject: [Qemu-devel] [PATCH v3 21/28] riscv: sifive_u: Update UART and ethernet node clock properties X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Now that we have added PRCI nodes, update existing UART and ethernet nodes to use PRCI as their clock sources, to keep in sync with the Linux kernel device tree. With above changes, the previously handcrafted "/soc/ethclk" node is no longer needed. Remove it. Signed-off-by: Bin Meng --- Changes in v3: None Changes in v2: None hw/riscv/sifive_u.c | 21 +++++---------------- include/hw/riscv/sifive_u.h | 3 +-- include/hw/riscv/sifive_u_prci.h | 10 ++++++++++ 3 files changed, 16 insertions(+), 18 deletions(-) diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index 486b247..7eb2b7e 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -82,8 +82,8 @@ static void create_fdt(SiFiveUState *s, const struct Memm= apEntry *memmap, int cpu; uint32_t *cells; char *nodename; - char ethclk_names[] =3D "pclk\0hclk\0tx_clk"; - uint32_t plic_phandle, prci_phandle, ethclk_phandle, phandle =3D 1; + char ethclk_names[] =3D "pclk\0hclk"; + uint32_t plic_phandle, prci_phandle, phandle =3D 1; uint32_t hfclk_phandle, rtcclk_phandle; =20 fdt =3D s->fdt =3D create_device_tree(&s->fdt_size); @@ -242,17 +242,6 @@ static void create_fdt(SiFiveUState *s, const struct M= emmapEntry *memmap, g_free(cells); g_free(nodename); =20 - ethclk_phandle =3D phandle++; - nodename =3D g_strdup_printf("/soc/ethclk"); - qemu_fdt_add_subnode(fdt, nodename); - qemu_fdt_setprop_string(fdt, nodename, "compatible", "fixed-clock"); - qemu_fdt_setprop_cell(fdt, nodename, "#clock-cells", 0x0); - qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency", - SIFIVE_U_GEM_CLOCK_FREQ); - qemu_fdt_setprop_cell(fdt, nodename, "phandle", ethclk_phandle); - ethclk_phandle =3D qemu_fdt_get_phandle(fdt, nodename); - g_free(nodename); - nodename =3D g_strdup_printf("/soc/ethernet@%lx", (long)memmap[SIFIVE_U_GEM].base); qemu_fdt_add_subnode(fdt, nodename); @@ -265,7 +254,7 @@ static void create_fdt(SiFiveUState *s, const struct Me= mmapEntry *memmap, qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle); qemu_fdt_setprop_cell(fdt, nodename, "interrupts", SIFIVE_U_GEM_IRQ); qemu_fdt_setprop_cells(fdt, nodename, "clocks", - ethclk_phandle, ethclk_phandle, ethclk_phandle); + prci_phandle, PRCI_CLK_GEMGXLPLL, prci_phandle, PRCI_CLK_GEMGXLPLL= ); qemu_fdt_setprop(fdt, nodename, "clocks-names", ethclk_names, sizeof(ethclk_names)); qemu_fdt_setprop_cell(fdt, nodename, "#address-cells", 1); @@ -285,8 +274,8 @@ static void create_fdt(SiFiveUState *s, const struct Me= mmapEntry *memmap, qemu_fdt_setprop_cells(fdt, nodename, "reg", 0x0, memmap[SIFIVE_U_UART0].base, 0x0, memmap[SIFIVE_U_UART0].size); - qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency", - SIFIVE_U_CLOCK_FREQ / 2); + qemu_fdt_setprop_cells(fdt, nodename, "clocks", + prci_phandle, PRCI_CLK_TLCLK); qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle); qemu_fdt_setprop_cell(fdt, nodename, "interrupts", SIFIVE_U_UART0_IRQ); =20 diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h index 3ae75b5..2a7877e 100644 --- a/include/hw/riscv/sifive_u.h +++ b/include/hw/riscv/sifive_u.h @@ -68,8 +68,7 @@ enum { enum { SIFIVE_U_CLOCK_FREQ =3D 1000000000, SIFIVE_U_HFCLK_FREQ =3D 33333333, - SIFIVE_U_RTCCLK_FREQ =3D 1000000, - SIFIVE_U_GEM_CLOCK_FREQ =3D 125000000 + SIFIVE_U_RTCCLK_FREQ =3D 1000000 }; =20 #define SIFIVE_U_MANAGEMENT_CPU_COUNT 1 diff --git a/include/hw/riscv/sifive_u_prci.h b/include/hw/riscv/sifive_u_p= rci.h index f3a4656..640c641 100644 --- a/include/hw/riscv/sifive_u_prci.h +++ b/include/hw/riscv/sifive_u_prci.h @@ -87,4 +87,14 @@ typedef struct SiFivePRCIState { =20 DeviceState *sifive_u_prci_create(hwaddr addr); =20 +/* + * Clock indexes for use by Device Tree data and the PRCI driver. + * + * These values are from sifive-fu540-prci.h in the Linux kernel. + */ +#define PRCI_CLK_COREPLL 0 +#define PRCI_CLK_DDRPLL 1 +#define PRCI_CLK_GEMGXLPLL 2 +#define PRCI_CLK_TLCLK 3 + #endif /* HW_SIFIVE_U_PRCI_H */ --=20 2.7.4