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[147.11.224.80]) by smtp.gmail.com with ESMTPSA id v8sm87339107pgs.82.2019.08.11.01.07.20 (version=TLS1 cipher=AES128-SHA bits=128/128); Sun, 11 Aug 2019 01:07:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:subject:date:message-id:in-reply-to:references; bh=6dLjJ31T+Cxxsp5GGfF1L/TvONGnqWJPKtEBUGOOwxo=; b=NiBe+Onz0WidQKT8En8usTGePGyZggd0WMiitJzXhpicEqNJ477G0GdQWdqLRamC1H s4/dtlNu9+4Coseenwsbrv+HhEu/h781rFzf/feoM3LMzCYg49SH3UyYLr5qdyIZmAXD WQIZbFxj5xxogtRDyZ8B+9KK6yu+qUc2iu8zC244bE4GSAW2MI8WpbAAPKfJ6J1dAGim BH4I+VK42c/ScekcsDdY3QQT/MH91VnAXbb7TvtqBzaex2r/dYPOnZoXzaMkZlQT1bLq lRga/C1nozVl8ShK9LEcWwbSANBBuYNjoy6kB5yuRkVOWGBlt3aQexk0L2iFHoeV3fkd 0log== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=6dLjJ31T+Cxxsp5GGfF1L/TvONGnqWJPKtEBUGOOwxo=; b=jve+IZ4NNtGdrUjx1FzJLKvwNjx2luCjEJnTm3+mvkLEnQWWliCscl+U7/yFEjzVFa ZWB3XL9f7dg+WBgg5CvpRPeMoiyRzMrIek3ktl96JSPprWjqAEMrkcsgVfNzC21sW2OP D7m5eu3/+xBVN/ldYAapAF99DtuW/JV4r8v/LgOuA/Neu7etVHegBm/01JOK6OBH9ZL9 pqucZ7Ew+FaLWD3aC4ABUJ38vx+MuNa7NDDboz9yFg4aqiB7wykI7DOU5Tu6mxpXEgTa RfVYhVEDk4dJh9hJo4BFHNA7aL7ZrHm8dB5unmPaG0r+l79mmhYwxw0YdtYvL2jBCphZ PhbA== X-Gm-Message-State: APjAAAXVU867bqRoeVMEREUD4OJUW50ikOXJKJ9SID6584M3j8IEzp+4 9SxnjP+OU5xRpBfzOnpGfhE= X-Google-Smtp-Source: APXvYqzTuSRF43Zp5DicrIANSdbzWn9Ig2AVRXEAx5GWYL2rMHlToC+eerzGWIapfYfwQMwwgo0GcQ== X-Received: by 2002:a63:2157:: with SMTP id s23mr22157702pgm.167.1565510841028; Sun, 11 Aug 2019 01:07:21 -0700 (PDT) From: Bin Meng To: Alistair Francis , Palmer Dabbelt , qemu-devel@nongnu.org, qemu-riscv@nongnu.org Date: Sun, 11 Aug 2019 01:06:46 -0700 Message-Id: <1565510821-3927-14-git-send-email-bmeng.cn@gmail.com> X-Mailer: git-send-email 1.7.1 In-Reply-To: <1565510821-3927-1-git-send-email-bmeng.cn@gmail.com> References: <1565510821-3927-1-git-send-email-bmeng.cn@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::542 Subject: [Qemu-devel] [PATCH v3 13/28] riscv: sifive_e: prci: Update the PRCI register block size X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Currently the PRCI register block size is set to 0x8000, but in fact 0x1000 is enough, which is also what the manual says. Signed-off-by: Bin Meng Reviewed-by: Chih-Min Chao Reviewed-by: Alistair Francis --- Changes in v3: None Changes in v2: None hw/riscv/sifive_e_prci.c | 2 +- include/hw/riscv/sifive_e_prci.h | 2 ++ 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/hw/riscv/sifive_e_prci.c b/hw/riscv/sifive_e_prci.c index c906f11..4cbce48 100644 --- a/hw/riscv/sifive_e_prci.c +++ b/hw/riscv/sifive_e_prci.c @@ -85,7 +85,7 @@ static void sifive_prci_init(Object *obj) SiFivePRCIState *s =3D SIFIVE_E_PRCI(obj); =20 memory_region_init_io(&s->mmio, obj, &sifive_prci_ops, s, - TYPE_SIFIVE_E_PRCI, 0x8000); + TYPE_SIFIVE_E_PRCI, SIFIVE_E_PRCI_REG_SIZE); sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio); =20 s->hfrosccfg =3D (SIFIVE_PRCI_HFROSCCFG_RDY | SIFIVE_PRCI_HFROSCCFG_EN= ); diff --git a/include/hw/riscv/sifive_e_prci.h b/include/hw/riscv/sifive_e_p= rci.h index 7932fe7..81e506b 100644 --- a/include/hw/riscv/sifive_e_prci.h +++ b/include/hw/riscv/sifive_e_prci.h @@ -47,6 +47,8 @@ enum { SIFIVE_PRCI_PLLOUTDIV_DIV1 =3D (1 << 8) }; =20 +#define SIFIVE_E_PRCI_REG_SIZE 0x1000 + #define TYPE_SIFIVE_E_PRCI "riscv.sifive.e.prci" =20 #define SIFIVE_E_PRCI(obj) \ --=20 2.7.4