From nobody Tue Nov 11 20:53:47 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1565355072; cv=none; d=zoho.com; s=zohoarc; b=cwbG81mBZQrHfE33Kx3HddLN5VXUGluZxnuDuUCrqMe4yJEIcpMw+jcaHYQ2v6fE0s1qCr6sp5NaO//Y9P0LuVnurNgm9NT6QPceyY2Z7+weGM55hPqeeR2lxbFnfI+InGxLlEJ6kHxmg1z0RdqqWSUdLuT1Blq8/DoH5gB763E= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1565355072; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=EEU/nl2TUKXljL5x88Jg74c9P7xcTNWDnaREql5no5I=; b=ERNhZj0GCREB91l0NpG4i19cSo5ifcaDwSEOD8KZhfPSVJRbVUiEV1mls09UW51pdmJjlft9klPCjJGv/ydD6cL+8eXrA0OsrhwcFNcqkNFJK++jlHAP1+728nT4LbYl9DhvqxdFy/cbVS2WrgceFW8hVKv2SirD3O3P92sOSco= ARC-Authentication-Results: i=1; mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1565355072608835.1331565705392; Fri, 9 Aug 2019 05:51:12 -0700 (PDT) Received: from localhost ([::1]:59048 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hw4MR-0006rp-LR for importer@patchew.org; Fri, 09 Aug 2019 08:51:11 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:52835) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hw4Jp-0001kC-48 for qemu-devel@nongnu.org; Fri, 09 Aug 2019 08:48:30 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hw4Jn-00018v-Kr for qemu-devel@nongnu.org; Fri, 09 Aug 2019 08:48:29 -0400 Received: from mx2.rt-rk.com ([89.216.37.149]:52478 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1hw4Jn-00017y-Ay for qemu-devel@nongnu.org; Fri, 09 Aug 2019 08:48:27 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id DDB781A20D8; Fri, 9 Aug 2019 14:48:24 +0200 (CEST) Received: from rtrkw774-lin.domain.local (rtrkw774-lin.domain.local [10.10.13.43]) by mail.rt-rk.com (Postfix) with ESMTPSA id 90B101A206F; Fri, 9 Aug 2019 14:48:24 +0200 (CEST) X-Virus-Scanned: amavisd-new at rt-rk.com From: Aleksandar Markovic To: qemu-devel@nongnu.org Date: Fri, 9 Aug 2019 14:46:39 +0200 Message-Id: <1565354819-1495-7-git-send-email-aleksandar.markovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1565354819-1495-1-git-send-email-aleksandar.markovic@rt-rk.com> References: <1565354819-1495-1-git-send-email-aleksandar.markovic@rt-rk.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 89.216.37.149 Subject: [Qemu-devel] [PATCH for 4.2 v7 06/26] target/mips: Style improvements in cp0_timer.c X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: arikalo@wavecomp.com, philmd@redhat.com, amarkovic@wavecomp.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" From: Aleksandar Markovic Fixes mostly errors and warnings reported by 'checkpatch.pl -f'. Signed-off-by: Aleksandar Markovic Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/mips/cp0_timer.c | 42 +++++++++++++++++++++++------------------- 1 file changed, 23 insertions(+), 19 deletions(-) diff --git a/target/mips/cp0_timer.c b/target/mips/cp0_timer.c index f471639..b5f3560 100644 --- a/target/mips/cp0_timer.c +++ b/target/mips/cp0_timer.c @@ -29,7 +29,7 @@ #define TIMER_PERIOD 10 /* 10 ns period for 100 Mhz frequency */ =20 /* XXX: do not use a global */ -uint32_t cpu_mips_get_random (CPUMIPSState *env) +uint32_t cpu_mips_get_random(CPUMIPSState *env) { static uint32_t seed =3D 1; static uint32_t prev_idx =3D 0; @@ -42,8 +42,10 @@ uint32_t cpu_mips_get_random (CPUMIPSState *env) =20 /* Don't return same value twice, so get another value */ do { - /* Use a simple algorithm of Linear Congruential Generator - * from ISO/IEC 9899 standard. */ + /* + * Use a simple algorithm of Linear Congruential Generator + * from ISO/IEC 9899 standard. + */ seed =3D 1103515245 * seed + 12345; idx =3D (seed >> 16) % nb_rand_tlb + env->CP0_Wired; } while (idx =3D=3D prev_idx); @@ -73,7 +75,7 @@ static void cpu_mips_timer_expire(CPUMIPSState *env) qemu_irq_raise(env->irq[(env->CP0_IntCtl >> CP0IntCtl_IPTI) & 0x7]); } =20 -uint32_t cpu_mips_get_count (CPUMIPSState *env) +uint32_t cpu_mips_get_count(CPUMIPSState *env) { if (env->CP0_Cause & (1 << CP0Ca_DC)) { return env->CP0_Count; @@ -91,16 +93,16 @@ uint32_t cpu_mips_get_count (CPUMIPSState *env) } } =20 -void cpu_mips_store_count (CPUMIPSState *env, uint32_t count) +void cpu_mips_store_count(CPUMIPSState *env, uint32_t count) { /* * This gets called from cpu_state_reset(), potentially before timer i= nit. * So env->timer may be NULL, which is also the case with KVM enabled = so * treat timer as disabled in that case. */ - if (env->CP0_Cause & (1 << CP0Ca_DC) || !env->timer) + if (env->CP0_Cause & (1 << CP0Ca_DC) || !env->timer) { env->CP0_Count =3D count; - else { + } else { /* Store new count register */ env->CP0_Count =3D count - (uint32_t)(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) / TIMER_PE= RIOD); @@ -109,13 +111,15 @@ void cpu_mips_store_count (CPUMIPSState *env, uint32_= t count) } } =20 -void cpu_mips_store_compare (CPUMIPSState *env, uint32_t value) +void cpu_mips_store_compare(CPUMIPSState *env, uint32_t value) { env->CP0_Compare =3D value; - if (!(env->CP0_Cause & (1 << CP0Ca_DC))) + if (!(env->CP0_Cause & (1 << CP0Ca_DC))) { cpu_mips_timer_update(env); - if (env->insn_flags & ISA_MIPS32R2) + } + if (env->insn_flags & ISA_MIPS32R2) { env->CP0_Cause &=3D ~(1 << CP0Ca_TI); + } qemu_irq_lower(env->irq[(env->CP0_IntCtl >> CP0IntCtl_IPTI) & 0x7]); } =20 @@ -131,27 +135,27 @@ void cpu_mips_stop_count(CPUMIPSState *env) TIMER_PERIOD); } =20 -static void mips_timer_cb (void *opaque) +static void mips_timer_cb(void *opaque) { CPUMIPSState *env; =20 env =3D opaque; -#if 0 - qemu_log("%s\n", __func__); -#endif =20 - if (env->CP0_Cause & (1 << CP0Ca_DC)) + if (env->CP0_Cause & (1 << CP0Ca_DC)) { return; + } =20 - /* ??? This callback should occur when the counter is exactly equal to - the comparator value. Offset the count by one to avoid immediately - retriggering the callback before any virtual time has passed. */ + /* + * ??? This callback should occur when the counter is exactly equal to + * the comparator value. Offset the count by one to avoid immediately + * retriggering the callback before any virtual time has passed. + */ env->CP0_Count++; cpu_mips_timer_expire(env); env->CP0_Count--; } =20 -void cpu_mips_clock_init (MIPSCPU *cpu) +void cpu_mips_clock_init(MIPSCPU *cpu) { CPUMIPSState *env =3D &cpu->env; =20 --=20 2.7.4