From nobody Tue Nov 11 20:53:45 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1565355075; cv=none; d=zoho.com; s=zohoarc; b=YepQ4BUNEVp/7DW8w3sONofLyJ9W5Fjcs3aI/+C5jgu/apWJ3DX7cz4UWyarEVOkrmxT4baeYyrNkcxPfy8baA6g+TMhuftT/6f9qjOohx91Us1TeyaGmJB1ujHSKCY1fR+7ikYDNqizNjkQJnHDuu6i/CNldY+jTLKXtuxROK4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1565355075; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=ppGv0A7lyxdlj0mUUOiThsiMn5Om1Dz0RY/lvEA0UAU=; b=WzVjaCmQC8Zff+QloPaqefPiV4ShwGYFRNOvyBL/Vh1KuMyzjMCVT+2QFVq0yioWoKEE1tCAdHFeCPIgrQXettn/6aMrM1x2GC4oSvcRV+ACWMSVuNm6i/HNYhrAvWaDEb21qdACm2V+YNcmMKU7VlZuhtkcUlMljP+ZIqZECDg= ARC-Authentication-Results: i=1; mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1565355075834587.7287035809951; Fri, 9 Aug 2019 05:51:15 -0700 (PDT) Received: from localhost ([::1]:59050 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hw4MU-000738-T9 for importer@patchew.org; Fri, 09 Aug 2019 08:51:14 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:52820) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hw4Jo-0001k9-H2 for qemu-devel@nongnu.org; Fri, 09 Aug 2019 08:48:30 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hw4Jn-00018U-5p for qemu-devel@nongnu.org; Fri, 09 Aug 2019 08:48:28 -0400 Received: from mx2.rt-rk.com ([89.216.37.149]:52466 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1hw4Jm-00017w-RF for qemu-devel@nongnu.org; Fri, 09 Aug 2019 08:48:27 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id A24E31A2113; Fri, 9 Aug 2019 14:48:24 +0200 (CEST) Received: from rtrkw774-lin.domain.local (rtrkw774-lin.domain.local [10.10.13.43]) by mail.rt-rk.com (Postfix) with ESMTPSA id 8679F1A2087; Fri, 9 Aug 2019 14:48:24 +0200 (CEST) X-Virus-Scanned: amavisd-new at rt-rk.com From: Aleksandar Markovic To: qemu-devel@nongnu.org Date: Fri, 9 Aug 2019 14:46:38 +0200 Message-Id: <1565354819-1495-6-git-send-email-aleksandar.markovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1565354819-1495-1-git-send-email-aleksandar.markovic@rt-rk.com> References: <1565354819-1495-1-git-send-email-aleksandar.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 89.216.37.149 Subject: [Qemu-devel] [PATCH for 4.2 v7 05/26] target/mips: Add support for emulation of CRC32 group of instructions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: arikalo@wavecomp.com, Yongbok Kim , philmd@redhat.com, amarkovic@wavecomp.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Yongbok Kim Add emulation of MIPS' CRC32 (Cyclic Redundancy Check) instructions. Reuse zlib crc32() and Linux crc32c(). Note that, at the time being, there is no MIPS CPU that supports CRC32 instructions (they are an optional part of MIPS64/32 R6 anf nanoMIPS ISAs). Signed-off-by: Yongbok Kim Signed-off-by: Aleksandar Markovic --- disas/mips.c | 8 ++++++++ target/mips/helper.h | 2 ++ target/mips/op_helper.c | 22 ++++++++++++++++++++++ target/mips/translate.c | 41 +++++++++++++++++++++++++++++++++++++++++ 4 files changed, 73 insertions(+) diff --git a/disas/mips.c b/disas/mips.c index c3a3059..b9a5204 100644 --- a/disas/mips.c +++ b/disas/mips.c @@ -1411,6 +1411,14 @@ const struct mips_opcode mips_builtin_opcodes[] =3D {"evp", "t", 0x41600004, 0xffe0ffff, TRAP|WR_t, 0, I= 32R6}, {"ginvi", "v", 0x7c00003d, 0xfc1ffcff, TRAP | INSN_TLB, 0, I= 32R6}, {"ginvt", "v", 0x7c0000bd, 0xfc1ffcff, TRAP | INSN_TLB, 0, I= 32R6}, +{"crc32b", "t,v,t", 0x7c00000f, 0xfc00ff3f, WR_d | RD_s | RD_t, 0, I= 32R6}, +{"crc32h", "t,v,t", 0x7c00004f, 0xfc00ff3f, WR_d | RD_s | RD_t, 0, I= 32R6}, +{"crc32w", "t,v,t", 0x7c00008f, 0xfc00ff3f, WR_d | RD_s | RD_t, 0, I= 32R6}, +{"crc32d", "t,v,t", 0x7c0000cf, 0xfc00ff3f, WR_d | RD_s | RD_t, 0, I= 64R6}, +{"crc32cb", "t,v,t", 0x7c00010f, 0xfc00ff3f, WR_d | RD_s | RD_t, 0, I= 32R6}, +{"crc32ch", "t,v,t", 0x7c00014f, 0xfc00ff3f, WR_d | RD_s | RD_t, 0, I= 32R6}, +{"crc32cw", "t,v,t", 0x7c00018f, 0xfc00ff3f, WR_d | RD_s | RD_t, 0, I= 32R6}, +{"crc32cd", "t,v,t", 0x7c0001cf, 0xfc00ff3f, WR_d | RD_s | RD_t, 0, I= 64R6}, =20 /* MSA */ {"sll.b", "+d,+e,+f", 0x7800000d, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA= }, diff --git a/target/mips/helper.h b/target/mips/helper.h index c7d35bd..0e61043 100644 --- a/target/mips/helper.h +++ b/target/mips/helper.h @@ -40,6 +40,8 @@ DEF_HELPER_FLAGS_1(bitswap, TCG_CALL_NO_RWG_SE, tl, tl) DEF_HELPER_FLAGS_1(dbitswap, TCG_CALL_NO_RWG_SE, tl, tl) #endif =20 +DEF_HELPER_3(crc32, tl, tl, tl, i32) +DEF_HELPER_3(crc32c, tl, tl, tl, i32) DEF_HELPER_FLAGS_4(rotx, TCG_CALL_NO_RWG_SE, tl, tl, i32, i32, i32) =20 #ifndef CONFIG_USER_ONLY diff --git a/target/mips/op_helper.c b/target/mips/op_helper.c index 3104904..5874029 100644 --- a/target/mips/op_helper.c +++ b/target/mips/op_helper.c @@ -25,6 +25,8 @@ #include "exec/exec-all.h" #include "exec/cpu_ldst.h" #include "sysemu/kvm.h" +#include "qemu/crc32c.h" +#include =20 /*************************************************************************= ****/ /* Exceptions processing helpers */ @@ -343,6 +345,26 @@ target_ulong helper_rotx(target_ulong rs, uint32_t shi= ft, uint32_t shiftx, return (int64_t)(int32_t)(uint32_t)tmp5; } =20 +/* these crc32 functions are based on target/arm/helper-a64.c */ +target_ulong helper_crc32(target_ulong val, target_ulong m, uint32_t sz) +{ + uint8_t buf[8]; + target_ulong mask =3D ((sz * 8) =3D=3D 64) ? -1ULL : ((1ULL << (sz * 8= )) - 1); + + m &=3D mask; + stq_le_p(buf, m); + return (int32_t) (crc32(val ^ 0xffffffff, buf, sz) ^ 0xffffffff); +} + +target_ulong helper_crc32c(target_ulong val, target_ulong m, uint32_t sz) +{ + uint8_t buf[8]; + target_ulong mask =3D ((sz * 8) =3D=3D 64) ? -1ULL : ((1ULL << (sz * 8= )) - 1); + m &=3D mask; + stq_le_p(buf, m); + return (int32_t) (crc32c(val, buf, sz) ^ 0xffffffff); +} + #ifndef CONFIG_USER_ONLY =20 static inline hwaddr do_translate_address(CPUMIPSState *env, diff --git a/target/mips/translate.c b/target/mips/translate.c index 3f73be0..3f9f113 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -452,6 +452,7 @@ enum { OPC_LWE =3D 0x2F | OPC_SPECIAL3, =20 /* R6 */ + OPC_CRC32 =3D 0x0F | OPC_SPECIAL3, R6_OPC_PREF =3D 0x35 | OPC_SPECIAL3, R6_OPC_CACHE =3D 0x25 | OPC_SPECIAL3, R6_OPC_LL =3D 0x36 | OPC_SPECIAL3, @@ -2550,6 +2551,7 @@ typedef struct DisasContext { bool saar; bool mi; int gi; + bool crcp; } DisasContext; =20 #define DISAS_STOP DISAS_TARGET_0 @@ -27041,6 +27043,33 @@ static void decode_opc_special2_legacy(CPUMIPSStat= e *env, DisasContext *ctx) } } =20 +static void gen_crc32(DisasContext *ctx, int rd, int rs, int rt, int sz, + int crc32c) +{ + TCGv t0; + TCGv t1; + TCGv_i32 tsz =3D tcg_const_i32(1 << sz); + if (rd =3D=3D 0) { + /* Treat as NOP. */ + return; + } + t0 =3D tcg_temp_new(); + t1 =3D tcg_temp_new(); + + gen_load_gpr(t0, rt); + gen_load_gpr(t1, rs); + + if (crc32c) { + gen_helper_crc32c(cpu_gpr[rd], t0, t1, tsz); + } else { + gen_helper_crc32(cpu_gpr[rd], t0, t1, tsz); + } + + tcg_temp_free(t0); + tcg_temp_free(t1); + tcg_temp_free_i32(tsz); +} + static void decode_opc_special3_r6(CPUMIPSState *env, DisasContext *ctx) { int rs, rt, rd, sa; @@ -27055,6 +27084,17 @@ static void decode_opc_special3_r6(CPUMIPSState *e= nv, DisasContext *ctx) =20 op1 =3D MASK_SPECIAL3(ctx->opcode); switch (op1) { + case OPC_CRC32: + if (unlikely(!ctx->crcp) || + unlikely((extract32(ctx->opcode, 6, 2) =3D=3D 3) && + (!(ctx->hflags & MIPS_HFLAG_64))) || + unlikely((extract32(ctx->opcode, 8, 3) >=3D 2))) { + generate_exception_end(ctx, EXCP_RI); + } + gen_crc32(ctx, rt, rs, rt, + extract32(ctx->opcode, 6, 2), + extract32(ctx->opcode, 8, 3)); + break; case R6_OPC_PREF: if (rt >=3D 24) { /* hint codes 24-31 are reserved and signal RI */ @@ -30049,6 +30089,7 @@ static void mips_tr_init_disas_context(DisasContext= Base *dcbase, CPUState *cs) ctx->abs2008 =3D (env->active_fpu.fcr31 >> FCR31_ABS2008) & 1; ctx->mi =3D (env->CP0_Config5 >> CP0C5_MI) & 1; ctx->gi =3D (env->CP0_Config5 >> CP0C5_GI) & 3; + ctx->crcp =3D (env->CP0_Config5 >> CP0C5_CRCP) & 1; restore_cpu_state(env, ctx); #ifdef CONFIG_USER_ONLY ctx->mem_idx =3D MIPS_HFLAG_UM; --=20 2.7.4