From nobody Mon Feb 9 09:46:56 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1565355578; cv=none; d=zoho.com; s=zohoarc; b=G3pC4CfQaXes5CqS7zTKuFvruTJ8Cv1YpSp0IsD6BbBahSB2dhM+FBvO+tppko6jaayxbP3zD813yJs7mVR8owaoWP7E8GKBkfXZcRMWR79U9OjxkKyjoQtyXQrUZYXiXsS2iJMzZYSdDlg9TWHYoaH90ojTBRLb0HTmmPN/p/Q= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1565355578; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=I756YFZo5yvsf0KbTlourjfwAIJmLfHASVYyIClV/+0=; b=HvcmAFbd0vDant3AP0bKfyeUcGi17Tw6S7R8VaLqkiFSbstDb4o4roHFeNhG6aZRUZdfeH2u36WS8iIxxhPiCAW6fZVlTmI8V/PYUDJihokM1KGHY1y9jLCTW5GicSq91P0BITc1HagS4MHXaYgf0QGVKg1liZgZMHfUEvNdE4I= ARC-Authentication-Results: i=1; mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1565355578032522.7488830619442; Fri, 9 Aug 2019 05:59:38 -0700 (PDT) Received: from localhost ([::1]:59180 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hw4Ub-0007gf-3s for importer@patchew.org; Fri, 09 Aug 2019 08:59:37 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:53016) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hw4K3-0002Ge-9M for qemu-devel@nongnu.org; Fri, 09 Aug 2019 08:48:49 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hw4K0-0001GX-CP for qemu-devel@nongnu.org; Fri, 09 Aug 2019 08:48:42 -0400 Received: from mx2.rt-rk.com ([89.216.37.149]:52669 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1hw4K0-0001AH-0S for qemu-devel@nongnu.org; Fri, 09 Aug 2019 08:48:40 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id 0BBB81A21BB; Fri, 9 Aug 2019 14:48:26 +0200 (CEST) Received: from rtrkw774-lin.domain.local (rtrkw774-lin.domain.local [10.10.13.43]) by mail.rt-rk.com (Postfix) with ESMTPSA id D59C31A21BF; Fri, 9 Aug 2019 14:48:25 +0200 (CEST) X-Virus-Scanned: amavisd-new at rt-rk.com From: Aleksandar Markovic To: qemu-devel@nongnu.org Date: Fri, 9 Aug 2019 14:46:57 +0200 Message-Id: <1565354819-1495-25-git-send-email-aleksandar.markovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1565354819-1495-1-git-send-email-aleksandar.markovic@rt-rk.com> References: <1565354819-1495-1-git-send-email-aleksandar.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 89.216.37.149 Subject: [Qemu-devel] [PATCH for 4.2 v7 24/26] target/mips: Clean up handling of CP0 register 31 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: arikalo@wavecomp.com, philmd@redhat.com, amarkovic@wavecomp.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Aleksandar Markovic Clean up handling of CP0 register 31. Signed-off-by: Aleksandar Markovic --- target/mips/cpu.h | 2 +- target/mips/translate.c | 56 ++++++++++++++++++++++++---------------------= ---- 2 files changed, 29 insertions(+), 29 deletions(-) diff --git a/target/mips/cpu.h b/target/mips/cpu.h index 9036611..49bedac 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -573,7 +573,6 @@ struct CPUMIPSState { * CP0 Register 4 */ target_ulong CP0_Context; - target_ulong CP0_KScratch[MIPS_KSCRATCH_NUM]; int32_t CP0_MemoryMapID; /* * CP0 Register 5 @@ -984,6 +983,7 @@ struct CPUMIPSState { * CP0 Register 31 */ int32_t CP0_DESAVE; + target_ulong CP0_KScratch[MIPS_KSCRATCH_NUM]; =20 /* We waste some space so we can handle shadow registers like TCs. */ TCState tcs[MIPS_SHADOW_SET_MAX]; diff --git a/target/mips/translate.c b/target/mips/translate.c index b6378ae..9468229 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -7573,17 +7573,17 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, i= nt reg, int sel) break; case CP0_REGISTER_31: switch (sel) { - case 0: + case CP0_REG31__DESAVE: /* EJTAG support */ gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_DESAVE)); register_name =3D "DESAVE"; break; - case 2: - case 3: - case 4: - case 5: - case 6: - case 7: + case CP0_REG31__KSCRATCH1: + case CP0_REG31__KSCRATCH2: + case CP0_REG31__KSCRATCH3: + case CP0_REG31__KSCRATCH4: + case CP0_REG31__KSCRATCH5: + case CP0_REG31__KSCRATCH6: CP0_CHECK(ctx->kscrexist & (1 << sel)); tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_KScratch[sel-2])); @@ -8319,17 +8319,17 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, i= nt reg, int sel) break; case CP0_REGISTER_31: switch (sel) { - case 0: + case CP0_REG31__DESAVE: /* EJTAG support */ gen_mtc0_store32(arg, offsetof(CPUMIPSState, CP0_DESAVE)); register_name =3D "DESAVE"; break; - case 2: - case 3: - case 4: - case 5: - case 6: - case 7: + case CP0_REG31__KSCRATCH1: + case CP0_REG31__KSCRATCH2: + case CP0_REG31__KSCRATCH3: + case CP0_REG31__KSCRATCH4: + case CP0_REG31__KSCRATCH5: + case CP0_REG31__KSCRATCH6: CP0_CHECK(ctx->kscrexist & (1 << sel)); tcg_gen_st_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_KScratch[sel-2])); @@ -9048,17 +9048,17 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, = int reg, int sel) break; case CP0_REGISTER_31: switch (sel) { - case 0: + case CP0_REG31__DESAVE: /* EJTAG support */ gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_DESAVE)); register_name =3D "DESAVE"; break; - case 2: - case 3: - case 4: - case 5: - case 6: - case 7: + case CP0_REG31__KSCRATCH1: + case CP0_REG31__KSCRATCH2: + case CP0_REG31__KSCRATCH3: + case CP0_REG31__KSCRATCH4: + case CP0_REG31__KSCRATCH5: + case CP0_REG31__KSCRATCH6: CP0_CHECK(ctx->kscrexist & (1 << sel)); tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_KScratch[sel-2])); @@ -9781,17 +9781,17 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, = int reg, int sel) break; case CP0_REGISTER_31: switch (sel) { - case 0: + case CP0_REG31__DESAVE: /* EJTAG support */ gen_mtc0_store32(arg, offsetof(CPUMIPSState, CP0_DESAVE)); register_name =3D "DESAVE"; break; - case 2: - case 3: - case 4: - case 5: - case 6: - case 7: + case CP0_REG31__KSCRATCH1: + case CP0_REG31__KSCRATCH2: + case CP0_REG31__KSCRATCH3: + case CP0_REG31__KSCRATCH4: + case CP0_REG31__KSCRATCH5: + case CP0_REG31__KSCRATCH6: CP0_CHECK(ctx->kscrexist & (1 << sel)); tcg_gen_st_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_KScratch[sel-2])); --=20 2.7.4