From nobody Mon Feb 9 12:45:28 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1565355212; cv=none; d=zoho.com; s=zohoarc; b=ALWtQNGWSsPQorBWStgIeZAllr3x1M5xkrPsWcxIxRHvEoyzAMAzo0K9/uoUwwoK2dUvlMmcVTwulkNiAIehrDLzRerCVwXhnKHS2Qp6k26rw1sVdzoYHEkOtfBq64U8d+Mz8TARBtuNbCMzhkOhjvmERosu35fggBWLVPDsTWE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1565355212; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=sIDeUXUtyoNjYeRGQrFRdKl7ArFdHIjNrJAb38rbkSA=; b=jTYVE/yNqXfvLIjLwWbLTNwoJHyX0NIWozt0YeApyi8XLmDp9p7sXlTEj5s5XbGo4047Z18G3lZtRwbHRTeKQvrCrCpsBwYer2LsSKOTfgESYbt6nCzmr61cdZCIancAn1Hrenv4N9eiZswHE70kVzZRt6lyzn4FpTdJB0qzSr4= ARC-Authentication-Results: i=1; mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1565355212630731.024386418971; Fri, 9 Aug 2019 05:53:32 -0700 (PDT) Received: from localhost ([::1]:59076 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hw4Oh-0002dJ-Kq for importer@patchew.org; Fri, 09 Aug 2019 08:53:31 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:53018) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hw4K3-0002Gg-9n for qemu-devel@nongnu.org; Fri, 09 Aug 2019 08:48:49 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hw4K0-0001Gd-G8 for qemu-devel@nongnu.org; Fri, 09 Aug 2019 08:48:43 -0400 Received: from mx2.rt-rk.com ([89.216.37.149]:52666 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1hw4K0-0001AB-4l for qemu-devel@nongnu.org; Fri, 09 Aug 2019 08:48:40 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id D32401A21D6; Fri, 9 Aug 2019 14:48:25 +0200 (CEST) Received: from rtrkw774-lin.domain.local (rtrkw774-lin.domain.local [10.10.13.43]) by mail.rt-rk.com (Postfix) with ESMTPSA id A7FAB1A217E; Fri, 9 Aug 2019 14:48:25 +0200 (CEST) X-Virus-Scanned: amavisd-new at rt-rk.com From: Aleksandar Markovic To: qemu-devel@nongnu.org Date: Fri, 9 Aug 2019 14:46:52 +0200 Message-Id: <1565354819-1495-20-git-send-email-aleksandar.markovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1565354819-1495-1-git-send-email-aleksandar.markovic@rt-rk.com> References: <1565354819-1495-1-git-send-email-aleksandar.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 89.216.37.149 Subject: [Qemu-devel] [PATCH for 4.2 v7 19/26] target/mips: Clean up handling of CP0 register 5 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: arikalo@wavecomp.com, philmd@redhat.com, amarkovic@wavecomp.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Aleksandar Markovic Clean up handling of CP0 register 5. Signed-off-by: Aleksandar Markovic --- target/mips/cpu.h | 6 +++++ target/mips/translate.c | 64 ++++++++++++++++++++++++---------------------= ---- 2 files changed, 38 insertions(+), 32 deletions(-) diff --git a/target/mips/cpu.h b/target/mips/cpu.h index eebdc9f..2ab388b 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -312,6 +312,12 @@ typedef struct mips_def_t mips_def_t; /* CP0 Register 05 */ #define CP0_REG05__PAGEMASK 0 #define CP0_REG05__PAGEGRAIN 1 +#define CP0_REG05__SEGCTL0 2 +#define CP0_REG05__SEGCTL1 3 +#define CP0_REG05__SEGCTL2 4 +#define CP0_REG05__PWBASE 5 +#define CP0_REG05__PWFIELD 6 +#define CP0_REG05__PWSIZE 7 /* CP0 Register 06 */ #define CP0_REG06__WIRED 0 /* CP0 Register 07 */ diff --git a/target/mips/translate.c b/target/mips/translate.c index 3fb3757..ea2d4b1 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -7042,44 +7042,44 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, i= nt reg, int sel) break; case CP0_REGISTER_05: switch (sel) { - case 0: + case CP0_REG05__PAGEMASK: gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PageMask)); register_name =3D "PageMask"; break; - case 1: + case CP0_REG05__PAGEGRAIN: check_insn(ctx, ISA_MIPS32R2); gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PageGrain)); register_name =3D "PageGrain"; break; - case 2: + case CP0_REG05__SEGCTL0: CP0_CHECK(ctx->sc); tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_SegCtl0= )); tcg_gen_ext32s_tl(arg, arg); register_name =3D "SegCtl0"; break; - case 3: + case CP0_REG05__SEGCTL1: CP0_CHECK(ctx->sc); tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_SegCtl1= )); tcg_gen_ext32s_tl(arg, arg); register_name =3D "SegCtl1"; break; - case 4: + case CP0_REG05__SEGCTL2: CP0_CHECK(ctx->sc); tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_SegCtl2= )); tcg_gen_ext32s_tl(arg, arg); register_name =3D "SegCtl2"; break; - case 5: + case CP0_REG05__PWBASE: check_pw(ctx); gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PWBase)); register_name =3D "PWBase"; break; - case 6: + case CP0_REG05__PWFIELD: check_pw(ctx); gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PWField)); register_name =3D "PWField"; break; - case 7: + case CP0_REG05__PWSIZE: check_pw(ctx); gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PWSize)); register_name =3D "PWSize"; @@ -7783,42 +7783,42 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, i= nt reg, int sel) break; case CP0_REGISTER_05: switch (sel) { - case 0: + case CP0_REG05__PAGEMASK: gen_helper_mtc0_pagemask(cpu_env, arg); register_name =3D "PageMask"; break; - case 1: + case CP0_REG05__PAGEGRAIN: check_insn(ctx, ISA_MIPS32R2); gen_helper_mtc0_pagegrain(cpu_env, arg); register_name =3D "PageGrain"; ctx->base.is_jmp =3D DISAS_STOP; break; - case 2: + case CP0_REG05__SEGCTL0: CP0_CHECK(ctx->sc); gen_helper_mtc0_segctl0(cpu_env, arg); register_name =3D "SegCtl0"; break; - case 3: + case CP0_REG05__SEGCTL1: CP0_CHECK(ctx->sc); gen_helper_mtc0_segctl1(cpu_env, arg); register_name =3D "SegCtl1"; break; - case 4: + case CP0_REG05__SEGCTL2: CP0_CHECK(ctx->sc); gen_helper_mtc0_segctl2(cpu_env, arg); register_name =3D "SegCtl2"; break; - case 5: + case CP0_REG05__PWBASE: check_pw(ctx); gen_mtc0_store32(arg, offsetof(CPUMIPSState, CP0_PWBase)); register_name =3D "PWBase"; break; - case 6: + case CP0_REG05__PWFIELD: check_pw(ctx); gen_helper_mtc0_pwfield(cpu_env, arg); register_name =3D "PWField"; break; - case 7: + case CP0_REG05__PWSIZE: check_pw(ctx); gen_helper_mtc0_pwsize(cpu_env, arg); register_name =3D "PWSize"; @@ -8534,41 +8534,41 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, = int reg, int sel) break; case CP0_REGISTER_05: switch (sel) { - case 0: + case CP0_REG05__PAGEMASK: gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PageMask)); register_name =3D "PageMask"; break; - case 1: + case CP0_REG05__PAGEGRAIN: check_insn(ctx, ISA_MIPS32R2); gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PageGrain)); register_name =3D "PageGrain"; break; - case 2: + case CP0_REG05__SEGCTL0: CP0_CHECK(ctx->sc); tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_SegCtl0= )); register_name =3D "SegCtl0"; break; - case 3: + case CP0_REG05__SEGCTL1: CP0_CHECK(ctx->sc); tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_SegCtl1= )); register_name =3D "SegCtl1"; break; - case 4: + case CP0_REG05__SEGCTL2: CP0_CHECK(ctx->sc); tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_SegCtl2= )); register_name =3D "SegCtl2"; break; - case 5: + case CP0_REG05__PWBASE: check_pw(ctx); tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_PWBase)= ); register_name =3D "PWBase"; break; - case 6: + case CP0_REG05__PWFIELD: check_pw(ctx); tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_PWField= )); register_name =3D "PWField"; break; - case 7: + case CP0_REG05__PWSIZE: check_pw(ctx); tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_PWSize)= ); register_name =3D "PWSize"; @@ -9255,41 +9255,41 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, = int reg, int sel) break; case CP0_REGISTER_05: switch (sel) { - case 0: + case CP0_REG05__PAGEMASK: gen_helper_mtc0_pagemask(cpu_env, arg); register_name =3D "PageMask"; break; - case 1: + case CP0_REG05__PAGEGRAIN: check_insn(ctx, ISA_MIPS32R2); gen_helper_mtc0_pagegrain(cpu_env, arg); register_name =3D "PageGrain"; break; - case 2: + case CP0_REG05__SEGCTL0: CP0_CHECK(ctx->sc); gen_helper_mtc0_segctl0(cpu_env, arg); register_name =3D "SegCtl0"; break; - case 3: + case CP0_REG05__SEGCTL1: CP0_CHECK(ctx->sc); gen_helper_mtc0_segctl1(cpu_env, arg); register_name =3D "SegCtl1"; break; - case 4: + case CP0_REG05__SEGCTL2: CP0_CHECK(ctx->sc); gen_helper_mtc0_segctl2(cpu_env, arg); register_name =3D "SegCtl2"; break; - case 5: + case CP0_REG05__PWBASE: check_pw(ctx); tcg_gen_st_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_PWBase)= ); register_name =3D "PWBase"; break; - case 6: + case CP0_REG05__PWFIELD: check_pw(ctx); gen_helper_mtc0_pwfield(cpu_env, arg); register_name =3D "PWField"; break; - case 7: + case CP0_REG05__PWSIZE: check_pw(ctx); gen_helper_mtc0_pwsize(cpu_env, arg); register_name =3D "PWSize"; --=20 2.7.4